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samplerjit: Decode colors with BMI2.
This only happens with nearest, though, so very small benefit.
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367525f875
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4cadcea6da
1 changed files with 124 additions and 71 deletions
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@ -3076,36 +3076,54 @@ bool SamplerJitCache::Jit_Decode5650(const SamplerID &id) {
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X64Reg temp1Reg = regCache_.Alloc(RegCache::GEN_TEMP1);
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X64Reg temp2Reg = regCache_.Alloc(RegCache::GEN_TEMP2);
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MOV(32, R(temp2Reg), R(resultReg));
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AND(32, R(temp2Reg), Imm32(0x0000001F));
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if (cpu_info.bBMI2_fast) {
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// Start off with the high bits.
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MOV(32, R(temp1Reg), Imm32(0x00F8FCF8));
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PDEP(32, temp1Reg, resultReg, R(temp1Reg));
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if (id.useTextureAlpha || id.fetch)
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OR(32, R(temp1Reg), Imm32(0xFF000000));
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// B (we do R and B at the same time, they're both 5.)
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MOV(32, R(temp1Reg), R(resultReg));
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AND(32, R(temp1Reg), Imm32(0x0000F800));
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SHL(32, R(temp1Reg), Imm8(5));
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OR(32, R(temp2Reg), R(temp1Reg));
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// Now grab the low bits (they end up packed.)
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MOV(32, R(temp2Reg), Imm32(0x0000E61C));
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PEXT(32, resultReg, resultReg, R(temp2Reg));
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// And spread them back out.
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MOV(32, R(temp2Reg), Imm32(0x00070307));
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PDEP(32, resultReg, resultReg, R(temp2Reg));
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// Expand 5 -> 8. At this point we have 00BB00RR.
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MOV(32, R(temp1Reg), R(temp2Reg));
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SHL(32, R(temp2Reg), Imm8(3));
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SHR(32, R(temp1Reg), Imm8(2));
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OR(32, R(temp2Reg), R(temp1Reg));
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AND(32, R(temp2Reg), Imm32(0x00FF00FF));
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// Finally put the high bits in, we're done.
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OR(32, R(resultReg), R(temp1Reg));
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} else {
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MOV(32, R(temp2Reg), R(resultReg));
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AND(32, R(temp2Reg), Imm32(0x0000001F));
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// Now's as good a time to put in A as any.
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if (id.useTextureAlpha || id.fetch)
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OR(32, R(temp2Reg), Imm32(0xFF000000));
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// B (we do R and B at the same time, they're both 5.)
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MOV(32, R(temp1Reg), R(resultReg));
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AND(32, R(temp1Reg), Imm32(0x0000F800));
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SHL(32, R(temp1Reg), Imm8(5));
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OR(32, R(temp2Reg), R(temp1Reg));
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// Last, we need to align, extract, and expand G.
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// 3 to align to G, and then 2 to expand to 8.
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SHL(32, R(resultReg), Imm8(3 + 2));
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AND(32, R(resultReg), Imm32(0x0000FC00));
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MOV(32, R(temp1Reg), R(resultReg));
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// 2 to account for resultReg being preshifted, 4 for expansion.
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SHR(32, R(temp1Reg), Imm8(2 + 4));
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OR(32, R(resultReg), R(temp1Reg));
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AND(32, R(resultReg), Imm32(0x0000FF00));
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OR(32, R(resultReg), R(temp2Reg));
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// Expand 5 -> 8. At this point we have 00BB00RR.
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MOV(32, R(temp1Reg), R(temp2Reg));
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SHL(32, R(temp2Reg), Imm8(3));
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SHR(32, R(temp1Reg), Imm8(2));
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OR(32, R(temp2Reg), R(temp1Reg));
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AND(32, R(temp2Reg), Imm32(0x00FF00FF));
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// Now's as good a time to put in A as any.
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if (id.useTextureAlpha || id.fetch)
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OR(32, R(temp2Reg), Imm32(0xFF000000));
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// Last, we need to align, extract, and expand G.
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// 3 to align to G, and then 2 to expand to 8.
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SHL(32, R(resultReg), Imm8(3 + 2));
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AND(32, R(resultReg), Imm32(0x0000FC00));
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MOV(32, R(temp1Reg), R(resultReg));
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// 2 to account for resultReg being preshifted, 4 for expansion.
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SHR(32, R(temp1Reg), Imm8(2 + 4));
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OR(32, R(resultReg), R(temp1Reg));
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AND(32, R(resultReg), Imm32(0x0000FF00));
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OR(32, R(resultReg), R(temp2Reg));
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}
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regCache_.Release(temp1Reg, RegCache::GEN_TEMP1);
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regCache_.Release(temp2Reg, RegCache::GEN_TEMP2);
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@ -3154,34 +3172,54 @@ bool SamplerJitCache::Jit_Decode5551(const SamplerID &id) {
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X64Reg temp1Reg = regCache_.Alloc(RegCache::GEN_TEMP1);
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X64Reg temp2Reg = regCache_.Alloc(RegCache::GEN_TEMP2);
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MOV(32, R(temp2Reg), R(resultReg));
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MOV(32, R(temp1Reg), R(resultReg));
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AND(32, R(temp2Reg), Imm32(0x0000001F));
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AND(32, R(temp1Reg), Imm32(0x000003E0));
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SHL(32, R(temp1Reg), Imm8(3));
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OR(32, R(temp2Reg), R(temp1Reg));
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if (cpu_info.bBMI2_fast) {
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// First, grab the top bits.
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bool keepAlpha = id.useTextureAlpha || id.fetch;
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MOV(32, R(temp1Reg), Imm32(keepAlpha ? 0x01F8F8F8 : 0x00F8F8F8));
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PDEP(32, resultReg, resultReg, R(temp1Reg));
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MOV(32, R(temp1Reg), R(resultReg));
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AND(32, R(temp1Reg), Imm32(0x00007C00));
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SHL(32, R(temp1Reg), Imm8(6));
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OR(32, R(temp2Reg), R(temp1Reg));
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// Now make the swizzle bits.
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MOV(32, R(temp2Reg), R(resultReg));
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SHR(32, R(temp2Reg), Imm8(5));
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AND(32, R(temp2Reg), Imm32(0x00070707));
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// Expand 5 -> 8. After this is just A.
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MOV(32, R(temp1Reg), R(temp2Reg));
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SHL(32, R(temp2Reg), Imm8(3));
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SHR(32, R(temp1Reg), Imm8(2));
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// Chop off the bits that were shifted out.
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AND(32, R(temp1Reg), Imm32(0x00070707));
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OR(32, R(temp2Reg), R(temp1Reg));
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if (keepAlpha) {
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// Sign extend the alpha bit to 8 bits.
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SHL(32, R(resultReg), Imm8(7));
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SAR(32, R(resultReg), Imm8(7));
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}
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if (id.useTextureAlpha || id.fetch) {
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// For A, we sign extend to get either 16 1s or 0s of alpha.
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SAR(16, R(resultReg), Imm8(15));
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// Now, shift left by 24 to get the lowest 8 of those at the top.
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SHL(32, R(resultReg), Imm8(24));
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OR(32, R(resultReg), R(temp2Reg));
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} else {
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MOV(32, R(resultReg), R(temp2Reg));
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MOV(32, R(temp2Reg), R(resultReg));
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MOV(32, R(temp1Reg), R(resultReg));
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AND(32, R(temp2Reg), Imm32(0x0000001F));
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AND(32, R(temp1Reg), Imm32(0x000003E0));
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SHL(32, R(temp1Reg), Imm8(3));
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OR(32, R(temp2Reg), R(temp1Reg));
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MOV(32, R(temp1Reg), R(resultReg));
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AND(32, R(temp1Reg), Imm32(0x00007C00));
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SHL(32, R(temp1Reg), Imm8(6));
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OR(32, R(temp2Reg), R(temp1Reg));
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// Expand 5 -> 8. After this is just A.
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MOV(32, R(temp1Reg), R(temp2Reg));
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SHL(32, R(temp2Reg), Imm8(3));
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SHR(32, R(temp1Reg), Imm8(2));
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// Chop off the bits that were shifted out.
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AND(32, R(temp1Reg), Imm32(0x00070707));
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OR(32, R(temp2Reg), R(temp1Reg));
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if (id.useTextureAlpha || id.fetch) {
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// For A, we sign extend to get either 16 1s or 0s of alpha.
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SAR(16, R(resultReg), Imm8(15));
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// Now, shift left by 24 to get the lowest 8 of those at the top.
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SHL(32, R(resultReg), Imm8(24));
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OR(32, R(resultReg), R(temp2Reg));
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} else {
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MOV(32, R(resultReg), R(temp2Reg));
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}
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}
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regCache_.Release(temp1Reg, RegCache::GEN_TEMP1);
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@ -3235,31 +3273,46 @@ alignas(16) static const u32 color4444mask[4] = { 0xf00ff00f, 0xf00ff00f, 0xf00f
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bool SamplerJitCache::Jit_Decode4444(const SamplerID &id) {
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Describe("4444");
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X64Reg resultReg = regCache_.Find(RegCache::GEN_RESULT);
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X64Reg vecTemp1Reg = regCache_.Alloc(RegCache::VEC_TEMP1);
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X64Reg vecTemp2Reg = regCache_.Alloc(RegCache::VEC_TEMP2);
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X64Reg vecTemp3Reg = regCache_.Alloc(RegCache::VEC_TEMP3);
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MOVD_xmm(vecTemp1Reg, R(resultReg));
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PUNPCKLBW(vecTemp1Reg, R(vecTemp1Reg));
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if (RipAccessible(color4444mask)) {
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PAND(vecTemp1Reg, M(color4444mask));
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} else {
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if (cpu_info.bBMI2_fast) {
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X64Reg temp1Reg = regCache_.Alloc(RegCache::GEN_TEMP1);
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MOV(PTRBITS, R(temp1Reg), ImmPtr(color4444mask));
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PAND(vecTemp1Reg, MatR(temp1Reg));
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regCache_.Release(temp1Reg, RegCache::GEN_TEMP1);
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}
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MOVSS(vecTemp2Reg, R(vecTemp1Reg));
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MOVSS(vecTemp3Reg, R(vecTemp1Reg));
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PSRLW(vecTemp2Reg, 4);
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PSLLW(vecTemp3Reg, 4);
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POR(vecTemp1Reg, R(vecTemp2Reg));
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POR(vecTemp1Reg, R(vecTemp3Reg));
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MOVD_xmm(R(resultReg), vecTemp1Reg);
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// First, spread the bits out with spaces.
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MOV(32, R(temp1Reg), Imm32(0xF0F0F0F0));
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PDEP(32, resultReg, resultReg, R(temp1Reg));
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regCache_.Release(vecTemp1Reg, RegCache::VEC_TEMP1);
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regCache_.Release(vecTemp2Reg, RegCache::VEC_TEMP2);
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regCache_.Release(vecTemp3Reg, RegCache::VEC_TEMP3);
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// Now swizzle the low bits in.
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MOV(32, R(temp1Reg), R(resultReg));
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SHR(32, R(temp1Reg), Imm8(4));
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OR(32, R(resultReg), R(temp1Reg));
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regCache_.Release(temp1Reg, RegCache::GEN_TEMP1);
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} else {
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X64Reg vecTemp1Reg = regCache_.Alloc(RegCache::VEC_TEMP1);
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X64Reg vecTemp2Reg = regCache_.Alloc(RegCache::VEC_TEMP2);
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X64Reg vecTemp3Reg = regCache_.Alloc(RegCache::VEC_TEMP3);
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MOVD_xmm(vecTemp1Reg, R(resultReg));
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PUNPCKLBW(vecTemp1Reg, R(vecTemp1Reg));
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if (RipAccessible(color4444mask)) {
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PAND(vecTemp1Reg, M(color4444mask));
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} else {
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X64Reg temp1Reg = regCache_.Alloc(RegCache::GEN_TEMP1);
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MOV(PTRBITS, R(temp1Reg), ImmPtr(color4444mask));
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PAND(vecTemp1Reg, MatR(temp1Reg));
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regCache_.Release(temp1Reg, RegCache::GEN_TEMP1);
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}
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MOVSS(vecTemp2Reg, R(vecTemp1Reg));
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MOVSS(vecTemp3Reg, R(vecTemp1Reg));
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PSRLW(vecTemp2Reg, 4);
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PSLLW(vecTemp3Reg, 4);
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POR(vecTemp1Reg, R(vecTemp2Reg));
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POR(vecTemp1Reg, R(vecTemp3Reg));
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MOVD_xmm(R(resultReg), vecTemp1Reg);
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regCache_.Release(vecTemp1Reg, RegCache::VEC_TEMP1);
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regCache_.Release(vecTemp2Reg, RegCache::VEC_TEMP2);
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regCache_.Release(vecTemp3Reg, RegCache::VEC_TEMP3);
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}
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regCache_.Unlock(resultReg, RegCache::GEN_RESULT);
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return true;
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}
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