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Merge pull request #7679 from unknownbrackets/ir-parts

Browse source 
More parts of the jit-ir branch
This commit is contained in:
Henrik Rydgård 2015-04-12 21:40:01 +02:00
commit 45f259178b
25 changed files with 201 additions and 205 deletions
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2
CMakeLists.txt
View file

@ -1342,6 +1342,8 @@ add_library(${CoreLibName} ${CoreLinkType}
Core/MIPS/JitCommon/NativeJit.h
Core/MIPS/JitCommon/JitBlockCache.cpp
Core/MIPS/JitCommon/JitBlockCache.h
Core/MIPS/JitCommon/JitState.cpp
Core/MIPS/JitCommon/JitState.h
Core/MIPS/MIPS.cpp
Core/MIPS/MIPS.h
Core/MIPS/MIPSAnalyst.cpp

39
Core/Core.vcxproj
View file

@ -415,17 +415,24 @@
</ClCompile>
<ClCompile Include="MIPS\JitCommon\JitBlockCache.cpp" />
<ClCompile Include="MIPS\JitCommon\JitCommon.cpp" />
<ClCompile Include="Mips\MIPS.cpp" />
<ClCompile Include="Mips\MIPSAnalyst.cpp" />
<ClCompile Include="MIPS\JitCommon\JitState.cpp" />
<ClCompile Include="MIPS\MIPS.cpp" />
<ClCompile Include="MIPS\MIPSAnalyst.cpp" />
<ClCompile Include="MIPS\MIPSAsm.cpp" />
<ClCompile Include="Mips\MIPSCodeUtils.cpp" />
<ClCompile Include="MIPS\MIPSCodeUtils.cpp" />
<ClCompile Include="MIPS\MIPSDebugInterface.cpp" />
<ClCompile Include="Mips\MIPSDis.cpp" />
<ClCompile Include="MIPS\MIPSDis.cpp" />
<ClCompile Include="MIPS\MIPSDisVFPU.cpp" />
<ClCompile Include="Mips\MIPSInt.cpp" />
<ClCompile Include="MIPS\MIPSInt.cpp" />
<ClCompile Include="MIPS\MIPSIntVFPU.cpp" />
<ClCompile Include="Mips\MIPSTables.cpp" />
<ClCompile Include="MIPS\MIPSTables.cpp" />
<ClCompile Include="MIPS\MIPSVFPUUtils.cpp" />
<ClCompile Include="MIPS\MIPS\MipsJit.cpp">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClCompile>
<ClCompile Include="MIPS\x86\Asm.cpp" />
<ClCompile Include="MIPS\x86\CompALU.cpp" />
<ClCompile Include="MIPS\x86\CompBranch.cpp" />
@ -654,17 +661,23 @@
<ClInclude Include="MIPS\JitCommon\JitCommon.h" />
<ClInclude Include="MIPS\JitCommon\NativeJit.h" />
<ClInclude Include="MIPS\JitCommon\JitState.h" />
<ClInclude Include="Mips\MIPS.h" />
<ClInclude Include="Mips\MIPSAnalyst.h" />
<ClInclude Include="MIPS\MIPS.h" />
<ClInclude Include="MIPS\MIPSAnalyst.h" />
<ClInclude Include="MIPS\MIPSAsm.h" />
<ClInclude Include="Mips\MIPSCodeUtils.h" />
<ClInclude Include="MIPS\MIPSCodeUtils.h" />
<ClInclude Include="MIPS\MIPSDebugInterface.h" />
<ClInclude Include="Mips\MIPSDis.h" />
<ClInclude Include="MIPS\MIPSDis.h" />
<ClInclude Include="MIPS\MIPSDisVFPU.h" />
<ClInclude Include="Mips\MIPSInt.h" />
<ClInclude Include="MIPS\MIPSInt.h" />
<ClInclude Include="MIPS\MIPSIntVFPU.h" />
<ClInclude Include="Mips\MIPSTables.h" />
<ClInclude Include="MIPS\MIPSTables.h" />
<ClInclude Include="MIPS\MIPSVFPUUtils.h" />
<ClInclude Include="MIPS\MIPS\MipsJit.h">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">true</ExcludedFromBuild>
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Release|x64'">true</ExcludedFromBuild>
</ClInclude>
<ClInclude Include="MIPS\x86\Asm.h" />
<ClInclude Include="MIPS\x86\JitSafeMem.h" />
<ClInclude Include="MIPS\x86\RegCacheFPU.h" />
@ -718,4 +731,4 @@
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>
</Project>
</Project>

38
Core/Core.vcxproj.filters
View file

@ -13,6 +13,9 @@
<Filter Include="MIPS\ARM">
<UniqueIdentifier>{8a5bebeb-575f-483d-8bd2-4b7eac163a7d}</UniqueIdentifier>
</Filter>
<Filter Include="MIPS\MIPS">
<UniqueIdentifier>{aaaaaaaa-575f-483d-8bd2-4b7eac163a7d}</UniqueIdentifier>
</Filter>
<Filter Include="MIPS\JitCommon">
<UniqueIdentifier>{37896407-c373-44a3-b6ec-b57bceb2c4a3}</UniqueIdentifier>
</Filter>
@ -66,34 +69,34 @@
<ClCompile Include="ELF\ElfReader.cpp">
<Filter>ELF</Filter>
</ClCompile>
<ClCompile Include="Mips\MIPS.cpp">
<ClCompile Include="MIPS\MIPS.cpp">
<Filter>MIPS</Filter>
</ClCompile>
<ClCompile Include="MIPS\MIPSDebugInterface.cpp">
<Filter>MIPS</Filter>
</ClCompile>
<ClCompile Include="Mips\MIPSDis.cpp">
<ClCompile Include="MIPS\MIPSDis.cpp">
<Filter>MIPS</Filter>
</ClCompile>
<ClCompile Include="MIPS\MIPSDisVFPU.cpp">
<Filter>MIPS</Filter>
</ClCompile>
<ClCompile Include="Mips\MIPSInt.cpp">
<ClCompile Include="MIPS\MIPSInt.cpp">
<Filter>MIPS</Filter>
</ClCompile>
<ClCompile Include="MIPS\MIPSIntVFPU.cpp">
<Filter>MIPS</Filter>
</ClCompile>
<ClCompile Include="Mips\MIPSTables.cpp">
<ClCompile Include="MIPS\MIPSTables.cpp">
<Filter>MIPS</Filter>
</ClCompile>
<ClCompile Include="MIPS\MIPSVFPUUtils.cpp">
<Filter>MIPS</Filter>
</ClCompile>
<ClCompile Include="Mips\MIPSAnalyst.cpp">
<ClCompile Include="MIPS\MIPSAnalyst.cpp">
<Filter>MIPS</Filter>
</ClCompile>
<ClCompile Include="Mips\MIPSCodeUtils.cpp">
<ClCompile Include="MIPS\MIPSCodeUtils.cpp">
<Filter>MIPS</Filter>
</ClCompile>
<ClCompile Include="MIPS\x86\CompALU.cpp">
@ -402,6 +405,9 @@
<ClCompile Include="MIPS\ARM\ArmJit.cpp">
<Filter>MIPS\ARM</Filter>
</ClCompile>
<ClCompile Include="MIPS\ARM\MipsJit.cpp">
<Filter>MIPS\MIPS</Filter>
</ClCompile>
<ClCompile Include="MIPS\ARM\ArmRegCache.cpp">
<Filter>MIPS\ARM</Filter>
</ClCompile>
@ -593,6 +599,9 @@
<ClCompile Include="Util\DisArm64.cpp">
<Filter>Util</Filter>
</ClCompile>
<ClCompile Include="MIPS\JitCommon\JitState.cpp">
<Filter>MIPS\JitCommon</Filter>
</ClCompile>
</ItemGroup>
<ItemGroup>
<ClInclude Include="ELF\ElfReader.h">
@ -604,31 +613,31 @@
<ClInclude Include="MIPS\MIPSDebugInterface.h">
<Filter>MIPS</Filter>
</ClInclude>
<ClInclude Include="Mips\MIPS.h">
<ClInclude Include="MIPS\MIPS.h">
<Filter>MIPS</Filter>
</ClInclude>
<ClInclude Include="Mips\MIPSDis.h">
<ClInclude Include="MIPS\MIPSDis.h">
<Filter>MIPS</Filter>
</ClInclude>
<ClInclude Include="MIPS\MIPSDisVFPU.h">
<Filter>MIPS</Filter>
</ClInclude>
<ClInclude Include="Mips\MIPSInt.h">
<ClInclude Include="MIPS\MIPSInt.h">
<Filter>MIPS</Filter>
</ClInclude>
<ClInclude Include="MIPS\MIPSIntVFPU.h">
<Filter>MIPS</Filter>
</ClInclude>
<ClInclude Include="Mips\MIPSTables.h">
<ClInclude Include="MIPS\MIPSTables.h">
<Filter>MIPS</Filter>
</ClInclude>
<ClInclude Include="MIPS\MIPSVFPUUtils.h">
<Filter>MIPS</Filter>
</ClInclude>
<ClInclude Include="Mips\MIPSAnalyst.h">
<ClInclude Include="MIPS\MIPSAnalyst.h">
<Filter>MIPS</Filter>
</ClInclude>
<ClInclude Include="Mips\MIPSCodeUtils.h">
<ClInclude Include="MIPS\MIPSCodeUtils.h">
<Filter>MIPS</Filter>
</ClInclude>
<ClInclude Include="MIPS\x86\Jit.h">
@ -931,6 +940,9 @@
<ClInclude Include="MIPS\ARM\ArmJit.h">
<Filter>MIPS\ARM</Filter>
</ClInclude>
<ClInclude Include="MIPS\MIPS\MipsJit.h">
<Filter>MIPS\MIPS</Filter>
</ClInclude>
<ClInclude Include="MIPS\ARM\ArmRegCache.h">
<Filter>MIPS\ARM</Filter>
</ClInclude>
@ -1122,4 +1134,4 @@
<None Include="..\android\jni\Android.mk" />
<None Include="GameLogNotes.txt" />
</ItemGroup>
</Project>
</Project>

10
Core/MIPS/ARM/ArmCompVFPUNEON.cpp
View file

@ -286,7 +286,7 @@ void ArmJit::CompNEON_SVQ(MIPSOpcode op) {
op.encoding,
GetOffsetInstruction(1).encoding,
GetOffsetInstruction(2).encoding,
GetOffsetInstruction(3).encoding
GetOffsetInstruction(3).encoding,
};
if (g_Config.bFastMemory && (ops[1] >> 26) == 54 && (ops[2] >> 26) == 54 && (ops[3] >> 26) == 54) {
int offsets[4] = {offset, (s16)(ops[1] & 0xFFFC), (s16)(ops[2] & 0xFFFC), (s16)(ops[3] & 0xFFFC)};
@ -294,8 +294,7 @@ void ArmJit::CompNEON_SVQ(MIPSOpcode op) {
if (offsets[1] == offset + 16 && offsets[2] == offsets[1] + 16 && offsets[3] == offsets[2] + 16 &&
rss[0] == rss[1] && rss[1] == rss[2] && rss[2] == rss[3]) {
int vts[4] = {MIPS_GET_VQVT(op.encoding), MIPS_GET_VQVT(ops[1]), MIPS_GET_VQVT(ops[2]), MIPS_GET_VQVT(ops[3])};
// Also check the destination registers!
// TODO: Also check the destination registers!
// Detected four consecutive ones!
// gpr.MapRegAsPointer(rs);
// fpr.QLoad4x4(vts[4], rs, offset);
@ -352,7 +351,7 @@ void ArmJit::CompNEON_SVQ(MIPSOpcode op) {
op.encoding,
GetOffsetInstruction(1).encoding,
GetOffsetInstruction(2).encoding,
GetOffsetInstruction(3).encoding
GetOffsetInstruction(3).encoding,
};
if (g_Config.bFastMemory && (ops[1] >> 26) == 54 && (ops[2] >> 26) == 54 && (ops[3] >> 26) == 54) {
int offsets[4] = { offset, (s16)(ops[1] & 0xFFFC), (s16)(ops[2] & 0xFFFC), (s16)(ops[3] & 0xFFFC) };
@ -360,8 +359,7 @@ void ArmJit::CompNEON_SVQ(MIPSOpcode op) {
if (offsets[1] == offset + 16 && offsets[2] == offsets[1] + 16 && offsets[3] == offsets[2] + 16 &&
rss[0] == rss[1] && rss[1] == rss[2] && rss[2] == rss[3]) {
int vts[4] = { MIPS_GET_VQVT(op.encoding), MIPS_GET_VQVT(ops[1]), MIPS_GET_VQVT(ops[2]), MIPS_GET_VQVT(ops[3]) };
// Also check the destination registers!
// TODO: Also check the destination registers!
// Detected four consecutive ones!
// gpr.MapRegAsPointer(rs);
// fpr.QLoad4x4(vts[4], rs, offset);

32
Core/MIPS/ARM/ArmJit.h
View file

@ -34,36 +34,6 @@
namespace MIPSComp
{
struct ArmJitOptions
{
ArmJitOptions() {
enableBlocklink = true;
downcountInRegister = true;
useBackJump = false;
useForwardJump = false;
cachePointers = true;
immBranches = false;
continueBranches = false;
continueJumps = false;
continueMaxInstructions = 300;
useNEONVFPU = false; // true
if (!cpu_info.bNEON)
useNEONVFPU = false;
}
bool useNEONVFPU;
bool enableBlocklink;
bool downcountInRegister;
bool useBackJump;
bool useForwardJump;
bool cachePointers;
bool immBranches;
bool continueBranches;
bool continueJumps;
int continueMaxInstructions;
};
class ArmJit : public ArmGen::ARMXCodeBlock
{
public:
@ -305,7 +275,7 @@ private:
void Comp_ITypeMemLR(MIPSOpcode op, bool load);
JitBlockCache blocks;
ArmJitOptions jo;
JitOptions jo;
JitState js;
ArmRegCache gpr;

2
Core/MIPS/ARM/ArmRegCache.cpp
View file

@ -29,7 +29,7 @@
using namespace ArmGen;
using namespace ArmJitConstants;
ArmRegCache::ArmRegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::ArmJitOptions *jo) : mips_(mips), js_(js), jo_(jo) {
ArmRegCache::ArmRegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo) : mips_(mips), js_(js), jo_(jo) {
}
void ArmRegCache::Init(ARMXEmitter *emitter) {

6
Core/MIPS/ARM/ArmRegCache.h
View file

@ -82,13 +82,13 @@ struct RegMIPS {
};
namespace MIPSComp {
struct ArmJitOptions;
struct JitOptions;
struct JitState;
}
class ArmRegCache {
public:
ArmRegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::ArmJitOptions *jo);
ArmRegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo);
~ArmRegCache() {}
void Init(ArmGen::ARMXEmitter *emitter);
@ -143,7 +143,7 @@ private:
MIPSState *mips_;
ArmGen::ARMXEmitter *emit_;
MIPSComp::JitState *js_;
MIPSComp::ArmJitOptions *jo_;
MIPSComp::JitOptions *jo_;
u32 compilerPC_;
enum {

2
Core/MIPS/ARM/ArmRegCacheFPU.cpp
View file

@ -27,7 +27,7 @@
using namespace ArmGen;
using namespace ArmJitConstants;
ArmRegCacheFPU::ArmRegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::ArmJitOptions *jo) : mips_(mips), vr(mr + 32), js_(js), jo_(jo), initialReady(false) {
ArmRegCacheFPU::ArmRegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo) : mips_(mips), vr(mr + 32), js_(js), jo_(jo), initialReady(false) {
if (cpu_info.bNEON) {
numARMFpuReg_ = 32;
} else {

6
Core/MIPS/ARM/ArmRegCacheFPU.h
View file

@ -77,13 +77,13 @@ struct FPURegMIPS {
};
namespace MIPSComp {
struct ArmJitOptions;
struct JitOptions;
struct JitState;
}
class ArmRegCacheFPU {
public:
ArmRegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::ArmJitOptions *jo);
ArmRegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo);
~ArmRegCacheFPU() {}
void Init(ArmGen::ARMXEmitter *emitter);
@ -191,7 +191,7 @@ private:
MIPSState *mips_;
ArmGen::ARMXEmitter *emit_;
MIPSComp::JitState *js_;
MIPSComp::ArmJitOptions *jo_;
MIPSComp::JitOptions *jo_;
int numARMFpuReg_;
int qTime_;

28
Core/MIPS/ARM64/Arm64Jit.h
View file

@ -34,32 +34,6 @@
namespace MIPSComp
{
struct Arm64JitOptions
{
Arm64JitOptions() {
enableBlocklink = true;
useBackJump = false;
useForwardJump = false;
cachePointers = true;
immBranches = false;
continueBranches = false;
continueJumps = false;
continueMaxInstructions = 300;
useASIMDVFPU = false; // true
}
bool useASIMDVFPU;
bool enableBlocklink;
bool useBackJump;
bool useForwardJump;
bool cachePointers;
bool immBranches;
bool continueBranches;
bool continueJumps;
int continueMaxInstructions;
};
class Arm64Jit : public Arm64Gen::ARM64CodeBlock
{
public:
@ -263,7 +237,7 @@ private:
void Comp_ITypeMemLR(MIPSOpcode op, bool load);
JitBlockCache blocks;
Arm64JitOptions jo;
JitOptions jo;
JitState js;
Arm64RegCache gpr;

2
Core/MIPS/ARM64/Arm64RegCache.cpp
View file

@ -29,7 +29,7 @@
using namespace Arm64Gen;
using namespace Arm64JitConstants;
Arm64RegCache::Arm64RegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::Arm64JitOptions *jo) : mips_(mips), js_(js), jo_(jo) {
Arm64RegCache::Arm64RegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo) : mips_(mips), js_(js), jo_(jo) {
}
void Arm64RegCache::Init(ARM64XEmitter *emitter) {

6
Core/MIPS/ARM64/Arm64RegCache.h
View file

@ -85,13 +85,13 @@ struct RegMIPS {
};
namespace MIPSComp {
struct Arm64JitOptions;
struct JitOptions;
struct JitState;
}
class Arm64RegCache {
public:
Arm64RegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::Arm64JitOptions *jo);
Arm64RegCache(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo);
~Arm64RegCache() {}
void Init(Arm64Gen::ARM64XEmitter *emitter);
@ -146,7 +146,7 @@ private:
MIPSState *mips_;
Arm64Gen::ARM64XEmitter *emit_;
MIPSComp::JitState *js_;
MIPSComp::Arm64JitOptions *jo_;
MIPSComp::JitOptions *jo_;
u32 compilerPC_;
enum {

2
Core/MIPS/ARM64/Arm64RegCacheFPU.cpp
View file

@ -27,7 +27,7 @@
using namespace Arm64Gen;
using namespace Arm64JitConstants;
Arm64RegCacheFPU::Arm64RegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::Arm64JitOptions *jo) : mips_(mips), vr(mr + 32), js_(js), jo_(jo), initialReady(false) {
Arm64RegCacheFPU::Arm64RegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo) : mips_(mips), vr(mr + 32), js_(js), jo_(jo), initialReady(false) {
numARMFpuReg_ = 32;
}

6
Core/MIPS/ARM64/Arm64RegCacheFPU.h
View file

@ -77,13 +77,13 @@ struct FPURegMIPS {
};
namespace MIPSComp {
struct Arm64JitOptions;
struct JitOptions;
struct JitState;
}
class Arm64RegCacheFPU {
public:
Arm64RegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::Arm64JitOptions *jo);
Arm64RegCacheFPU(MIPSState *mips, MIPSComp::JitState *js, MIPSComp::JitOptions *jo);
~Arm64RegCacheFPU() {}
void Init(Arm64Gen::ARM64XEmitter *emitter, Arm64Gen::ARM64FloatEmitter *fp);
@ -159,7 +159,7 @@ private:
Arm64Gen::ARM64XEmitter *emit_;
Arm64Gen::ARM64FloatEmitter *fp_;
MIPSComp::JitState *js_;
MIPSComp::Arm64JitOptions *jo_;
MIPSComp::JitOptions *jo_;
int numARMFpuReg_;
int qTime_;

49
Core/MIPS/JitCommon/JitState.cpp Normal file
View file

@ -0,0 +1,49 @@
// Copyright (c) 2013- PPSSPP Project.
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, version 2.0 or later versions.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License 2.0 for more details.
// A copy of the GPL 2.0 should have been included with the program.
// If not, see http://www.gnu.org/licenses/
// Official git repository and contact information can be found at
// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
#include "Common/CPUDetect.h"
#include "Core/MIPS/JitCommon/JitState.h"
namespace MIPSComp {
JitOptions::JitOptions() {
// x86
enableVFPUSIMD = true;
// Set by Asm if needed.
reserveR15ForAsm = false;
// ARM/ARM64
useBackJump = false;
useForwardJump = false;
cachePointers = true;
// ARM only
downcountInRegister = true;
useNEONVFPU = false; // true
if (!cpu_info.bNEON)
useNEONVFPU = false;
//ARM64
useASIMDVFPU = false; // true
// Common
enableBlocklink = true;
immBranches = false;
continueBranches = false;
continueJumps = false;
continueMaxInstructions = 300;
}
}

25
Core/MIPS/JitCommon/JitState.h
View file

@ -175,4 +175,29 @@ namespace MIPSComp {
}
}
};
struct JitOptions {
JitOptions();
// x86
bool enableVFPUSIMD;
bool reserveR15ForAsm;
// ARM/ARM64
bool useBackJump;
bool useForwardJump;
bool cachePointers;
// ARM only
bool useNEONVFPU;
bool downcountInRegister;
// ARM64 only
bool useASIMDVFPU;
// Common
bool enableBlocklink;
bool immBranches;
bool continueBranches;
bool continueJumps;
int continueMaxInstructions;
};
}

6
Core/MIPS/JitCommon/NativeJit.h
View file

@ -34,10 +34,7 @@ typedef MIPSComp::Arm64Jit NativeJit;
typedef MIPSComp::Jit NativeJit;
#elif defined(MIPS)
#include "../MIPS/MipsJit.h"
typedef MIPSComp::Jit NativeJit;
//#elif defined(ARM64)
//#include "../ARM64/Arm64Jit.h"
//typedef MIPSComp::Arm64Jit NativeJit;
typedef MIPSComp::MipsJit NativeJit;
#else
#include "../fake/FakeJit.h"
typedef MIPSComp::FakeJit NativeJit;
@ -48,5 +45,4 @@ namespace MIPSComp {
typedef void (NativeJit::*MIPSCompileFunc)(MIPSOpcode opcode);
typedef int (NativeJit::*MIPSReplaceFunc)();
}

70
Core/MIPS/MIPS/MipsJit.cpp
View file

@ -38,15 +38,7 @@ void DisassembleMIPS(const u8 *data, int size) {
namespace MIPSComp
{
MIPSJitOptions::MIPSJitOptions() {
enableBlocklink = true;
immBranches = false;
continueBranches = false;
continueJumps = false;
continueMaxInstructions = 300;
}
Jit::Jit(MIPSState *mips) : blocks(mips, this), mips_(mips)
MipsJit::MipsJit(MIPSState *mips) : blocks(mips, this), mips_(mips)
{
logBlocks = 0;
dontLogBlocks = 0;
@ -55,7 +47,7 @@ Jit::Jit(MIPSState *mips) : blocks(mips, this), mips_(mips)
js.startDefaultPrefix = mips_->HasDefaultPrefix();
}
void Jit::DoState(PointerWrap &p)
void MipsJit::DoState(PointerWrap &p)
{
auto s = p.Section("Jit", 1, 2);
if (!s)
@ -71,7 +63,7 @@ void Jit::DoState(PointerWrap &p)
}
// This is here so the savestate matches between jit and non-jit.
void Jit::DoDummyState(PointerWrap &p)
void MipsJit::DoDummyState(PointerWrap &p)
{
auto s = p.Section("Jit", 1, 2);
if (!s)
@ -85,35 +77,35 @@ void Jit::DoDummyState(PointerWrap &p)
}
}
void Jit::FlushAll()
void MipsJit::FlushAll()
{
//gpr.FlushAll();
//fpr.FlushAll();
FlushPrefixV();
}
void Jit::FlushPrefixV()
void MipsJit::FlushPrefixV()
{
}
void Jit::ClearCache()
void MipsJit::ClearCache()
{
blocks.Clear();
ClearCodeSpace();
//GenerateFixedCode();
}
void Jit::InvalidateCache()
void MipsJit::InvalidateCache()
{
blocks.Clear();
}
void Jit::InvalidateCacheAt(u32 em_address, int length)
void MipsJit::InvalidateCacheAt(u32 em_address, int length)
{
blocks.InvalidateICache(em_address, length);
}
void Jit::EatInstruction(MIPSOpcode op) {
void MipsJit::EatInstruction(MIPSOpcode op) {
MIPSInfo info = MIPSGetInfo(op);
if (info & DELAYSLOT) {
ERROR_LOG_REPORT_ONCE(ateDelaySlot, JIT, "Ate a branch op.");
@ -127,7 +119,7 @@ void Jit::EatInstruction(MIPSOpcode op) {
js.downcountAmount += MIPSGetInstructionCycleEstimate(op);
}
void Jit::CompileDelaySlot(int flags)
void MipsJit::CompileDelaySlot(int flags)
{
//if (flags & DELAYSLOT_SAFE)
// Save flags here
@ -144,7 +136,7 @@ void Jit::CompileDelaySlot(int flags)
}
void Jit::Compile(u32 em_address) {
void MipsJit::Compile(u32 em_address) {
if (GetSpaceLeft() < 0x10000 || blocks.IsFull()) {
ClearCache();
}
@ -169,12 +161,12 @@ void Jit::Compile(u32 em_address) {
}
}
void Jit::RunLoopUntil(u64 globalticks)
void MipsJit::RunLoopUntil(u64 globalticks)
{
((void (*)())enterCode)();
}
const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
const u8 *MipsJit::DoJit(u32 em_address, JitBlock *b)
{
js.cancel = false;
js.blockStart = js.compilerPC = mips_->pc;
@ -224,7 +216,7 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b)
return b->normalEntry;
}
void Jit::AddContinuedBlock(u32 dest)
void MipsJit::AddContinuedBlock(u32 dest)
{
// The first block is the root block. When we continue, we create proxy blocks after that.
if (js.lastContinuedPC == 0)
@ -234,27 +226,27 @@ void Jit::AddContinuedBlock(u32 dest)
js.lastContinuedPC = dest;
}
bool Jit::DescribeCodePtr(const u8 *ptr, std::string &name)
bool MipsJit::DescribeCodePtr(const u8 *ptr, std::string &name)
{
// TODO: Not used by anything yet.
return false;
}
void Jit::Comp_RunBlock(MIPSOpcode op)
void MipsJit::Comp_RunBlock(MIPSOpcode op)
{
// This shouldn't be necessary, the dispatcher should catch us before we get here.
ERROR_LOG(JIT, "Comp_RunBlock should never be reached!");
}
bool Jit::ReplaceJalTo(u32 dest) {
bool MipsJit::ReplaceJalTo(u32 dest) {
return true;
}
void Jit::Comp_ReplacementFunc(MIPSOpcode op)
void MipsJit::Comp_ReplacementFunc(MIPSOpcode op)
{
}
void Jit::Comp_Generic(MIPSOpcode op)
void MipsJit::Comp_Generic(MIPSOpcode op)
{
FlushAll();
MIPSInterpretFunc func = MIPSGetInterpretFunc(op);
@ -277,34 +269,34 @@ void Jit::Comp_Generic(MIPSOpcode op)
}
}
void Jit::MovFromPC(MIPSReg r) {
void MipsJit::MovFromPC(MIPSReg r) {
}
void Jit::MovToPC(MIPSReg r) {
void MipsJit::MovToPC(MIPSReg r) {
}
void Jit::SaveDowncount() {
void MipsJit::SaveDowncount() {
}
void Jit::RestoreDowncount() {
void MipsJit::RestoreDowncount() {
}
void Jit::WriteDownCount(int offset) {
void MipsJit::WriteDownCount(int offset) {
}
void Jit::WriteDownCountR(MIPSReg reg) {
void MipsJit::WriteDownCountR(MIPSReg reg) {
}
void Jit::RestoreRoundingMode(bool force) {
void MipsJit::RestoreRoundingMode(bool force) {
}
void Jit::ApplyRoundingMode(bool force) {
void MipsJit::ApplyRoundingMode(bool force) {
}
void Jit::UpdateRoundingMode() {
void MipsJit::UpdateRoundingMode() {
}
void Jit::WriteExit(u32 destination, int exit_num)
void MipsJit::WriteExit(u32 destination, int exit_num)
{
//WriteDownCount();
JitBlock *b = js.curBlock;
@ -323,7 +315,7 @@ void Jit::WriteExit(u32 destination, int exit_num)
}
}
void Jit::WriteExitDestInR(MIPSReg Reg)
void MipsJit::WriteExitDestInR(MIPSReg Reg)
{
MovToPC(Reg);
//WriteDownCount();
@ -331,7 +323,7 @@ void Jit::WriteExitDestInR(MIPSReg Reg)
B((const void *)dispatcher);
}
void Jit::WriteSyscallExit()
void MipsJit::WriteSyscallExit()
{
//WriteDownCount();
B((const void *)dispatcherCheckCoreState);

21
Core/MIPS/MIPS/MipsJit.h
View file

@ -28,21 +28,10 @@
namespace MIPSComp
{
struct MIPSJitOptions
{
MIPSJitOptions();
bool enableBlocklink;
bool immBranches;
bool continueBranches;
bool continueJumps;
int continueMaxInstructions;
};
class Jit : public MIPSGen::MIPSCodeBlock
class MipsJit : public MIPSGen::MIPSCodeBlock
{
public:
Jit(MIPSState *mips);
MipsJit(MIPSState *mips);
void DoState(PointerWrap &p);
static void DoDummyState(PointerWrap &p);
@ -165,7 +154,7 @@ private:
void WriteSyscallExit();
JitBlockCache blocks;
MIPSJitOptions jo;
JitOptions jo;
JitState js;
MIPSState *mips_;
@ -187,8 +176,8 @@ public:
const u8 *breakpointBailout;
};
typedef void (Jit::*MIPSCompileFunc)(MIPSOpcode opcode);
typedef int (Jit::*MIPSReplaceFunc)();
typedef void (MipsJit::*MIPSCompileFunc)(MIPSOpcode opcode);
typedef int (MipsJit::*MIPSReplaceFunc)();
} // namespace MIPSComp

24
Core/MIPS/MIPSTables.cpp
View file

@ -142,10 +142,10 @@ const MIPSInstruction tableImmediate[64] = // xxxxxx ..... ..... ...............
ENCODING(VFPU1),
ENCODING(Emu),
ENCODING(VFPU3),
ENCODING(Spe2),//special2
INVALID, //, "jalx", 0, Dis_JumpType, Int_JumpType},
ENCODING(Spe2), //special2
INVALID,
ENCODING(Spe3),//special3
INVALID,
ENCODING(Spe3), //special3
//32
INSTR("lb", JITFUNC(Comp_ITypeMem), Dis_ITypeMem, Int_ITypeMem, IN_MEM|IN_IMM16|IN_RS_ADDR|OUT_RT|MEMTYPE_BYTE),
INSTR("lh", JITFUNC(Comp_ITypeMem), Dis_ITypeMem, Int_ITypeMem, IN_MEM|IN_IMM16|IN_RS_ADDR|OUT_RT|MEMTYPE_HWORD),
@ -168,7 +168,7 @@ const MIPSInstruction tableImmediate[64] = // xxxxxx ..... ..... ...............
INSTR("ll", JITFUNC(Comp_Generic), Dis_Generic, Int_StoreSync, IN_MEM|IN_IMM16|IN_RS_ADDR|OUT_RT|OUT_OTHER|MEMTYPE_WORD),
INSTR("lwc1", JITFUNC(Comp_FPULS), Dis_FPULS, Int_FPULS, IN_MEM|IN_IMM16|IN_RS_ADDR|OUT_FT|MEMTYPE_FLOAT|IS_FPU),
INSTR("lv.s", JITFUNC(Comp_SV), Dis_SV, Int_SV, IN_MEM|IN_IMM16|IN_RS_ADDR|OUT_OTHER|IS_VFPU|VFPU_NO_PREFIX|MEMTYPE_FLOAT),
INVALID, // HIT THIS IN WIPEOUT
INVALID,
ENCODING(VFPU4Jump),
INSTR("lv", JITFUNC(Comp_SVQ), Dis_SVLRQ, Int_SVQ, IN_MEM|IN_IMM16|IN_RS_ADDR|OUT_OTHER|IS_VFPU|VFPU_NO_PREFIX|MEMTYPE_VQUAD),
INSTR("lv.q", JITFUNC(Comp_SVQ), Dis_SVQ, Int_SVQ, IN_MEM|IN_IMM16|IN_RS_ADDR|OUT_OTHER|IS_VFPU|VFPU_NO_PREFIX|MEMTYPE_VQUAD), //copU
@ -434,13 +434,13 @@ const MIPSInstruction tableCop0CO[64] = // 010000 1.... ..... ..... ..... xxxxxx
const MIPSInstruction tableCop1[32] = // 010001 xxxxx ..... ..... ...........
{
INSTR("mfc1", JITFUNC(Comp_mxc1), Dis_mxc1, Int_mxc1, IN_FS|OUT_RT),
INSTR("mfc1", JITFUNC(Comp_mxc1), Dis_mxc1, Int_mxc1, IN_FS|OUT_RT|IS_FPU),
INVALID,
INSTR("cfc1", JITFUNC(Comp_mxc1), Dis_mxc1, Int_mxc1, IN_OTHER|IN_FPUFLAG|OUT_RT),
INSTR("cfc1", JITFUNC(Comp_mxc1), Dis_mxc1, Int_mxc1, IN_OTHER|IN_FPUFLAG|OUT_RT|IS_FPU),
INVALID,
INSTR("mtc1", JITFUNC(Comp_mxc1), Dis_mxc1, Int_mxc1, IN_RT|OUT_FS),
INSTR("mtc1", JITFUNC(Comp_mxc1), Dis_mxc1, Int_mxc1, IN_RT|OUT_FS|IS_FPU),
INVALID,
INSTR("ctc1", JITFUNC(Comp_mxc1), Dis_mxc1, Int_mxc1, IN_RT|OUT_FPUFLAG|OUT_OTHER),
INSTR("ctc1", JITFUNC(Comp_mxc1), Dis_mxc1, Int_mxc1, IN_RT|OUT_FPUFLAG|OUT_OTHER|IS_FPU),
INVALID,
//8
ENCODING(Cop1BC), INVALID, INVALID, INVALID, INVALID, INVALID, INVALID, INVALID,
@ -453,10 +453,10 @@ const MIPSInstruction tableCop1[32] = // 010001 xxxxx ..... ..... ...........
const MIPSInstruction tableCop1BC[32] = // 010001 01000 xxxxx ................
{
INSTR("bc1f", JITFUNC(Comp_FPUBranch), Dis_FPUBranch, Int_FPUBranch, IS_CONDBRANCH|IN_IMM16|IN_FPUFLAG|DELAYSLOT|CONDTYPE_FPUFALSE),
INSTR("bc1t", JITFUNC(Comp_FPUBranch), Dis_FPUBranch, Int_FPUBranch, IS_CONDBRANCH|IN_IMM16|IN_FPUFLAG|DELAYSLOT|CONDTYPE_FPUTRUE),
INSTR("bc1fl", JITFUNC(Comp_FPUBranch), Dis_FPUBranch, Int_FPUBranch, IS_CONDBRANCH|IN_IMM16|IN_FPUFLAG|DELAYSLOT|LIKELY|CONDTYPE_FPUFALSE),
INSTR("bc1tl", JITFUNC(Comp_FPUBranch), Dis_FPUBranch, Int_FPUBranch, IS_CONDBRANCH|IN_IMM16|IN_FPUFLAG|DELAYSLOT|LIKELY|CONDTYPE_FPUTRUE),
INSTR("bc1f", JITFUNC(Comp_FPUBranch), Dis_FPUBranch, Int_FPUBranch, IS_CONDBRANCH|IN_IMM16|IN_FPUFLAG|DELAYSLOT|CONDTYPE_FPUFALSE|IS_FPU),
INSTR("bc1t", JITFUNC(Comp_FPUBranch), Dis_FPUBranch, Int_FPUBranch, IS_CONDBRANCH|IN_IMM16|IN_FPUFLAG|DELAYSLOT|CONDTYPE_FPUTRUE|IS_FPU),
INSTR("bc1fl", JITFUNC(Comp_FPUBranch), Dis_FPUBranch, Int_FPUBranch, IS_CONDBRANCH|IN_IMM16|IN_FPUFLAG|DELAYSLOT|LIKELY|CONDTYPE_FPUFALSE|IS_FPU),
INSTR("bc1tl", JITFUNC(Comp_FPUBranch), Dis_FPUBranch, Int_FPUBranch, IS_CONDBRANCH|IN_IMM16|IN_FPUFLAG|DELAYSLOT|LIKELY|CONDTYPE_FPUTRUE|IS_FPU),
INVALID, INVALID, INVALID, INVALID,
//8
INVALID_X_8,

2
Core/MIPS/MIPSTables.h
View file

@ -28,7 +28,7 @@ struct MIPSInfo {
explicit MIPSInfo(u64 v) : value(v) {
}
u64 operator & (const u32 &arg) const {
u64 operator & (const u64 &arg) const {
return value & arg;
}

12
Core/MIPS/x86/Jit.cpp
View file

@ -114,18 +114,6 @@ static void JitLogMiss(MIPSOpcode op)
func(op);
}
JitOptions::JitOptions()
{
enableBlocklink = true;
immBranches = false;
continueBranches = false;
continueJumps = false;
continueMaxInstructions = 300;
enableVFPUSIMD = true;
// Set by Asm if needed.
reserveR15ForAsm = false;
}
#ifdef _MSC_VER
// JitBlockCache doesn't use this, just stores it.
#pragma warning(disable:4355)

13
Core/MIPS/x86/Jit.h
View file

@ -41,19 +41,6 @@ namespace MIPSComp
// This is called when Jit hits a breakpoint. Returns 1 when hit.
u32 JitBreakpoint();
struct JitOptions
{
JitOptions();
bool enableBlocklink;
bool immBranches;
bool continueBranches;
bool continueJumps;
int continueMaxInstructions;
bool enableVFPUSIMD;
bool reserveR15ForAsm;
};
// TODO: Hmm, humongous.
struct RegCacheState {
GPRRegCacheState gpr;

1
android/jni/Android.mk
View file

@ -314,6 +314,7 @@ EXEC_AND_LIB_FILES := \
$(SRC)/Core/FileSystems/tlzrc.cpp \
$(SRC)/Core/MIPS/JitCommon/JitCommon.cpp \
$(SRC)/Core/MIPS/JitCommon/JitBlockCache.cpp \
$(SRC)/Core/MIPS/JitCommon/JitState.cpp \
$(SRC)/Core/Util/AudioFormat.cpp \
$(SRC)/Core/Util/GameManager.cpp \
$(SRC)/Core/Util/BlockAllocator.cpp \

2
unittest/TestArmEmitter.cpp
View file

@ -199,7 +199,7 @@ bool TestArmEmitter() {
MIPSState mips;
MIPSComp::JitState js;
MIPSComp::ArmJitOptions jo;
MIPSComp::JitOptions jo;
ArmRegCacheFPU fpr(&mips, &js, &jo);
fpr.SetEmitter(&emitter);
int C000 = GetColumnName(0, M_4x4, 0, 0);