diff --git a/Core/MIPS/MIPSIntVFPU.cpp b/Core/MIPS/MIPSIntVFPU.cpp
index f4273a10be..a64be2caf7 100644
--- a/Core/MIPS/MIPSIntVFPU.cpp
+++ b/Core/MIPS/MIPSIntVFPU.cpp
@@ -494,7 +494,7 @@ namespace MIPSInt
 			case 19: d[i] = cosf((float)M_PI_2 * s[i]); break; //vcos
 			case 20: d[i] = powf(2.0f, s[i]); break; //vexp2
 			case 21: d[i] = logf(s[i])/log(2.0f); break; //vlog2
-			case 22: d[i] = sqrtf(s[i]); break; //vsqrt
+			case 22: d[i] = fabsf(sqrtf(s[i])); break; //vsqrt
 			case 23: d[i] = asinf(s[i] * (float)M_2_PI); break; //vasin
 			case 24: d[i] = -1.0f / s[i]; break; // vnrcp
 			case 26: d[i] = -sinf((float)M_PI_2 * s[i]); break; // vnsin
diff --git a/Core/MIPS/x86/CompVFPU.cpp b/Core/MIPS/x86/CompVFPU.cpp
index 7a2ab488f7..13ca0a02ee 100644
--- a/Core/MIPS/x86/CompVFPU.cpp
+++ b/Core/MIPS/x86/CompVFPU.cpp
@@ -553,6 +553,7 @@ void Jit::Comp_VV2Op(u32 op) {
 			break;
 		case 22: // d[i] = sqrtf(s[i]); break; //vsqrt
 			SQRTSS(tempxregs[i], fpr.V(sregs[i]));
+			ANDPS(tempxregs[i], M((void *)&noSignMask));
 			break;
 		case 23: // d[i] = asinf(s[i] * (float)M_2_PI); break; //vasin
 			DISABLE;