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https://github.com/hrydgard/ppsspp.git
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Better logic immediate support in ARM emitter. From V8.
This commit is contained in:
Henrik Rydgard
parent
b309c83973
commit
3aebc06329
4 changed files with 298 additions and 4 deletions
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@ -6,6 +6,8 @@
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#include <algorithm>
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#include <cmath>
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#include "base/basictypes.h"
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#include "Arm64Emitter.h"
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#include "MathUtil.h"
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#include "CommonTypes.h"
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@ -13,6 +15,232 @@
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namespace Arm64Gen
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{
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const int kWRegSizeInBits = 32;
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const int kXRegSizeInBits = 64;
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// The below few functions are taken from V8.
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int CountLeadingZeros(uint64_t value, int width) {
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// TODO(jbramley): Optimize this for ARM64 hosts.
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int count = 0;
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uint64_t bit_test = 1UL << (width - 1);
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while ((count < width) && ((bit_test & value) == 0)) {
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count++;
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bit_test >>= 1;
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}
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return count;
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}
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uint64_t LargestPowerOf2Divisor(uint64_t value) {
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return value & -value;
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}
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bool IsPowerOfTwo(uint64_t x) {
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return (x != 0) && ((x & (x - 1)) == 0);
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}
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#define V8_UINT64_C(x) ((uint64_t)(x))
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static bool IsImmLogical(uint64_t value,
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unsigned int width,
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unsigned int *n,
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unsigned int *imm_s,
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unsigned int *imm_r) {
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//DCHECK((n != NULL) && (imm_s != NULL) && (imm_r != NULL));
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// DCHECK((width == kWRegSizeInBits) || (width == kXRegSizeInBits));
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bool negate = false;
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// Logical immediates are encoded using parameters n, imm_s and imm_r using
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// the following table:
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//
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// N imms immr size S R
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// 1 ssssss rrrrrr 64 UInt(ssssss) UInt(rrrrrr)
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// 0 0sssss xrrrrr 32 UInt(sssss) UInt(rrrrr)
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// 0 10ssss xxrrrr 16 UInt(ssss) UInt(rrrr)
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// 0 110sss xxxrrr 8 UInt(sss) UInt(rrr)
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// 0 1110ss xxxxrr 4 UInt(ss) UInt(rr)
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// 0 11110s xxxxxr 2 UInt(s) UInt(r)
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// (s bits must not be all set)
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//
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// A pattern is constructed of size bits, where the least significant S+1 bits
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// are set. The pattern is rotated right by R, and repeated across a 32 or
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// 64-bit value, depending on destination register width.
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//
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// Put another way: the basic format of a logical immediate is a single
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// contiguous stretch of 1 bits, repeated across the whole word at intervals
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// given by a power of 2. To identify them quickly, we first locate the
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// lowest stretch of 1 bits, then the next 1 bit above that; that combination
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// is different for every logical immediate, so it gives us all the
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// information we need to identify the only logical immediate that our input
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// could be, and then we simply check if that's the value we actually have.
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//
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// (The rotation parameter does give the possibility of the stretch of 1 bits
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// going 'round the end' of the word. To deal with that, we observe that in
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// any situation where that happens the bitwise NOT of the value is also a
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// valid logical immediate. So we simply invert the input whenever its low bit
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// is set, and then we know that the rotated case can't arise.)
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if (value & 1) {
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// If the low bit is 1, negate the value, and set a flag to remember that we
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// did (so that we can adjust the return values appropriately).
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negate = true;
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value = ~value;
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}
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if (width == kWRegSizeInBits) {
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// To handle 32-bit logical immediates, the very easiest thing is to repeat
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// the input value twice to make a 64-bit word. The correct encoding of that
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// as a logical immediate will also be the correct encoding of the 32-bit
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// value.
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// The most-significant 32 bits may not be zero (ie. negate is true) so
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// shift the value left before duplicating it.
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value <<= kWRegSizeInBits;
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value |= value >> kWRegSizeInBits;
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}
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// The basic analysis idea: imagine our input word looks like this.
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//
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// 0011111000111110001111100011111000111110001111100011111000111110
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// c b a
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// |<--d-->|
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//
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// We find the lowest set bit (as an actual power-of-2 value, not its index)
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// and call it a. Then we add a to our original number, which wipes out the
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// bottommost stretch of set bits and replaces it with a 1 carried into the
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// next zero bit. Then we look for the new lowest set bit, which is in
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// position b, and subtract it, so now our number is just like the original
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// but with the lowest stretch of set bits completely gone. Now we find the
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// lowest set bit again, which is position c in the diagram above. Then we'll
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// measure the distance d between bit positions a and c (using CLZ), and that
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// tells us that the only valid logical immediate that could possibly be equal
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// to this number is the one in which a stretch of bits running from a to just
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// below b is replicated every d bits.
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uint64_t a = LargestPowerOf2Divisor(value);
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uint64_t value_plus_a = value + a;
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uint64_t b = LargestPowerOf2Divisor(value_plus_a);
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uint64_t value_plus_a_minus_b = value_plus_a - b;
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uint64_t c = LargestPowerOf2Divisor(value_plus_a_minus_b);
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int d, clz_a, out_n;
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uint64_t mask;
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if (c != 0) {
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// The general case, in which there is more than one stretch of set bits.
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// Compute the repeat distance d, and set up a bitmask covering the basic
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// unit of repetition (i.e. a word with the bottom d bits set). Also, in all
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// of these cases the N bit of the output will be zero.
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clz_a = CountLeadingZeros(a, kXRegSizeInBits);
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int clz_c = CountLeadingZeros(c, kXRegSizeInBits);
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d = clz_a - clz_c;
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mask = ((V8_UINT64_C(1) << d) - 1);
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out_n = 0;
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} else {
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// Handle degenerate cases.
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//
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// If any of those 'find lowest set bit' operations didn't find a set bit at
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// all, then the word will have been zero thereafter, so in particular the
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// last lowest_set_bit operation will have returned zero. So we can test for
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// all the special case conditions in one go by seeing if c is zero.
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if (a == 0) {
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// The input was zero (or all 1 bits, which will come to here too after we
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// inverted it at the start of the function), for which we just return
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// false.
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return false;
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} else {
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// Otherwise, if c was zero but a was not, then there's just one stretch
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// of set bits in our word, meaning that we have the trivial case of
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// d == 64 and only one 'repetition'. Set up all the same variables as in
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// the general case above, and set the N bit in the output.
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clz_a = CountLeadingZeros(a, kXRegSizeInBits);
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d = 64;
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mask = ~V8_UINT64_C(0);
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out_n = 1;
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}
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}
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// If the repeat period d is not a power of two, it can't be encoded.
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if (!IsPowerOfTwo(d)) {
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return false;
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}
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if (((b - a) & ~mask) != 0) {
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// If the bit stretch (b - a) does not fit within the mask derived from the
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// repeat period, then fail.
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return false;
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}
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// The only possible option is b - a repeated every d bits. Now we're going to
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// actually construct the valid logical immediate derived from that
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// specification, and see if it equals our original input.
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//
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// To repeat a value every d bits, we multiply it by a number of the form
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// (1 + 2^d + 2^(2d) + ...), i.e. 0x0001000100010001 or similar. These can
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// be derived using a table lookup on CLZ(d).
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static const uint64_t multipliers[] = {
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0x0000000000000001UL,
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0x0000000100000001UL,
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0x0001000100010001UL,
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0x0101010101010101UL,
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0x1111111111111111UL,
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0x5555555555555555UL,
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};
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int multiplier_idx = CountLeadingZeros(d, kXRegSizeInBits) - 57;
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// Ensure that the index to the multipliers array is within bounds.
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_dbg_assert_(JIT, (multiplier_idx >= 0) &&
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(static_cast<size_t>(multiplier_idx) < ARRAY_SIZE(multipliers)));
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uint64_t multiplier = multipliers[multiplier_idx];
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uint64_t candidate = (b - a) * multiplier;
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if (value != candidate) {
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// The candidate pattern doesn't match our input value, so fail.
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return false;
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}
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// We have a match! This is a valid logical immediate, so now we have to
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// construct the bits and pieces of the instruction encoding that generates
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// it.
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// Count the set bits in our basic stretch. The special case of clz(0) == -1
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// makes the answer come out right for stretches that reach the very top of
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// the word (e.g. numbers like 0xffffc00000000000).
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int clz_b = (b == 0) ? -1 : CountLeadingZeros(b, kXRegSizeInBits);
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int s = clz_a - clz_b;
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// Decide how many bits to rotate right by, to put the low bit of that basic
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// stretch in position a.
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int r;
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if (negate) {
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// If we inverted the input right at the start of this function, here's
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// where we compensate: the number of set bits becomes the number of clear
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// bits, and the rotation count is based on position b rather than position
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// a (since b is the location of the 'lowest' 1 bit after inversion).
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s = d - s;
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r = (clz_b + 1) & (d - 1);
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} else {
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r = (clz_a + 1) & (d - 1);
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}
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// Now we're done, except for having to encode the S output in such a way that
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// it gives both the number of set bits and the length of the repeated
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// segment. The s field is encoded like this:
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//
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// imms size S
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// ssssss 64 UInt(ssssss)
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// 0sssss 32 UInt(sssss)
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// 10ssss 16 UInt(ssss)
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// 110sss 8 UInt(sss)
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// 1110ss 4 UInt(ss)
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// 11110s 2 UInt(s)
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//
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// So we 'or' (-d << 1) with our computed s to form imms.
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*n = out_n;
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*imm_s = ((-d << 1) | (s - 1)) & 0x3f;
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*imm_r = r;
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return true;
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}
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void ARM64XEmitter::SetCodePtr(u8* ptr)
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{
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m_code = ptr;
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@ -704,6 +932,12 @@ void ARM64XEmitter::BL(const void* ptr)
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EncodeUnconditionalBranchInst(1, ptr);
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}
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void ARM64XEmitter::QuickCallFunction(ARM64Reg scratchreg, const void *func) {
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// TODO: Add special code to use the scratch reg if the call distance is too great.
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BL(func);
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}
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// Unconditional Branch (register)
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void ARM64XEmitter::BR(ARM64Reg Rn)
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{
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@ -1114,7 +1348,7 @@ void ARM64XEmitter::ORR(ARM64Reg Rd, ARM64Reg Rn, u32 immr, u32 imms)
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}
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void ARM64XEmitter::TST(ARM64Reg Rn, u32 immr, u32 imms)
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{
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EncodeLogicalImmInst(3, SP, Rn, immr, imms);
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EncodeLogicalImmInst(3, Is64Bit(Rn) ? SP : WSP, Rn, immr, imms);
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}
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// Add/subtract (immediate)
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@ -2784,5 +3018,35 @@ void ARM64FloatEmitter::ABI_PopRegisters(BitSet32 registers, BitSet32 ignore_mas
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}
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}
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void ARM64XEmitter::ANDI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch) {
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unsigned int n, imm_s, imm_r;
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if (IsImmLogical(imm, Is64Bit(Rn) ? 64 : 32, &n, &imm_s, &imm_r)) {
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AND(Rd, Rn, imm_r, imm_s);
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} else {
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MOVI2R(scratch, imm);
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AND(Rd, Rn, scratch);
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}
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}
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void ARM64XEmitter::ORI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch) {
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unsigned int n, imm_s, imm_r;
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if (IsImmLogical(imm, Is64Bit(Rn) ? 64 : 32, &n, &imm_s, &imm_r)) {
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ORR(Rd, Rn, imm_r, imm_s);
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} else {
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MOVI2R(scratch, imm);
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ORR(Rd, Rn, scratch);
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}
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}
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void ARM64XEmitter::ANDSI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch) {
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unsigned int n, imm_s, imm_r;
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if (IsImmLogical(imm, Is64Bit(Rn) ? 64 : 32, &n, &imm_s, &imm_r)) {
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ANDS(Rd, Rn, imm_r, imm_s);
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} else {
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MOVI2R(scratch, imm);
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ANDS(Rd, Rn, scratch);
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}
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}
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}
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@ -79,7 +79,7 @@ enum ARM64Reg
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INVALID_REG = 0xFFFFFFFF
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};
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inline bool Is64Bit(ARM64Reg reg) { return reg & 0x20; }
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inline bool Is64Bit(ARM64Reg reg) { return (reg & 0x20) != 0; }
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inline bool IsSingle(ARM64Reg reg) { return (reg & 0xC0) == 0x40; }
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inline bool IsDouble(ARM64Reg reg) { return (reg & 0xC0) == 0x80; }
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inline bool IsQuad(ARM64Reg reg) { return (reg & 0xC0) == 0xC0; }
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@ -500,6 +500,17 @@ public:
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void EON(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift);
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void ANDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift);
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void BICS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift);
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// Wrap the above for saner syntax
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void AND(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { AND(Rd, Rn, Rm, ArithOption(Rd, 0)); }
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void BIC(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { BIC(Rd, Rn, Rm, ArithOption(Rd, 0)); }
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void ORR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { ORR(Rd, Rn, Rm, ArithOption(Rd, 0)); }
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void ORN(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { ORN(Rd, Rn, Rm, ArithOption(Rd, 0)); }
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void EOR(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { EOR(Rd, Rn, Rm, ArithOption(Rd, 0)); }
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void EON(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { EON(Rd, Rn, Rm, ArithOption(Rd, 0)); }
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void ANDS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { ANDS(Rd, Rn, Rm, ArithOption(Rd, 0)); }
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void BICS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm) { BICS(Rd, Rn, Rm, ArithOption(Rd, 0)); }
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void MOV(ARM64Reg Rd, ARM64Reg Rm);
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void MVN(ARM64Reg Rd, ARM64Reg Rm);
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@ -611,6 +622,12 @@ public:
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// Wrapper around MOVZ+MOVK
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void MOVI2R(ARM64Reg Rd, u64 imm, bool optimize = true);
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// Wrapper around AND x, y, imm etc
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void ANDI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch);
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void ANDSI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch);
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void TSTI2R(ARM64Reg Rn, u64 imm, ARM64Reg scratch) { ANDSI2R(Is64Bit(Rn) ? SP : WSP, Rn, imm, scratch); }
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void ORI2R(ARM64Reg Rd, ARM64Reg Rn, u64 imm, ARM64Reg scratch);
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// ABI related
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void ABI_PushRegisters(BitSet32 registers);
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void ABI_PopRegisters(BitSet32 registers, BitSet32 ignore_mask = BitSet32(0));
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@ -637,6 +654,12 @@ public:
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MOVI2R(X0, (u64)const_cast<void*>((const void*)f));
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return X30;
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}
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// Plain function call
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void QuickCallFunction(ARM64Reg scratchreg, const void *func);
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template <typename T> void QuickCallFunction(ARM64Reg scratchreg, T func) {
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QuickCallFunction(scratchreg, (const void *)func);
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}
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};
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class ARM64FloatEmitter
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@ -748,6 +771,7 @@ public:
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// vector x indexed element
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void FMUL(u8 size, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, u8 index);
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// ABI related
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void ABI_PushRegisters(BitSet32 registers);
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void ABI_PopRegisters(BitSet32 registers, BitSet32 ignore_mask = BitSet32(0));
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@ -160,7 +160,7 @@ void CPUInfo::Detect()
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{
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// Set some defaults here
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HTT = false;
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#ifdef _M_ARM_64
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#ifdef ARM64
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OS64bit = true;
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CPU64bit = true;
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Mode64bit = true;
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@ -229,7 +229,13 @@ u8* MemArena::Find4GBBase()
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return reinterpret_cast<u8*>(0x2300000000ULL);
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#endif
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#else // 32 bit
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#elif defined(ARM64)
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// Very precarious - mmap cannot return an error when trying to map already used pages.
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// This makes the Windows approach above unusable on Linux, so we will simply pray...
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return reinterpret_cast<u8*>(0x2300000000ULL);
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#else
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#ifdef _WIN32
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u8* base = (u8*)VirtualAlloc(0, 0x10000000, MEM_RESERVE, PAGE_READWRITE);
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