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Protect against some writes to $0.

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Unknown W. Brackets 2013-02-16 17:56:27 -08:00
parent 7d4dd1b393
commit 3a365fef64
1 changed files with 50 additions and 3 deletions
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53
Core/MIPS/MIPSInt.cpp
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@ -304,7 +304,6 @@ namespace MIPSInt
_dbg_assert_msg_(CPU,0,"Jump in delay slot :(");
}
int rs = (op>>21)&0x1f;
u32 addr = R(rs);
switch (op & 0x3f)
@ -362,13 +361,17 @@ namespace MIPSInt
switch (op >> 26)
{
case 48: // ll
R(rt) = Memory::Read_U32(addr);
if (rt != 0) {
R(rt) = Memory::Read_U32(addr);
}
currentMIPS->llBit = 1;
break;
case 56: // sc
if (currentMIPS->llBit) {
Memory::Write_U32(R(rt), addr);
R(rt) = 1;
if (rt != 0) {
R(rt) = 1;
}
} else {
R(rt) = 0;
}
@ -388,6 +391,13 @@ namespace MIPSInt
int rd = _RD;
static bool has_warned = false;
// Don't change $zr.
if (rd == 0)
{
PC += 4;
return;
}
switch (op & 63)
{
case 10: if (R(rt) == 0) R(rd) = R(rs); break; //movz
@ -533,6 +543,14 @@ namespace MIPSInt
{
int rs = _RS;
int rd = _RD;
// Don't change $zr.
if (rd == 0)
{
PC += 4;
return;
}
switch (op & 63)
{
case 22: //clz
@ -675,6 +693,13 @@ namespace MIPSInt
int rs = _RS;
int rd = _RD;
int sa = _FD;
// Don't change $zr.
if (rd == 0)
{
PC += 4;
return;
}
switch (op & 0x3f)
{
@ -720,6 +745,14 @@ namespace MIPSInt
{
int rt = _RT;
int rd = _RD;
// Don't change $zr.
if (rd == 0)
{
PC += 4;
return;
}
switch((op>>6)&31)
{
case 16: // seb
@ -756,6 +789,13 @@ namespace MIPSInt
int rt = _RT;
int rd = _RD;
// Don't change $zr.
if (rd == 0)
{
PC += 4;
return;
}
switch (op & 0x3ff)
{
case 0xA0: //wsbh
@ -777,6 +817,13 @@ namespace MIPSInt
int rt = _RT;
int pos = _POS;
// Don't change $zr.
if (rt == 0)
{
PC += 4;
return;
}
switch (op & 0x3f)
{
case 0x0: //ext