diff --git a/Common/Arm64Emitter.cpp b/Common/Arm64Emitter.cpp
index ebf0a9101a..52f341efd0 100644
--- a/Common/Arm64Emitter.cpp
+++ b/Common/Arm64Emitter.cpp
@@ -1354,6 +1354,10 @@ void ARM64XEmitter::UMADDL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra)
 {
 	EncodeData3SrcInst(5, Rd, Rn, Rm, Ra);
 }
+void ARM64XEmitter::UMULL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
+{
+	UMADDL(Rd, Rn, Rm, SP);
+}
 void ARM64XEmitter::UMSUBL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra)
 {
 	EncodeData3SrcInst(6, Rd, Rn, Rm, Ra);
diff --git a/Common/Arm64Emitter.h b/Common/Arm64Emitter.h
index ef5720c2d6..9cae8bf9f8 100644
--- a/Common/Arm64Emitter.h
+++ b/Common/Arm64Emitter.h
@@ -532,6 +532,7 @@ public:
 	void SMSUBL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
 	void SMULH(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
 	void UMADDL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
+	void UMULL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
 	void UMSUBL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
 	void UMULH(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
 	void MUL(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
diff --git a/Core/Util/DisArm64.cpp b/Core/Util/DisArm64.cpp
index fcf5e87c5a..8f1b176a90 100644
--- a/Core/Util/DisArm64.cpp
+++ b/Core/Util/DisArm64.cpp
@@ -437,7 +437,11 @@ static void DataProcessingRegister(uint32_t w, uint64_t addr, Instruction *instr
 			// The rest are 64-bit accumulator, 32-bit operands
 			char sign = (op31 >> 2) ? 'u' : 's';
 			int opn = (op31 & 0x3) << 1 | o0;
-			snprintf(instr->text, sizeof(instr->text), "%c%s x%d, x%d, w%d, w%d", sign, opnames[opn], Rd, Rn, Rm, Ra);
+			if (opn < 4 && Ra == 31) {
+				snprintf(instr->text, sizeof(instr->text), "%cmull x%d, w%d, w%d", sign, Rd, Rn, Rm);
+			} else {
+				snprintf(instr->text, sizeof(instr->text), "%c%s x%d, w%d, w%d, x%d", sign, opnames[opn], Rd, Rn, Rm, Ra);
+			}
 		}
 	} else {
 		// Logical (extended register)