From 2e8ef3027f76251b88622dfb236d62179d1630d0 Mon Sep 17 00:00:00 2001
From: "Unknown W. Brackets" <checkins@unknownbrackets.org>
Date: Thu, 17 Oct 2013 07:39:33 -0700
Subject: [PATCH] Write the retaddr to rd, not always ra, in jalr.

Thanks go entirely to @Kingcom for pointing this out.

Don't know of any games not using RA as the rd.
---
 Core/MIPS/ARM/ArmCompBranch.cpp | 3 ++-
 Core/MIPS/MIPSDis.cpp           | 9 ++++++---
 Core/MIPS/MIPSInt.cpp           | 3 ++-
 Core/MIPS/MIPSTables.cpp        | 2 +-
 Core/MIPS/PPC/PpcCompBranch.cpp | 3 ++-
 Core/MIPS/x86/CompBranch.cpp    | 3 ++-
 6 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/Core/MIPS/ARM/ArmCompBranch.cpp b/Core/MIPS/ARM/ArmCompBranch.cpp
index 9bca9d8be3..44f4e83e4c 100644
--- a/Core/MIPS/ARM/ArmCompBranch.cpp
+++ b/Core/MIPS/ARM/ArmCompBranch.cpp
@@ -372,6 +372,7 @@ void Jit::Comp_JumpReg(MIPSOpcode op)
 		return;
 	}
 	MIPSGPReg rs = _RS;
+	MIPSGPReg rd = _RD:
 
 	MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
 	bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
@@ -402,7 +403,7 @@ void Jit::Comp_JumpReg(MIPSOpcode op)
 		break;
 	case 9: //jalr
 		MOVI2R(R0, js.compilerPC + 8);
-		STR(R0, CTXREG, MIPS_REG_RA * 4);
+		STR(R0, CTXREG, (int)rd * 4);
 		break;
 	default:
 		_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
diff --git a/Core/MIPS/MIPSDis.cpp b/Core/MIPS/MIPSDis.cpp
index 1b5f8e3a5b..5eac7c6173 100644
--- a/Core/MIPS/MIPSDis.cpp
+++ b/Core/MIPS/MIPSDis.cpp
@@ -328,10 +328,13 @@ namespace MIPSDis
 	}
 	void Dis_JumpRegType(MIPSOpcode op, char *out)
 	{
-		int rs = (op>>21)&0x1f;
+		int rs = _RS;
+		int rd = _RD;
 		const char *name = MIPSGetName(op);
-		sprintf(out, "%s\t->%s",name,RN(rs));
-
+		if ((op & 0x3f) == 9 && rd != MIPS_REG_RA)
+			sprintf(out, "%s\t%s,->%s", name, RN(rd), RN(rs));
+		else
+			sprintf(out, "%s\t->%s", name, RN(rs));
 	}
 
 	void Dis_Allegrex(MIPSOpcode op, char *out)
diff --git a/Core/MIPS/MIPSInt.cpp b/Core/MIPS/MIPSInt.cpp
index 73217d132c..43ae88496f 100644
--- a/Core/MIPS/MIPSInt.cpp
+++ b/Core/MIPS/MIPSInt.cpp
@@ -292,6 +292,7 @@ namespace MIPSInt
 		}
 
 		int rs = _RS;
+		int rd = _RD;
 		u32 addr = R(rs);
 		switch (op & 0x3f) 
 		{
@@ -300,7 +301,7 @@ namespace MIPSInt
 			DelayBranchTo(addr);
 			break;
 		case 9: //jalr
-			R(31) = PC + 8;
+			R(rd) = PC + 8;
 			DelayBranchTo(addr);
 			break;
 		}
diff --git a/Core/MIPS/MIPSTables.cpp b/Core/MIPS/MIPSTables.cpp
index e26f2b05d7..bba0152204 100644
--- a/Core/MIPS/MIPSTables.cpp
+++ b/Core/MIPS/MIPSTables.cpp
@@ -184,7 +184,7 @@ const MIPSInstruction tableSpecial[64] = // 000000 ..... ..... ..... ..... xxxxx
 
 	//8
 	INSTR("jr",    &Jit::Comp_JumpReg, Dis_JumpRegType, Int_JumpRegType, IS_JUMP|IN_RS|DELAYSLOT),
-	INSTR("jalr",  &Jit::Comp_JumpReg, Dis_JumpRegType, Int_JumpRegType, IS_JUMP|IN_RS|OUT_RA|DELAYSLOT),
+	INSTR("jalr",  &Jit::Comp_JumpReg, Dis_JumpRegType, Int_JumpRegType, IS_JUMP|IN_RS|OUT_RD|DELAYSLOT),
 	INSTR("movz",  &Jit::Comp_RType3, Dis_RType3, Int_RType3, OUT_RD|IN_RS|IN_RT|IS_CONDMOVE|CONDTYPE_EQ),
 	INSTR("movn",  &Jit::Comp_RType3, Dis_RType3, Int_RType3, OUT_RD|IN_RS|IN_RT|IS_CONDMOVE|CONDTYPE_NE),
 	INSTR("syscall", &Jit::Comp_Syscall, Dis_Syscall, Int_Syscall, IN_MEM|IN_OTHER|OUT_MEM|OUT_OTHER),
diff --git a/Core/MIPS/PPC/PpcCompBranch.cpp b/Core/MIPS/PPC/PpcCompBranch.cpp
index 4533d4cbd0..ed8d8da11f 100644
--- a/Core/MIPS/PPC/PpcCompBranch.cpp
+++ b/Core/MIPS/PPC/PpcCompBranch.cpp
@@ -360,6 +360,7 @@ void Jit::Comp_JumpReg(MIPSOpcode op) {
 		return;
 	}
 	MIPSGPReg rs = _RS;
+	MIPSGPReg rd = _RD;
 
 	MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
 	bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
@@ -394,7 +395,7 @@ void Jit::Comp_JumpReg(MIPSOpcode op) {
 	case 9: //jalr
 		// mips->reg = js.compilerPC + 8;
 		MOVI2R(SREG, js.compilerPC + 8);
-		STW(SREG, CTXREG, MIPS_REG_RA * 4);
+		STW(SREG, CTXREG, (int)rd * 4);
 		break;
 	default:
 		_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
diff --git a/Core/MIPS/x86/CompBranch.cpp b/Core/MIPS/x86/CompBranch.cpp
index 1434a5954e..3d63d07f65 100644
--- a/Core/MIPS/x86/CompBranch.cpp
+++ b/Core/MIPS/x86/CompBranch.cpp
@@ -575,6 +575,7 @@ void Jit::Comp_JumpReg(MIPSOpcode op)
 		return;
 	}
 	MIPSGPReg rs = _RS;
+	MIPSGPReg rd = _RD;
 
 	MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4);
 	bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
@@ -612,7 +613,7 @@ void Jit::Comp_JumpReg(MIPSOpcode op)
 	case 8: //jr
 		break;
 	case 9: //jalr
-		MOV(32, M(&mips_->r[MIPS_REG_RA]), Imm32(js.compilerPC + 8));
+		MOV(32, M(&mips_->r[rd]), Imm32(js.compilerPC + 8));
 		break;
 	default:
 		_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");