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https://github.com/hrydgard/ppsspp.git
synced 2025-04-02 11:01:50 -04:00
Clear out the jit pointer on shutdown. Some cleanup.
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parent
27a863a02e
commit
2b05a60d9d
3 changed files with 34 additions and 63 deletions
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@ -23,6 +23,7 @@
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#include "Common.h"
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#include "Common/ChunkFile.h"
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#include "Core/MIPS/MIPS.h"
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#include "Core/MIPS/MIPSInt.h"
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#include "Core/MIPS/MIPSTables.h"
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#include "Core/MIPS/MIPSDebugInterface.h"
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#include "Core/MIPS/MIPSVFPUUtils.h"
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@ -91,8 +92,7 @@ const float cst_constants[32] = {
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};
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MIPSState::MIPSState()
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{
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MIPSState::MIPSState() {
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MIPSComp::jit = 0;
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// Initialize vorder
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@ -103,7 +103,7 @@ MIPSState::MIPSState()
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// 0x01 0x21 0x41 0x61
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// 0x02 0x22 0x42 0x62
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// 0x03 0x23 0x43 0x63
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// 0x04 0x24 0x44 0x64
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// 0x06 0x26 0x45 0x65
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// ....
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@ -111,7 +111,7 @@ MIPSState::MIPSState()
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// the VPU registers are effectively organized like this:
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// 0x00 0x01 0x02 0x03
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// 0x04 0x05 0x06 0x07
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// 0x08 0x09 0x0a 0x0b
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// 0x08 0x09 0x0a 0x0b
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// ....
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// This is because the original indices look like this:
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@ -119,14 +119,14 @@ MIPSState::MIPSState()
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// We will now map 0YYMMMXX to 0MMMXXYY.
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// Advantages:
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// Advantages:
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// * Columns can be flushed and reloaded faster "at once"
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// * 4x4 Matrices are contiguous in RAM, making them, too, fast-loadable in NEON
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// Disadvantages:
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// * Extra indirection, can be confusing and slower (interpreter only)
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// * Flushing and reloading row registers is now slower
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int i = 0;
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for (int m = 0; m < 8; m++) {
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for (int y = 0; y < 4; y++) {
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@ -153,6 +153,7 @@ MIPSState::MIPSState()
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0x6, 0x26, 0x46, 0x66,
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0x7, 0x27, 0x47, 0x67,
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};
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for (int i = 0; i < (int)ARRAY_SIZE(firstThirtyTwo); i++) {
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if (voffset[firstThirtyTwo[i]] != i) {
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ERROR_LOG(CPU, "Wrong voffset order! %i: %i should have been %i", firstThirtyTwo[i], voffset[firstThirtyTwo[i]], i);
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@ -160,23 +161,23 @@ MIPSState::MIPSState()
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}
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}
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MIPSState::~MIPSState()
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{
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if (MIPSComp::jit)
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{
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MIPSState::~MIPSState() {
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Shutdown();
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}
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void MIPSState::Shutdown() {
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if (MIPSComp::jit) {
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delete MIPSComp::jit;
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MIPSComp::jit = 0;
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}
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}
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void MIPSState::Reset()
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{
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if (MIPSComp::jit)
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{
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delete MIPSComp::jit;
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MIPSComp::jit = 0;
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}
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void MIPSState::Reset() {
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Shutdown();
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Init();
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}
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void MIPSState::Init() {
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if (PSP_CoreParameter().cpuCore == CPU_JIT)
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MIPSComp::jit = new MIPSComp::Jit(this);
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@ -257,18 +258,15 @@ void MIPSState::DoState(PointerWrap &p) {
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p.Do(debugCount);
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}
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void MIPSState::SingleStep()
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{
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void MIPSState::SingleStep() {
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int cycles = MIPS_SingleStep();
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currentMIPS->downcount -= cycles;
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CoreTiming::Advance();
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}
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// returns 1 if reached ticks limit
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int MIPSState::RunLoopUntil(u64 globalTicks)
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{
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switch (PSP_CoreParameter().cpuCore)
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{
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int MIPSState::RunLoopUntil(u64 globalTicks) {
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switch (PSP_CoreParameter().cpuCore) {
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case CPU_JIT:
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MIPSComp::jit->RunLoopUntil(globalTicks);
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break;
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@ -279,62 +277,37 @@ int MIPSState::RunLoopUntil(u64 globalTicks)
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return 1;
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}
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void MIPSState::WriteFCR(int reg, int value)
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{
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if (reg == 31)
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{
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void MIPSState::WriteFCR(int reg, int value) {
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if (reg == 31) {
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fcr31 = value & 0x0181FFFF;
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fpcond = (value >> 23) & 1;
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}
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else
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{
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} else {
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WARN_LOG_REPORT(CPU, "WriteFCR: Unexpected reg %d (value %08x)", reg, value);
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// MessageBox(0, "Invalid FCR","...",0);
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}
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DEBUG_LOG(CPU, "FCR%i written to, value %08x", reg, value);
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}
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u32 MIPSState::ReadFCR(int reg)
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{
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u32 MIPSState::ReadFCR(int reg) {
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DEBUG_LOG(CPU,"FCR%i read",reg);
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if (reg == 31)
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{
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if (reg == 31) {
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fcr31 = (fcr31 & ~(1<<23)) | ((fpcond & 1)<<23);
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return fcr31;
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}
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else if (reg == 0)
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{
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} else if (reg == 0) {
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return FCR0_VALUE;
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}
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else
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{
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} else {
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WARN_LOG_REPORT(CPU, "ReadFCR: Unexpected reg %d", reg);
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// MessageBox(0, "Invalid FCR","...",0);
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}
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return 0;
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}
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void MIPSState::InvalidateICache(u32 address, int length)
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{
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void MIPSState::InvalidateICache(u32 address, int length) {
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// Only really applies to jit.
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if (MIPSComp::jit)
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MIPSComp::jit->ClearCacheAt(address, length);
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}
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// Interrupts should be served directly on the running thread.
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void MIPSState::Irq()
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{
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// if (IRQEnabled())
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{
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}
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}
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void MIPSState::SWI()
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{
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}
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const char *MIPSState::DisasmAt(u32 compilerPC) {
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static char temp[256];
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MIPSDisAsm(Memory::Read_Instruction(compilerPC), 0, temp);
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@ -126,7 +126,10 @@ public:
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MIPSState();
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~MIPSState();
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void Init();
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void Shutdown();
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void Reset();
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void DoState(PointerWrap &p);
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// MUST start with r and be followed by f!
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@ -181,10 +184,6 @@ public:
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return (vfpuCtrl[VFPU_CTRL_DPREFIX] >> (8 + i)) & 1;
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}
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void Irq();
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void SWI();
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void Abort();
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void SingleStep();
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int RunLoopUntil(u64 globalTicks);
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// To clear jit caches, etc.
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@ -202,6 +201,4 @@ extern MIPSState *currentMIPS;
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extern MIPSDebugInterface *currentDebugMIPS;
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extern MIPSState mipsr4k;
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int MIPS_SingleStep();
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extern const float cst_constants[32];
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@ -235,6 +235,7 @@ void CPU_Shutdown() {
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mixer = 0; // deleted in ShutdownSound
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}
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pspFileSystem.Shutdown();
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mipsr4k.Shutdown();
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Memory::Shutdown();
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}
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