diff --git a/Common/ArmEmitter.cpp b/Common/ArmEmitter.cpp
index 1f58aefd02..8f7a1e843e 100644
--- a/Common/ArmEmitter.cpp
+++ b/Common/ArmEmitter.cpp
@@ -596,44 +596,44 @@ void ARMXEmitter::MRS (ARMReg dest)
 	Write32(condition | (16 << 20) | (15 << 16) | (dest << 12));
 }
 
-void ARMXEmitter::WriteStoreOp(u32 op, ARMReg dest, ARMReg src, Operand2 op2)
+void ARMXEmitter::WriteStoreOp(u32 op, ARMReg result, ARMReg base, Operand2 op2)
 {
 	if (op2.GetData() == 0) // set the preindex bit, but not the W bit!
-		Write32(condition | 0x01800000 | (op << 20) | (dest << 16) | (src << 12) | op2.Imm12());
+		Write32(condition | 0x01800000 | (op << 20) | (base << 16) | (result << 12) | op2.Imm12());
 	else
-		Write32(condition | (op << 20) | (3 << 23) | (dest << 16) | (src << 12) | op2.Imm12()); 
+		Write32(condition | (op << 20) | (3 << 23) | (base << 16) | (result << 12) | op2.Imm12()); 
 }
-void ARMXEmitter::STR  (ARMReg dest, ARMReg src, Operand2 op) { WriteStoreOp(0x40, dest, src, op);}
-void ARMXEmitter::STRH (ARMReg dest, ARMReg src, Operand2 op)
+void ARMXEmitter::STR  (ARMReg result, ARMReg base, Operand2 op) { WriteStoreOp(0x40, result, base, op);}
+void ARMXEmitter::STRH (ARMReg result, ARMReg base, Operand2 op)
 {
 	u8 Imm = op.Imm8();
-	Write32(condition | (0x04 << 20) | (src << 16) | (dest << 12) | ((Imm >> 4) << 8) | (0xB << 4) | (Imm & 0x0F));
+	Write32(condition | (0x04 << 20) | (base << 16) | (result << 12) | ((Imm >> 4) << 8) | (0xB << 4) | (Imm & 0x0F));
 }
-void ARMXEmitter::STRB (ARMReg dest, ARMReg src, Operand2 op) { WriteStoreOp(0x44, dest, src, op);}
-void ARMXEmitter::STR  (ARMReg dest, ARMReg base, Operand2 op2, bool Index, bool Add)
+void ARMXEmitter::STRB (ARMReg result, ARMReg base, Operand2 op) { WriteStoreOp(0x44, result, base, op);}
+void ARMXEmitter::STR  (ARMReg result, ARMReg base, Operand2 op2, bool Index, bool Add)
 {
-	Write32(condition | (0x60 << 20) | (Index << 24) | (Add << 23) | (dest << 16) | (base << 12) | op2.IMMSR());
+	Write32(condition | (0x60 << 20) | (Index << 24) | (Add << 23) | (base << 16) | (result << 12) | op2.IMMSR());
 }
-void ARMXEmitter::STR  (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add)
+void ARMXEmitter::STR  (ARMReg result, ARMReg base, ARMReg offset, bool Index, bool Add)
 {
-	Write32(condition | (0x60 << 20) | (Index << 24) | (Add << 23) | (dest << 16) | (base << 12) | offset);
+	Write32(condition | (0x60 << 20) | (Index << 24) | (Add << 23) | (base << 16) | (result << 12) | offset);
 }
-void ARMXEmitter::STRH (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add)
+void ARMXEmitter::STRH (ARMReg result, ARMReg base, ARMReg offset, bool Index, bool Add)
 {
-	Write32(condition | (0x00 << 20) | (Index << 24) | (Add << 23) | (dest << 16) | (base << 12) | (0xB << 4) | offset);
+	Write32(condition | (0x00 << 20) | (Index << 24) | (Add << 23) | (base << 16) | (result << 12) | (0xB << 4) | offset);
 }
-void ARMXEmitter::STRB (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add)
+void ARMXEmitter::STRB (ARMReg result, ARMReg base, ARMReg offset, bool Index, bool Add)
 {
-	Write32(condition | (0x64 << 20) | (Index << 24) | (Add << 23) | (dest << 16) | (base << 12) | offset);
+	Write32(condition | (0x64 << 20) | (Index << 24) | (Add << 23) | (base << 16) | (result << 12) | offset);
 }
 void ARMXEmitter::LDREX(ARMReg dest, ARMReg base)
 {
 	Write32(condition | (25 << 20) | (base << 16) | (dest << 12) | 0xF9F);
 }
-void ARMXEmitter::STREX(ARMReg dest, ARMReg base, ARMReg op)
+void ARMXEmitter::STREX(ARMReg result, ARMReg base, ARMReg op)
 {
-	_assert_msg_(DYNA_REC, (dest != base && dest != op), "STREX dest can't be other two registers");
-	Write32(condition | (24 << 20) | (base << 16) | (dest << 12) | (0xF9 << 4) | op);
+	_assert_msg_(DYNA_REC, (result != base && result != op), "STREX dest can't be other two registers");
+	Write32(condition | (24 << 20) | (base << 16) | (result << 12) | (0xF9 << 4) | op);
 }
 void ARMXEmitter::DMB ()
 {
diff --git a/Common/ArmEmitter.h b/Common/ArmEmitter.h
index feab20eb86..cc66393422 100644
--- a/Common/ArmEmitter.h
+++ b/Common/ArmEmitter.h
@@ -509,22 +509,22 @@ public:
 	void LDRSB(ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add);
 	void LDRLIT(ARMReg dest, u32 offset, bool Add);
 
-	void STR  (ARMReg dest, ARMReg src, Operand2 op2 = 0);
-	void STRH (ARMReg dest, ARMReg src, Operand2 op2 = 0);
-	void STRB (ARMReg dest, ARMReg src, Operand2 op2 = 0);
+	void STR  (ARMReg result, ARMReg base, Operand2 op2 = 0);
+	void STRH (ARMReg result, ARMReg base, Operand2 op2 = 0);
+	void STRB (ARMReg result, ARMReg base, Operand2 op2 = 0);
 	// Offset adds on to the destination register in STR
-	void STR  (ARMReg dest, ARMReg base, Operand2 op2, bool Index, bool Add);
-	void STR  (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add);
-	void STRH (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add);
-	void STRB (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add);
+	void STR  (ARMReg result, ARMReg base, Operand2 op2, bool Index, bool Add);
+	void STR  (ARMReg result, ARMReg base, ARMReg offset, bool Index, bool Add);
+	void STRH (ARMReg result, ARMReg base, ARMReg offset, bool Index, bool Add);
+	void STRB (ARMReg result, ARMReg base, ARMReg offset, bool Index, bool Add);
 
 	void STMFD(ARMReg dest, bool WriteBack, const int Regnum, ...);
 	void LDMFD(ARMReg dest, bool WriteBack, const int Regnum, ...);
 	
 	// Exclusive Access operations
 	void LDREX(ARMReg dest, ARMReg base);
-	// dest contains the result if the instruction managed to store the value
-	void STREX(ARMReg dest, ARMReg base, ARMReg op);
+	// result contains the result if the instruction managed to store the value
+	void STREX(ARMReg result, ARMReg base, ARMReg op);
 	void DMB ();
 	void SVC(Operand2 op);
 
diff --git a/Core/MIPS/ARM/ArmCompBranch.cpp b/Core/MIPS/ARM/ArmCompBranch.cpp
index bd5eed47c6..75770ed842 100644
--- a/Core/MIPS/ARM/ArmCompBranch.cpp
+++ b/Core/MIPS/ARM/ArmCompBranch.cpp
@@ -147,7 +147,7 @@ void Jit::BranchRSZeroComp(u32 op, ArmGen::CCFlags cc, bool andLink, bool likely
 	if (andLink)
 	{
 		MOVI2R(R0, js.compilerPC + 8);
-		STR(CTXREG, R0, MIPS_REG_RA * 4);
+		STR(R0, CTXREG, MIPS_REG_RA * 4);
 	}
 
 	WriteExit(targetAddr, 0);
@@ -340,7 +340,7 @@ void Jit::Comp_Jump(u32 op)
 
 	case 3: //jal
 		MOVI2R(R0, js.compilerPC + 8);
-		STR(CTXREG, R0, MIPS_REG_RA * 4);
+		STR(R0, CTXREG, MIPS_REG_RA * 4);
 		WriteExit(targetAddr, 0);
 		break;
 
@@ -388,7 +388,7 @@ void Jit::Comp_JumpReg(u32 op)
 		break;
 	case 9: //jalr
 		MOVI2R(R0, js.compilerPC + 8);
-		STR(CTXREG, R0, MIPS_REG_RA * 4);
+		STR(R0, CTXREG, MIPS_REG_RA * 4);
 		break;
 	default:
 		_dbg_assert_msg_(CPU,0,"Trying to compile instruction that can't be compiled");
diff --git a/Core/MIPS/ARM/ArmCompFPU.cpp b/Core/MIPS/ARM/ArmCompFPU.cpp
index 15e581ac8e..e21a2b2fb9 100644
--- a/Core/MIPS/ARM/ArmCompFPU.cpp
+++ b/Core/MIPS/ARM/ArmCompFPU.cpp
@@ -111,7 +111,7 @@ void Jit::Comp_FPUComp(u32 op) {
 	if (opc == 0)//f, sf (signalling false)
 	{
 		MOVI2R(R0, 0);
-		STR(CTXREG, R0, offsetof(MIPSState, fpcond));
+		STR(R0, CTXREG, offsetof(MIPSState, fpcond));
 		return;
 	}
 
@@ -165,7 +165,7 @@ void Jit::Comp_FPUComp(u32 op) {
 	}
 	MOVI2R(R0, 0);
 	SetCC(CC_AL);
-	STR(CTXREG, R0, offsetof(MIPSState, fpcond));
+	STR(R0, CTXREG, offsetof(MIPSState, fpcond));
 }
 
 void Jit::Comp_FPU2op(u32 op)
diff --git a/Core/MIPS/ARM/ArmCompLoadStore.cpp b/Core/MIPS/ARM/ArmCompLoadStore.cpp
index 51d8375838..5ec605200e 100644
--- a/Core/MIPS/ARM/ArmCompLoadStore.cpp
+++ b/Core/MIPS/ARM/ArmCompLoadStore.cpp
@@ -179,17 +179,17 @@ namespace MIPSComp
 					LSR(gpr.R(rt), gpr.R(rt), 24-shift);
 					AND(R0, R0, 0xffffff00 << shift);
 					ORR(R0, R0, gpr.R(rt));
-					STR(R0, gpr.R(rt), R11, true, true);
+					STR(gpr.R(rt), R11, R0, true, true);
 					break;
 				case 46:
 					LSL(gpr.R(rt), gpr.R(rt), shift);
 					AND(R0, R0, 0x00ffffff >> (24 - shift));
 					ORR(R0, R0, gpr.R(rt));
-					STR(R0, gpr.R(rt), R11, true, true);
+					STR(gpr.R(rt), R11, R0, true, true);
 					break;
-				case 43: STR  (R0, gpr.R(rt), R11, true, true); break;
-				case 41: STRH (R0, gpr.R(rt), R11, true, true); break;
-				case 40: STRB (R0, gpr.R(rt), R11, true, true); break;
+				case 43: STR  (gpr.R(rt), R11, R0, true, true); break;
+				case 41: STRH (gpr.R(rt), R11, R0, true, true); break;
+				case 40: STRB (gpr.R(rt), R11, R0, true, true); break;
 				}
 			} else {
 				Comp_Generic(op);
diff --git a/Core/MIPS/ARM/ArmJit.cpp b/Core/MIPS/ARM/ArmJit.cpp
index ae80235f82..f4325414d8 100644
--- a/Core/MIPS/ARM/ArmJit.cpp
+++ b/Core/MIPS/ARM/ArmJit.cpp
@@ -86,21 +86,21 @@ void Jit::FlushPrefixV()
 	if ((js.prefixSFlag & ArmJitState::PREFIX_DIRTY) != 0)
 	{
 		MOVI2R(R0, js.prefixS);
-		STR(CTXREG, R0, offsetof(MIPSState, vfpuCtrl[VFPU_CTRL_SPREFIX]));
+		STR(R0, CTXREG, offsetof(MIPSState, vfpuCtrl[VFPU_CTRL_SPREFIX]));
 		js.prefixSFlag = (ArmJitState::PrefixState) (js.prefixSFlag & ~ArmJitState::PREFIX_DIRTY);
 	}
 
 	if ((js.prefixTFlag & ArmJitState::PREFIX_DIRTY) != 0)
 	{
 		MOVI2R(R0, js.prefixT);
-		STR(CTXREG, R0, offsetof(MIPSState, vfpuCtrl[VFPU_CTRL_TPREFIX]));
+		STR(R0, CTXREG, offsetof(MIPSState, vfpuCtrl[VFPU_CTRL_TPREFIX]));
 		js.prefixTFlag = (ArmJitState::PrefixState) (js.prefixTFlag & ~ArmJitState::PREFIX_DIRTY);
 	}
 
 	if ((js.prefixDFlag & ArmJitState::PREFIX_DIRTY) != 0)
 	{
 		MOVI2R(R0, js.prefixD);
-		STR(CTXREG, R0, offsetof(MIPSState, vfpuCtrl[VFPU_CTRL_DPREFIX]));
+		STR(R0, CTXREG, offsetof(MIPSState, vfpuCtrl[VFPU_CTRL_DPREFIX]));
 		js.prefixDFlag = (ArmJitState::PrefixState) (js.prefixDFlag & ~ArmJitState::PREFIX_DIRTY);
 	}
 }
@@ -295,7 +295,7 @@ void Jit::MovFromPC(ARMReg r) {
 }
 
 void Jit::MovToPC(ARMReg r) {
-	STR(R10, r, offsetof(MIPSState, pc));
+	STR(r, R10, offsetof(MIPSState, pc));
 }
 
 void Jit::WriteDownCount(int offset)
@@ -306,13 +306,13 @@ void Jit::WriteDownCount(int offset)
 	if (TryMakeOperand2(theDowncount, op2)) // We can enlarge this if we used rotations
 	{
 		SUBS(R1, R1, op2);
-		STR(R10, R1, offsetof(MIPSState, downcount));
+		STR(R1, R10, offsetof(MIPSState, downcount));
 	} else {
 		// Should be fine to use R2 here, flushed the regcache anyway.
 		// If js.downcountAmount can be expressed as an Imm8, we don't need this anyway.
 		MOVI2R(R2, theDowncount);
 		SUBS(R1, R1, R2);
-		STR(R10, R1, offsetof(MIPSState, downcount));
+		STR(R1, R10, offsetof(MIPSState, downcount));
 	}
 }
 
diff --git a/Core/MIPS/ARM/ArmJitCache.cpp b/Core/MIPS/ARM/ArmJitCache.cpp
index 57c86e9c45..c0b95c543e 100644
--- a/Core/MIPS/ARM/ArmJitCache.cpp
+++ b/Core/MIPS/ARM/ArmJitCache.cpp
@@ -355,7 +355,7 @@ void ArmJitBlockCache::DestroyBlock(int block_num, bool invalidate)
 	// checkedEntry is the only "linked" entrance so it's enough to overwrite that.
 	ARMXEmitter emit((u8 *)b.checkedEntry);
 	emit.MOVI2R(R0, b.originalAddress);
-	emit.STR(CTXREG, R0, offsetof(MIPSState, pc));
+	emit.STR(R0, CTXREG, offsetof(MIPSState, pc));
 	emit.B(MIPSComp::jit->dispatcher);
 	emit.FlushIcache();
 }
diff --git a/Core/MIPS/ARM/ArmRegCache.cpp b/Core/MIPS/ARM/ArmRegCache.cpp
index 5a7f5cac50..32b3111028 100644
--- a/Core/MIPS/ARM/ArmRegCache.cpp
+++ b/Core/MIPS/ARM/ArmRegCache.cpp
@@ -168,7 +168,7 @@ void ArmRegCache::FlushArmReg(ARMReg r) {
 	}
 	if (ar[r].mipsReg != -1) {
 		if (ar[r].isDirty && mr[ar[r].mipsReg].loc == ML_ARMREG)
-			emit->STR(CTXREG, r, GetMipsRegOffset(ar[r].mipsReg));
+			emit->STR(r, CTXREG, GetMipsRegOffset(ar[r].mipsReg));
 		// IMMs won't be in an ARM reg.
 		mr[ar[r].mipsReg].loc = ML_MEM;
 		mr[ar[r].mipsReg].reg = INVALID_REG;
@@ -185,7 +185,7 @@ void ArmRegCache::FlushR(MIPSReg r) {
 	case ML_IMM:
 		// IMM is always "dirty".
 		emit->MOVI2R(R0, mr[r].imm);
-		emit->STR(CTXREG, R0, GetMipsRegOffset(r));
+		emit->STR(R0, CTXREG, GetMipsRegOffset(r));
 		break;
 
 	case ML_ARMREG:
@@ -193,7 +193,7 @@ void ArmRegCache::FlushR(MIPSReg r) {
 			ERROR_LOG(HLE, "FlushMipsReg: MipsReg had bad ArmReg");
 		}
 		if (ar[mr[r].reg].isDirty) {
-			emit->STR(CTXREG, (ARMReg)mr[r].reg, GetMipsRegOffset(r));
+			emit->STR((ARMReg)mr[r].reg, CTXREG, GetMipsRegOffset(r));
 			ar[mr[r].reg].isDirty = false;
 		}
 		ar[mr[r].reg].mipsReg = -1;
diff --git a/Core/MIPS/ARM/ArmRegCacheFPU.cpp b/Core/MIPS/ARM/ArmRegCacheFPU.cpp
index 98a0f5bca8..0bc0764018 100644
--- a/Core/MIPS/ARM/ArmRegCacheFPU.cpp
+++ b/Core/MIPS/ARM/ArmRegCacheFPU.cpp
@@ -192,7 +192,7 @@ void ArmRegCacheFPU::FlushArmReg(ARMReg r) {
 		if (ar[reg].isDirty && mr[ar[reg].mipsReg].loc == ML_ARMREG)
 		{
 			//INFO_LOG(HLE, "Flushing ARM reg %i", reg);
-			emit->VSTR(r, CTXREG, GetMipsRegOffset(ar[reg].mipsReg));
+			emit->VSTR(CTXREG, r, GetMipsRegOffset(ar[reg].mipsReg));
 		}
 		// IMMs won't be in an ARM reg.
 		mr[ar[reg].mipsReg].loc = ML_MEM;
@@ -218,7 +218,7 @@ void ArmRegCacheFPU::FlushR(MIPSReg r) {
 		}
 		if (ar[mr[r].reg].isDirty) {
 			//INFO_LOG(HLE, "Flushing dirty reg %i", mr[r].reg);
-			emit->VSTR((ARMReg)(mr[r].reg + S0), CTXREG, GetMipsRegOffset(r));
+			emit->VSTR(CTXREG, (ARMReg)(mr[r].reg + S0), GetMipsRegOffset(r));
 			ar[mr[r].reg].isDirty = false;
 		}
 		ar[mr[r].reg].mipsReg = -1;