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https://github.com/hrydgard/ppsspp.git
synced 2025-04-02 11:01:50 -04:00
more recompiled fpu (not tested)
This commit is contained in:
Ced2911
parent
e90d9c035a
commit
23637db54c
1 changed files with 194 additions and 24 deletions
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@ -10,14 +10,17 @@
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#include "ppcEmitter.h"
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#include "PpcJit.h"
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#define _RS ((op>>21) & 0x1F)
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#define _RT ((op>>16) & 0x1F)
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#define _RD ((op>>11) & 0x1F)
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#define _FS ((op>>11) & 0x1F)
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#define _FT ((op>>16) & 0x1F)
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#define _FD ((op>>6 ) & 0x1F)
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#define _POS ((op>>6 ) & 0x1F)
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#define _RS MIPS_GET_RS(op)
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#define _RT MIPS_GET_RT(op)
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#define _RD MIPS_GET_RD(op)
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#define _FS MIPS_GET_FS(op)
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#define _FT MIPS_GET_FT(op)
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#define _FD MIPS_GET_FD(op)
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#define _SA MIPS_GET_SA(op)
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#define _POS ((op>> 6) & 0x1F)
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#define _SIZE ((op>>11) & 0x1F)
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#define _IMM16 (signed short)(op & 0xFFFF)
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#define _IMM26 (op & 0x03FFFFFF)
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE.
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@ -44,20 +47,6 @@ void Jit::Comp_FPU3op(MIPSOpcode op) {
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case 0: FADDS(fpr.R(fd), fpr.R(fs), fpr.R(ft)); break; //F(fd) = F(fs) + F(ft); //add
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case 1: FSUBS(fpr.R(fd), fpr.R(fs), fpr.R(ft)); break; //F(fd) = F(fs) - F(ft); //sub
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case 2: { //F(fd) = F(fs) * F(ft); //mul
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/*
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u32 nextOp = Memory::Read_Instruction(js.compilerPC + 4);
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// Optimization possible if destination is the same
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if (fd == (int)((nextOp>>6) & 0x1F)) {
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// VMUL + VNEG -> VNMUL
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if (!strcmp(MIPSGetName(nextOp), "neg.s")) {
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if (fd == (int)((nextOp>>11) & 0x1F)) {
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VNMUL(fpr.R(fd), fpr.R(fs), fpr.R(ft));
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EatInstruction(nextOp);
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}
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return;
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}
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}
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*/
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FMULS(fpr.R(fd), fpr.R(fs), fpr.R(ft));
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break;
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}
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@ -100,7 +89,6 @@ void Jit::Comp_FPULS(MIPSOpcode op) {
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fpr.MapReg(ft);
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if (gpr.IsImm(rs)) {
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u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF;
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MOVI2R(R0, addr);
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MOVI2R(SREG, addr);
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} else {
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gpr.MapReg(rs);
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@ -116,8 +104,122 @@ void Jit::Comp_FPULS(MIPSOpcode op) {
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}
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}
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/**
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This can be made with branch, but i'm trying to do it branch free, not tested yet ...
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**/
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void Jit::Comp_FPUComp(MIPSOpcode op) {
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Comp_Generic(op);
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DISABLE;
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CONDITIONAL_DISABLE;
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int opc = op & 0xF;
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if (opc >= 8) opc -= 8; // alias
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if (opc == 0) { // f, sf (signalling false)
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MOVI2R(SREG, 0);
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STW(SREG, CTXREG, offsetof(MIPSState, fpcond));
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return;
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}
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int fs = _FS;
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int ft = _FT;
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fpr.MapInIn(fs, ft);
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PPCReg _tmp = FPR8;
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PPCReg _zero = FPR6;
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PPCReg _one = FPR7;
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//VCMP(fpr.R(fs), fpr.R(ft));
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//VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags).
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/**
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Condition-Register Field and Floating-Point Condition Code Interpretation
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Bit Name Description
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0 FL (FRA) < (FRB)
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1 FG (FRA) > (FRB)
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2 FE (FRA) = (FRB)
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3 FU (FRA) ? (FRB) (unordered)
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**/
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switch(opc)
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{
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case 1: // un, ngle (unordered)
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Break();
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// CR0 = cmp fs, fs
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FCMPU(0, fpr.R(fs), fpr.R(ft));
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// SREG = CR
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MFCR(SREG);
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// SREG = (SREG >> 3) & 1
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SRAWI(SREG, SREG, 3);
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ANDI(SREG, SREG, 0x1);
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break;
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case 2: //eq, seq (equal, ordered)
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Break();
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FCMPO(0, fpr.R(fs), fpr.R(ft));
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MFCR(SREG);
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// SREG = (SREG >> 2) & 1
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SRAWI(SREG, SREG, 2);
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ANDI(SREG, SREG, 0x1);
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break;
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case 3: // ueq, ngl (equal, unordered)
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Break();
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FCMPU(0, fpr.R(fs), fpr.R(ft));
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MFCR(R7);
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// SREG = (R7 >> 2) & 1
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SRAWI(SREG, R7, 2);
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ANDI(SREG, SREG, 0x1);
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// check unordered
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// R8 = (R7 >> 3) & 1
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SRAWI(R8, R7, 3);
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ANDI(R8, R8, 0x1);
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// SREG = ((R7 >> 2) & 1) || ((R8 >> 3) & 1)
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OR(SREG, R7, R8);
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return;
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case 4: // olt, lt (less than, ordered)
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Break();
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FCMPO(0, fpr.R(fs), fpr.R(ft));
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MFCR(SREG);
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// SREG = SREG & 1
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ANDI(SREG, SREG, 0x1);
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break;
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case 5: // ult, nge (less than, unordered)
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Break();
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FCMPO(0, fpr.R(fs), fpr.R(ft));
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MFCR(R7);
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// SREG = SREG & 1
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ANDI(SREG, R7, 0x1);
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// check unordered
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// R8 = (R7 >> 3) & 1
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SRAWI(R8, R7, 3);
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ANDI(R8, R8, 0x1);
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// SREG = (R7 & 1) || ((R8 >> 3) & 1)
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OR(SREG, R7, R8);
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break;
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case 6: // ole, le (less equal, ordered)
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Break();
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FCMPO(0, fpr.R(ft), fpr.R(fs));
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MFCR(SREG);
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// SREG = (SREG >> 1) & 1
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SRAWI(SREG, SREG, 1);
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ANDI(SREG, SREG, 0x1);
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break;
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case 7: // ule, ngt (less equal, unordered)
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Break();
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FCMPO(0, fpr.R(ft), fpr.R(fs));
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MFCR(R7);
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// SREG = (SREG >> 1) & 1
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SRAWI(SREG, R7, 1);
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ANDI(SREG, SREG, 0x1);
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// check unordered
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// R8 = (R7 >> 3) & 1
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SRAWI(R8, R7, 3);
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ANDI(R8, R8, 0x1);
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// SREG = (R7 & 1) || ((R8 >> 3) & 1)
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OR(SREG, R7, R8);
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break;
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default:
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Comp_Generic(op);
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return;
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}
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STW(SREG, CTXREG, offsetof(MIPSState, fpcond));
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}
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void Jit::Comp_FPU2op(MIPSOpcode op) {
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@ -150,8 +252,76 @@ void Jit::Comp_FPU2op(MIPSOpcode op) {
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}
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}
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/**
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Not tested yet
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**/
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void Jit::Comp_mxc1(MIPSOpcode op) {
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Comp_Generic(op);
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DISABLE;
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CONDITIONAL_DISABLE;
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int fs = _FS;
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MIPSGPReg rt = _RT;
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switch ((op >> 21) & 0x1f)
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{
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case 0: // R(rt) = FI(fs); break; //mfc1
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// Let's just go through RAM for now.
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fpr.FlushR(fs);
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gpr.MapReg(rt, MAP_DIRTY | MAP_NOINIT);
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LWZ(gpr.R(rt), CTXREG, fpr.GetMipsRegOffset(fs));
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return;
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case 2: //cfc1
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if (fs == 31)
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{
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/* Todo Lazy code ! */
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gpr.MapReg(rt, MAP_DIRTY | MAP_NOINIT);
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PPCReg _rt = gpr.R(rt);
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// SREG = fpcond & 1;
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LWZ(SREG, CTXREG, offsetof(MIPSState, fpcond));
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ANDI(SREG, SREG, 1); // Just in case
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// SREG << 23
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SLWI(SREG, SREG, 23);
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// RT = fcr31 & ~(1<<23)
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LWZ(_rt, CTXREG, offsetof(MIPSState, fcr31));
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MOVI2R(R8, ~(1<<23));
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AND(_rt, _rt, R8);
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// RT = RT | SREG
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OR(_rt, _rt, SREG);
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}
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else if (fs == 0)
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{
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gpr.MapReg(rt, MAP_DIRTY | MAP_NOINIT);
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LWZ(gpr.R(rt), CTXREG, offsetof(MIPSState, fcr0));
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}
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return;
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case 4: //FI(fs) = R(rt); break; //mtc1
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// Let's just go through RAM for now.
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gpr.FlushR(rt);
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fpr.MapReg(fs, MAP_DIRTY | MAP_NOINIT);
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LFS(fpr.R(fs), CTXREG, gpr.GetMipsRegOffset(rt));
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return;
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case 6: //ctc1
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if (fs == 31)
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{
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gpr.MapReg(rt, 0);
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// Update MIPS state
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// fcr31 = rt
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STW(gpr.R(rt), CTXREG, offsetof(MIPSState, fcr31));
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// fpcond = (rt >> 23) & 1;
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SRWI(SREG, gpr.R(rt), 23);
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ANDI(SREG, SREG, 1);
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STW(SREG, CTXREG, offsetof(MIPSState, fpcond));
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}
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return;
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}
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}
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}
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