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Optimize some common ops for immediates
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parent
5983925fc5
commit
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2 changed files with 40 additions and 13 deletions
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@ -39,8 +39,10 @@ using namespace MIPSAnalyst;
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namespace MIPSComp
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namespace MIPSComp
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{
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{
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static u32 EvalOr(u32 a, u32 b) { return a | b; }
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static u32 EvalOr(u32 a, u32 b) { return a | b; }
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static u32 EvalXor(u32 a, u32 b) { return a ^ b; }
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static u32 EvalEor(u32 a, u32 b) { return a ^ b; }
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static u32 EvalAnd(u32 a, u32 b) { return a & b; }
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static u32 EvalAnd(u32 a, u32 b) { return a & b; }
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static u32 EvalAdd(u32 a, u32 b) { return a + b; }
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static u32 EvalSub(u32 a, u32 b) { return a - b; }
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void Jit::CompImmLogic(int rs, int rt, u32 uimm, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg src, Operand2 op2), u32 (*eval)(u32 a, u32 b))
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void Jit::CompImmLogic(int rs, int rt, u32 uimm, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg src, Operand2 op2), u32 (*eval)(u32 a, u32 b))
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{
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{
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@ -99,7 +101,7 @@ namespace MIPSComp
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case 12: CompImmLogic(rs, rt, uimm, &ARMXEmitter::AND, &EvalAnd); break;
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case 12: CompImmLogic(rs, rt, uimm, &ARMXEmitter::AND, &EvalAnd); break;
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case 13: CompImmLogic(rs, rt, uimm, &ARMXEmitter::ORR, &EvalOr); break;
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case 13: CompImmLogic(rs, rt, uimm, &ARMXEmitter::ORR, &EvalOr); break;
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case 14: CompImmLogic(rs, rt, uimm, &ARMXEmitter::EOR, &EvalXor); break;
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case 14: CompImmLogic(rs, rt, uimm, &ARMXEmitter::EOR, &EvalEor); break;
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case 10: // R(rt) = (s32)R(rs) < simm; break; //slti
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case 10: // R(rt) = (s32)R(rs) < simm; break; //slti
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{
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{
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@ -181,6 +183,33 @@ namespace MIPSComp
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}
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}
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}
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}
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void Jit::CompType3(int rd, int rs, int rt, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg rm, Operand2 rn), u32 (*eval)(u32 a, u32 b), bool isSub)
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{
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if (gpr.IsImm(rs) && gpr.IsImm(rt)) {
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gpr.SetImm(rd, (*eval)(gpr.GetImm(rs), gpr.GetImm(rt)));
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} else if (gpr.IsImm(rt)) {
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u32 rtImm = gpr.GetImm(rt);
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gpr.MapDirtyIn(rd, rs);
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Operand2 op2;
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if (TryMakeOperand2(rtImm, op2)) {
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(this->*arith)(gpr.R(rd), gpr.R(rs), op2);
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} else {
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MOVI2R(R0, rtImm);
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(this->*arith)(gpr.R(rd), gpr.R(rs), R0);
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}
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} else if (gpr.IsImm(rs)) {
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u32 rsImm = gpr.GetImm(rs);
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gpr.MapDirtyIn(rd, rt);
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// TODO: Special case when rsImm can be represented as an Operand2
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MOVI2R(R0, rsImm);
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(this->*arith)(gpr.R(rd), R0, gpr.R(rt));
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} else {
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// Generic solution
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gpr.MapDirtyInIn(rd, rs, rt);
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(this->*arith)(gpr.R(rd), gpr.R(rs), gpr.R(rt));
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}
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}
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void Jit::Comp_RType3(u32 op)
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void Jit::Comp_RType3(u32 op)
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{
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{
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CONDITIONAL_DISABLE;
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CONDITIONAL_DISABLE;
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@ -251,26 +280,22 @@ namespace MIPSComp
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gpr.MapDirtyIn(rd, rs);
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gpr.MapDirtyIn(rd, rs);
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MOV(gpr.R(rd), gpr.R(rs));
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MOV(gpr.R(rd), gpr.R(rs));
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} else {
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} else {
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gpr.MapDirtyInIn(rd, rs, rt);
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CompType3(rd, rs, rt, &ARMXEmitter::ADD, &EvalAdd);
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ADD(gpr.R(rd), gpr.R(rs), gpr.R(rt));
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}
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}
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break;
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break;
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case 34: //R(rd) = R(rs) - R(rt); break; //sub
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case 34: //R(rd) = R(rs) - R(rt); break; //sub
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case 35:
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case 35: //R(rd) = R(rs) - R(rt); break; //subu
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gpr.MapDirtyInIn(rd, rs, rt);
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CompType3(rd, rs, rt, &ARMXEmitter::SUB, &EvalSub, true);
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SUB(gpr.R(rd), gpr.R(rs), gpr.R(rt));
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break;
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break;
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case 36: //R(rd) = R(rs) & R(rt); break; //and
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case 36: //R(rd) = R(rs) & R(rt); break; //and
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gpr.MapDirtyInIn(rd, rs, rt);
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CompType3(rd, rs, rt, &ARMXEmitter::AND, &EvalAnd);
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AND(gpr.R(rd), gpr.R(rs), gpr.R(rt));
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break;
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break;
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case 37: //R(rd) = R(rs) | R(rt); break; //or
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case 37: //R(rd) = R(rs) | R(rt); break; //or
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gpr.MapDirtyInIn(rd, rs, rt);
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CompType3(rd, rs, rt, &ARMXEmitter::ORR, &EvalOr);
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ORR(gpr.R(rd), gpr.R(rs), gpr.R(rt));
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break;
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break;
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case 38: //R(rd) = R(rs) ^ R(rt); break; //xor/eor
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case 38: //R(rd) = R(rs) ^ R(rt); break; //xor/eor
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gpr.MapDirtyInIn(rd, rs, rt);
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CompType3(rd, rs, rt, &ARMXEmitter::EOR, &EvalEor);
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EOR(gpr.R(rd), gpr.R(rs), gpr.R(rt));
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break;
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break;
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case 39: // R(rd) = ~(R(rs) | R(rt)); break; //nor
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case 39: // R(rd) = ~(R(rs) | R(rt)); break; //nor
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@ -219,6 +219,8 @@ private:
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// Utilities to reduce duplicated code
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// Utilities to reduce duplicated code
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void CompImmLogic(int rs, int rt, u32 uimm, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg src, Operand2 op2), u32 (*eval)(u32 a, u32 b));
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void CompImmLogic(int rs, int rt, u32 uimm, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg src, Operand2 op2), u32 (*eval)(u32 a, u32 b));
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void CompType3(int rd, int rs, int rt, void (ARMXEmitter::*arithOp2)(ARMReg dst, ARMReg rm, Operand2 rn), u32 (*eval)(u32 a, u32 b), bool isSub = false);
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void CompShiftImm(u32 op, ArmGen::ShiftType shiftType);
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void CompShiftImm(u32 op, ArmGen::ShiftType shiftType);
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void CompShiftVar(u32 op, ArmGen::ShiftType shiftType);
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void CompShiftVar(u32 op, ArmGen::ShiftType shiftType);
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