Emulation/ppsspp
1
0
Fork 0
mirror of https://github.com/hrydgard/ppsspp.git synced 2025-04-02 11:01:50 -04:00
Code Issues Projects Releases Packages Wiki Activity

Optimize some common ops for immediates

Browse source
This commit is contained in:
Henrik Rydgard 2013-03-10 00:48:44 +01:00
parent 5983925fc5
commit 216dc7ad65
2 changed files with 40 additions and 13 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

51
Core/MIPS/ARM/ArmCompALU.cpp
View file

@ -39,8 +39,10 @@ using namespace MIPSAnalyst;
namespace MIPSComp namespace MIPSComp
{ {
static u32 EvalOr(u32 a, u32 b) { return a | b; } static u32 EvalOr(u32 a, u32 b) { return a | b; }
static u32 EvalXor(u32 a, u32 b) { return a ^ b; } static u32 EvalEor(u32 a, u32 b) { return a ^ b; }
static u32 EvalAnd(u32 a, u32 b) { return a & b; } static u32 EvalAnd(u32 a, u32 b) { return a & b; }
static u32 EvalAdd(u32 a, u32 b) { return a + b; }
static u32 EvalSub(u32 a, u32 b) { return a - b; }
void Jit::CompImmLogic(int rs, int rt, u32 uimm, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg src, Operand2 op2), u32 (*eval)(u32 a, u32 b)) void Jit::CompImmLogic(int rs, int rt, u32 uimm, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg src, Operand2 op2), u32 (*eval)(u32 a, u32 b))
{ {
@ -99,7 +101,7 @@ namespace MIPSComp
case 12: CompImmLogic(rs, rt, uimm, &ARMXEmitter::AND, &EvalAnd); break; case 12: CompImmLogic(rs, rt, uimm, &ARMXEmitter::AND, &EvalAnd); break;
case 13: CompImmLogic(rs, rt, uimm, &ARMXEmitter::ORR, &EvalOr); break; case 13: CompImmLogic(rs, rt, uimm, &ARMXEmitter::ORR, &EvalOr); break;
case 14: CompImmLogic(rs, rt, uimm, &ARMXEmitter::EOR, &EvalXor); break; case 14: CompImmLogic(rs, rt, uimm, &ARMXEmitter::EOR, &EvalEor); break;
case 10: // R(rt) = (s32)R(rs) < simm; break; //slti case 10: // R(rt) = (s32)R(rs) < simm; break; //slti
{ {
@ -181,6 +183,33 @@ namespace MIPSComp
} }
} }
void Jit::CompType3(int rd, int rs, int rt, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg rm, Operand2 rn), u32 (*eval)(u32 a, u32 b), bool isSub)
{
if (gpr.IsImm(rs) && gpr.IsImm(rt)) {
gpr.SetImm(rd, (*eval)(gpr.GetImm(rs), gpr.GetImm(rt)));
} else if (gpr.IsImm(rt)) {
u32 rtImm = gpr.GetImm(rt);
gpr.MapDirtyIn(rd, rs);
Operand2 op2;
if (TryMakeOperand2(rtImm, op2)) {
(this->*arith)(gpr.R(rd), gpr.R(rs), op2);
} else {
MOVI2R(R0, rtImm);
(this->*arith)(gpr.R(rd), gpr.R(rs), R0);
}
} else if (gpr.IsImm(rs)) {
u32 rsImm = gpr.GetImm(rs);
gpr.MapDirtyIn(rd, rt);
// TODO: Special case when rsImm can be represented as an Operand2
MOVI2R(R0, rsImm);
(this->*arith)(gpr.R(rd), R0, gpr.R(rt));
} else {
// Generic solution
gpr.MapDirtyInIn(rd, rs, rt);
(this->*arith)(gpr.R(rd), gpr.R(rs), gpr.R(rt));
}
}
void Jit::Comp_RType3(u32 op) void Jit::Comp_RType3(u32 op)
{ {
CONDITIONAL_DISABLE; CONDITIONAL_DISABLE;
@ -251,26 +280,22 @@ namespace MIPSComp
gpr.MapDirtyIn(rd, rs); gpr.MapDirtyIn(rd, rs);
MOV(gpr.R(rd), gpr.R(rs)); MOV(gpr.R(rd), gpr.R(rs));
} else { } else {
gpr.MapDirtyInIn(rd, rs, rt); CompType3(rd, rs, rt, &ARMXEmitter::ADD, &EvalAdd);
ADD(gpr.R(rd), gpr.R(rs), gpr.R(rt));
} }
break; break;
case 34: //R(rd) = R(rs) - R(rt); break; //sub case 34: //R(rd) = R(rs) - R(rt); break; //sub
case 35: case 35: //R(rd) = R(rs) - R(rt); break; //subu
gpr.MapDirtyInIn(rd, rs, rt); CompType3(rd, rs, rt, &ARMXEmitter::SUB, &EvalSub, true);
SUB(gpr.R(rd), gpr.R(rs), gpr.R(rt));
break; break;
case 36: //R(rd) = R(rs) & R(rt); break; //and case 36: //R(rd) = R(rs) & R(rt); break; //and
gpr.MapDirtyInIn(rd, rs, rt); CompType3(rd, rs, rt, &ARMXEmitter::AND, &EvalAnd);
AND(gpr.R(rd), gpr.R(rs), gpr.R(rt));
break; break;
case 37: //R(rd) = R(rs) | R(rt); break; //or case 37: //R(rd) = R(rs) | R(rt); break; //or
gpr.MapDirtyInIn(rd, rs, rt); CompType3(rd, rs, rt, &ARMXEmitter::ORR, &EvalOr);
ORR(gpr.R(rd), gpr.R(rs), gpr.R(rt));
break; break;
case 38: //R(rd) = R(rs) ^ R(rt); break; //xor/eor case 38: //R(rd) = R(rs) ^ R(rt); break; //xor/eor
gpr.MapDirtyInIn(rd, rs, rt); CompType3(rd, rs, rt, &ARMXEmitter::EOR, &EvalEor);
EOR(gpr.R(rd), gpr.R(rs), gpr.R(rt));
break; break;
case 39: // R(rd) = ~(R(rs) | R(rt)); break; //nor case 39: // R(rd) = ~(R(rs) | R(rt)); break; //nor

2
Core/MIPS/ARM/ArmJit.h
View file

@ -219,6 +219,8 @@ private:
// Utilities to reduce duplicated code // Utilities to reduce duplicated code
void CompImmLogic(int rs, int rt, u32 uimm, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg src, Operand2 op2), u32 (*eval)(u32 a, u32 b)); void CompImmLogic(int rs, int rt, u32 uimm, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg src, Operand2 op2), u32 (*eval)(u32 a, u32 b));
void CompType3(int rd, int rs, int rt, void (ARMXEmitter::*arithOp2)(ARMReg dst, ARMReg rm, Operand2 rn), u32 (*eval)(u32 a, u32 b), bool isSub = false);
void CompShiftImm(u32 op, ArmGen::ShiftType shiftType); void CompShiftImm(u32 op, ArmGen::ShiftType shiftType);
void CompShiftVar(u32 op, ArmGen::ShiftType shiftType); void CompShiftVar(u32 op, ArmGen::ShiftType shiftType);