diff --git a/Core/MIPS/ARM/ArmRegCache.cpp b/Core/MIPS/ARM/ArmRegCache.cpp
index f1334edee7..80000ce026 100644
--- a/Core/MIPS/ARM/ArmRegCache.cpp
+++ b/Core/MIPS/ARM/ArmRegCache.cpp
@@ -295,7 +295,8 @@ allocate:
 
 	if (bestToSpill != INVALID_REG) {
 		// ERROR_LOG(JIT, "Out of registers at PC %08x - spills register %i.", mips_->pc, bestToSpill);
-		if (clobbered) {
+		// TODO: Something is wrong with our flags or clobber detection.  Disabling for now.
+		if (clobbered && false) {
 			DiscardR(ar[bestToSpill].mipsReg);
 		} else {
 			FlushArmReg(bestToSpill);
diff --git a/Core/MIPS/x86/RegCache.cpp b/Core/MIPS/x86/RegCache.cpp
index c8cef7ccb7..94f770413f 100644
--- a/Core/MIPS/x86/RegCache.cpp
+++ b/Core/MIPS/x86/RegCache.cpp
@@ -174,7 +174,8 @@ X64Reg GPRRegCache::GetFreeXReg()
 	}
 
 	if (bestToSpill != INVALID_REG) {
-		if (clobbered) {
+		// TODO: Something is wrong with our flags or clobber detection.  Disabling for now.
+		if (clobbered && false) {
 			DiscardRegContentsIfCached(xregs[bestToSpill].mipsReg);
 		} else {
 			StoreFromRegister(xregs[bestToSpill].mipsReg);