From 0fc8274ec4e084297aba95c38f106320888df78c Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Fri, 29 Dec 2017 17:15:21 -0800 Subject: [PATCH] arm64jit: Enable safe memory for lwl/lwr. --- Core/MIPS/ARM64/Arm64CompLoadStore.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Core/MIPS/ARM64/Arm64CompLoadStore.cpp b/Core/MIPS/ARM64/Arm64CompLoadStore.cpp index 5219c1a239..856d3e71cb 100644 --- a/Core/MIPS/ARM64/Arm64CompLoadStore.cpp +++ b/Core/MIPS/ARM64/Arm64CompLoadStore.cpp @@ -176,18 +176,18 @@ namespace MIPSComp { } else { gpr.MapInIn(rt, rs); } + gpr.SpillLock(rt); + gpr.SpillLock(rs); + // Need to get temps before skipping safe mem. + ARM64Reg LR_SCRATCH3 = gpr.GetAndLockTempR(); + ARM64Reg LR_SCRATCH4 = gpr.GetAndLockTempR(); - if (false && !g_Config.bFastMemory && rs != MIPS_REG_SP) { + if (!g_Config.bFastMemory && rs != MIPS_REG_SP) { skips = SetScratch1ForSafeAddress(rs, offset, SCRATCH2); } else { SetScratch1ToEffectiveAddress(rs, offset); } - // We can lose rs now, since we have it in SCRATCH1. - gpr.SpillLock(rt); - ARM64Reg LR_SCRATCH3 = gpr.GetAndLockTempR(); - ARM64Reg LR_SCRATCH4 = gpr.GetAndLockTempR(); - // Here's our shift amount. ANDI2R(SCRATCH2, SCRATCH1, 3); LSL(SCRATCH2, SCRATCH2, 3);