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x86jit: Consistently use mips_.

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Unknown W. Brackets 2014-10-12 15:16:09 -07:00
parent afbe50d3b9
commit 0f32103615
5 changed files with 24 additions and 26 deletions
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2
Core/MIPS/ARM/ArmCompVFPU.cpp
View file

@ -1252,8 +1252,6 @@ namespace MIPSComp
gpr.MapReg(rt); gpr.MapReg(rt);
STR(gpr.R(rt), CTXREG, offsetof(MIPSState, vfpuCtrl) + 4 * (imm - 128)); STR(gpr.R(rt), CTXREG, offsetof(MIPSState, vfpuCtrl) + 4 * (imm - 128));
} }
//gpr.BindToRegister(rt, true, false);
//MOV(32, M(&currentMIPS->vfpuCtrl[imm - 128]), gpr.R(rt));
// TODO: Optimization if rt is Imm? // TODO: Optimization if rt is Imm?
// Set these BEFORE disable! // Set these BEFORE disable!

4
Core/MIPS/PPC/PpcCompVFPU.cpp
View file

@ -671,7 +671,7 @@ namespace MIPSComp
// In case we have a saved prefix. // In case we have a saved prefix.
//FlushPrefixV(); //FlushPrefixV();
//gpr.BindToRegister(rt, false, true); //gpr.BindToRegister(rt, false, true);
//MOV(32, gpr.R(rt), M(&currentMIPS->vfpuCtrl[imm - 128])); //MOV(32, gpr.R(rt), M(&mips_->vfpuCtrl[imm - 128]));
} else { } else {
//ERROR - maybe need to make this value too an "interlock" value? //ERROR - maybe need to make this value too an "interlock" value?
ERROR_LOG(CPU, "mfv - invalid register %i", imm); ERROR_LOG(CPU, "mfv - invalid register %i", imm);
@ -688,7 +688,7 @@ namespace MIPSComp
gpr.MapReg(rt); gpr.MapReg(rt);
STW(gpr.R(rt), CTXREG, offsetof(MIPSState, vfpuCtrl) + 4 * (imm - 128)); STW(gpr.R(rt), CTXREG, offsetof(MIPSState, vfpuCtrl) + 4 * (imm - 128));
//gpr.BindToRegister(rt, true, false); //gpr.BindToRegister(rt, true, false);
//MOV(32, M(&currentMIPS->vfpuCtrl[imm - 128]), gpr.R(rt)); //MOV(32, M(&mips_->vfpuCtrl[imm - 128]), gpr.R(rt));
// TODO: Optimization if rt is Imm? // TODO: Optimization if rt is Imm?
// Set these BEFORE disable! // Set these BEFORE disable!

2
Core/MIPS/x86/CompBranch.cpp
View file

@ -650,7 +650,7 @@ void Jit::Comp_JumpReg(MIPSOpcode op)
{ {
// If this is a syscall, write the pc (for thread switching and other good reasons.) // If this is a syscall, write the pc (for thread switching and other good reasons.)
gpr.MapReg(rs, true, false); gpr.MapReg(rs, true, false);
MOV(32, M(&currentMIPS->pc), gpr.R(rs)); MOV(32, M(&mips_->pc), gpr.R(rs));
if (andLink) if (andLink)
gpr.SetImm(rd, js.compilerPC + 8); gpr.SetImm(rd, js.compilerPC + 8);
CompileDelaySlot(DELAYSLOT_FLUSH); CompileDelaySlot(DELAYSLOT_FLUSH);

8
Core/MIPS/x86/CompVFPU.cpp
View file

@ -1697,7 +1697,7 @@ void Jit::Comp_Mftv(MIPSOpcode op) {
// In case we have a saved prefix. // In case we have a saved prefix.
FlushPrefixV(); FlushPrefixV();
gpr.MapReg(rt, false, true); gpr.MapReg(rt, false, true);
MOV(32, gpr.R(rt), M(&currentMIPS->vfpuCtrl[imm - 128])); MOV(32, gpr.R(rt), M(&mips_->vfpuCtrl[imm - 128]));
} }
} else { } else {
//ERROR - maybe need to make this value too an "interlock" value? //ERROR - maybe need to make this value too an "interlock" value?
@ -1724,7 +1724,7 @@ void Jit::Comp_Mftv(MIPSOpcode op) {
} }
} else { } else {
gpr.MapReg(rt, true, false); gpr.MapReg(rt, true, false);
MOV(32, M(&currentMIPS->vfpuCtrl[imm - 128]), gpr.R(rt)); MOV(32, M(&mips_->vfpuCtrl[imm - 128]), gpr.R(rt));
} }
// TODO: Optimization if rt is Imm? // TODO: Optimization if rt is Imm?
@ -1756,7 +1756,7 @@ void Jit::Comp_Vmfvc(MIPSOpcode op) {
gpr.MapReg(MIPS_REG_VFPUCC, true, false); gpr.MapReg(MIPS_REG_VFPUCC, true, false);
MOVD_xmm(fpr.VX(vs), gpr.R(MIPS_REG_VFPUCC)); MOVD_xmm(fpr.VX(vs), gpr.R(MIPS_REG_VFPUCC));
} else { } else {
MOVSS(fpr.VX(vs), M(&currentMIPS->vfpuCtrl[imm - 128])); MOVSS(fpr.VX(vs), M(&mips_->vfpuCtrl[imm - 128]));
} }
fpr.ReleaseSpillLocks(); fpr.ReleaseSpillLocks();
} }
@ -1772,7 +1772,7 @@ void Jit::Comp_Vmtvc(MIPSOpcode op) {
gpr.MapReg(MIPS_REG_VFPUCC, false, true); gpr.MapReg(MIPS_REG_VFPUCC, false, true);
MOVD_xmm(gpr.R(MIPS_REG_VFPUCC), fpr.VX(vs)); MOVD_xmm(gpr.R(MIPS_REG_VFPUCC), fpr.VX(vs));
} else { } else {
MOVSS(M(&currentMIPS->vfpuCtrl[imm - 128]), fpr.VX(vs)); MOVSS(M(&mips_->vfpuCtrl[imm - 128]), fpr.VX(vs));
} }
fpr.ReleaseSpillLocks(); fpr.ReleaseSpillLocks();

34
Core/MIPS/x86/Jit.cpp
View file

@ -218,7 +218,7 @@ void Jit::FlushPrefixV()
void Jit::WriteDowncount(int offset) void Jit::WriteDowncount(int offset)
{ {
const int downcount = js.downcountAmount + offset; const int downcount = js.downcountAmount + offset;
SUB(32, M(&currentMIPS->downcount), downcount > 127 ? Imm32(downcount) : Imm8(downcount)); SUB(32, M(&mips_->downcount), downcount > 127 ? Imm32(downcount) : Imm8(downcount));
} }
void Jit::RestoreRoundingMode(bool force, XEmitter *emitter) void Jit::RestoreRoundingMode(bool force, XEmitter *emitter)
@ -228,10 +228,10 @@ void Jit::RestoreRoundingMode(bool force, XEmitter *emitter)
{ {
if (emitter == NULL) if (emitter == NULL)
emitter = this; emitter = this;
emitter->STMXCSR(M(&currentMIPS->temp)); emitter->STMXCSR(M(&mips_->temp));
// Clear the rounding mode and flush-to-zero bits back to 0. // Clear the rounding mode and flush-to-zero bits back to 0.
emitter->AND(32, M(&currentMIPS->temp), Imm32(~(7 << 13))); emitter->AND(32, M(&mips_->temp), Imm32(~(7 << 13)));
emitter->LDMXCSR(M(&currentMIPS->temp)); emitter->LDMXCSR(M(&mips_->temp));
} }
} }
@ -252,7 +252,7 @@ void Jit::ApplyRoundingMode(bool force, XEmitter *emitter)
if (!g_Config.bForceFlushToZero) if (!g_Config.bForceFlushToZero)
skip = emitter->J_CC(CC_Z); skip = emitter->J_CC(CC_Z);
emitter->STMXCSR(M(&currentMIPS->temp)); emitter->STMXCSR(M(&mips_->temp));
// The MIPS bits don't correspond exactly, so we have to adjust. // The MIPS bits don't correspond exactly, so we have to adjust.
// 0 -> 0 (skip2), 1 -> 3, 2 -> 2 (skip2), 3 -> 1 // 0 -> 0 (skip2), 1 -> 3, 2 -> 2 (skip2), 3 -> 1
@ -262,18 +262,18 @@ void Jit::ApplyRoundingMode(bool force, XEmitter *emitter)
emitter->SetJumpTarget(skip2); emitter->SetJumpTarget(skip2);
emitter->SHL(32, R(EAX), Imm8(13)); emitter->SHL(32, R(EAX), Imm8(13));
emitter->OR(32, M(&currentMIPS->temp), R(EAX)); emitter->OR(32, M(&mips_->temp), R(EAX));
if (g_Config.bForceFlushToZero) { if (g_Config.bForceFlushToZero) {
emitter->OR(32, M(&currentMIPS->temp), Imm32(1 << 15)); emitter->OR(32, M(&mips_->temp), Imm32(1 << 15));
} else { } else {
emitter->TEST(32, M(&mips_->fcr31), Imm32(1 << 24)); emitter->TEST(32, M(&mips_->fcr31), Imm32(1 << 24));
FixupBranch skip3 = emitter->J_CC(CC_Z); FixupBranch skip3 = emitter->J_CC(CC_Z);
emitter->OR(32, M(&currentMIPS->temp), Imm32(1 << 15)); emitter->OR(32, M(&mips_->temp), Imm32(1 << 15));
emitter->SetJumpTarget(skip3); emitter->SetJumpTarget(skip3);
} }
emitter->LDMXCSR(M(&currentMIPS->temp)); emitter->LDMXCSR(M(&mips_->temp));
if (!g_Config.bForceFlushToZero) if (!g_Config.bForceFlushToZero)
emitter->SetJumpTarget(skip); emitter->SetJumpTarget(skip);
@ -543,7 +543,7 @@ bool Jit::ReplaceJalTo(u32 dest) {
MOV(32, M(&mips_->pc), Imm32(js.compilerPC)); MOV(32, M(&mips_->pc), Imm32(js.compilerPC));
RestoreRoundingMode(); RestoreRoundingMode();
ABI_CallFunction(entry->replaceFunc); ABI_CallFunction(entry->replaceFunc);
SUB(32, M(&currentMIPS->downcount), R(EAX)); SUB(32, M(&mips_->downcount), R(EAX));
ApplyRoundingMode(); ApplyRoundingMode();
} }
@ -582,7 +582,7 @@ void Jit::Comp_ReplacementFunc(MIPSOpcode op)
MIPSCompileOp(Memory::Read_Instruction(js.compilerPC, true)); MIPSCompileOp(Memory::Read_Instruction(js.compilerPC, true));
} else { } else {
FlushAll(); FlushAll();
MOV(32, R(ECX), M(&currentMIPS->r[MIPS_REG_RA])); MOV(32, R(ECX), M(&mips_->r[MIPS_REG_RA]));
js.downcountAmount += cycles; js.downcountAmount += cycles;
WriteExitDestInReg(ECX); WriteExitDestInReg(ECX);
js.compiling = false; js.compiling = false;
@ -601,10 +601,10 @@ void Jit::Comp_ReplacementFunc(MIPSOpcode op)
ApplyRoundingMode(); ApplyRoundingMode();
MIPSCompileOp(Memory::Read_Instruction(js.compilerPC, true)); MIPSCompileOp(Memory::Read_Instruction(js.compilerPC, true));
} else { } else {
MOV(32, R(ECX), M(&currentMIPS->r[MIPS_REG_RA])); MOV(32, R(ECX), M(&mips_->r[MIPS_REG_RA]));
SUB(32, M(&currentMIPS->downcount), R(EAX)); SUB(32, M(&mips_->downcount), R(EAX));
ApplyRoundingMode(); ApplyRoundingMode();
SUB(32, M(&currentMIPS->downcount), Imm8(0)); SUB(32, M(&mips_->downcount), Imm8(0));
WriteExitDestInReg(ECX); WriteExitDestInReg(ECX);
js.compiling = false; js.compiling = false;
} }
@ -707,7 +707,7 @@ void Jit::WriteExitDestInReg(X64Reg reg)
FixupBranch tooHigh = J_CC(CC_AE); FixupBranch tooHigh = J_CC(CC_AE);
// Need to set neg flag again if necessary. // Need to set neg flag again if necessary.
SUB(32, M(&currentMIPS->downcount), Imm32(0)); SUB(32, M(&mips_->downcount), Imm32(0));
JMP(asm_.dispatcher, true); JMP(asm_.dispatcher, true);
SetJumpTarget(tooLow); SetJumpTarget(tooLow);
@ -721,11 +721,11 @@ void Jit::WriteExitDestInReg(X64Reg reg)
if (g_Config.bIgnoreBadMemAccess) if (g_Config.bIgnoreBadMemAccess)
CallProtectedFunction(Core_UpdateState, Imm32(CORE_ERROR)); CallProtectedFunction(Core_UpdateState, Imm32(CORE_ERROR));
SUB(32, M(&currentMIPS->downcount), Imm32(0)); SUB(32, M(&mips_->downcount), Imm32(0));
JMP(asm_.dispatcherCheckCoreState, true); JMP(asm_.dispatcherCheckCoreState, true);
SetJumpTarget(skip); SetJumpTarget(skip);
SUB(32, M(&currentMIPS->downcount), Imm32(0)); SUB(32, M(&mips_->downcount), Imm32(0));
J_CC(CC_NE, asm_.dispatcher, true); J_CC(CC_NE, asm_.dispatcher, true);
} }
else else