From 0a8f85a9198f768fb5ada08a485bce9893ea1664 Mon Sep 17 00:00:00 2001 From: Henrik Rydgard Date: Wed, 31 Jul 2013 17:26:14 +0200 Subject: [PATCH] Some JIT cleanup, implement VI2F on ARM. also disabled untested impl of viim for x86. --- Core/MIPS/ARM/ArmCompVFPU.cpp | 58 ++++++++++++++++++++++++++++++----- Core/MIPS/ARM/ArmJit.cpp | 15 ++------- Core/MIPS/ARM/ArmJit.h | 3 +- Core/MIPS/x86/CompVFPU.cpp | 18 ++++++++--- Core/MIPS/x86/Jit.h | 3 +- 5 files changed, 71 insertions(+), 26 deletions(-) diff --git a/Core/MIPS/ARM/ArmCompVFPU.cpp b/Core/MIPS/ARM/ArmCompVFPU.cpp index e935020e99..0807317279 100644 --- a/Core/MIPS/ARM/ArmCompVFPU.cpp +++ b/Core/MIPS/ARM/ArmCompVFPU.cpp @@ -793,7 +793,55 @@ namespace MIPSComp fpr.ReleaseSpillLocksAndDiscardTemps(); } - + + void Jit::Comp_Vi2f(u32 op) { + CONDITIONAL_DISABLE; + + if (js.HasUnknownPrefix()) + DISABLE; + + VectorSize sz = GetVecSize(op); + int n = GetNumVectorElements(sz); + + int imm = (op >> 16) & 0x1f; + const float mult = 1.0f / (float)(1 << imm); + + u8 sregs[4], dregs[4]; + GetVectorRegsPrefixS(sregs, sz, _VS); + GetVectorRegsPrefixD(dregs, sz, _VD); + + MIPSReg tempregs[4]; + for (int i = 0; i < n; ++i) { + if (!IsOverlapSafe(dregs[i], i, n, sregs)) { + tempregs[i] = fpr.GetTempV(); + } else { + tempregs[i] = dregs[i]; + } + } + + if (mult != 1.0f) + MOVI2F(S0, mult, R0); + + for (int i = 0; i < n; i++) { + fpr.MapDirtyInV(tempregs[i], sregs[i]); + VCVT(fpr.V(tempregs[i]), fpr.V(sregs[i]), TO_FLOAT | IS_SIGNED); + if (mult != 1.0f) + VMUL(fpr.V(tempregs[i]), fpr.V(tempregs[i]), S0); + } + + for (int i = 0; i < n; ++i) { + if (dregs[i] != tempregs[i]) { + fpr.MapDirtyInV(dregs[i], tempregs[i]); + VMOV(fpr.V(dregs[i]), fpr.V(tempregs[i])); + } + } + + ApplyPrefixD(dregs, sz); + fpr.ReleaseSpillLocksAndDiscardTemps(); + } + + + void Jit::Comp_Mftv(u32 op) { CONDITIONAL_DISABLE; @@ -920,8 +968,6 @@ namespace MIPSComp void Jit::Comp_VScl(u32 op) { CONDITIONAL_DISABLE; - WARN_LOG(CPU, "HERE WE GO 0"); - if (js.HasUnknownPrefix()) { DISABLE; } @@ -941,7 +987,7 @@ namespace MIPSComp // and that there's no overlap. MIPSReg tempregs[4]; for (int i = 0; i < n; ++i) { - if (dregs[i] == treg || !IsOverlapSafe(dregs[i], i, n, sregs)) { + if (!IsOverlapSafe(dregs[i], i, n, sregs)) { // Need to use temp regs tempregs[i] = fpr.GetTempV(); } else { @@ -1098,10 +1144,6 @@ namespace MIPSComp DISABLE; } - void Jit::Comp_Vi2f(u32 op) { - DISABLE; - } - void Jit::Comp_Vcmp(u32 op) { DISABLE; } diff --git a/Core/MIPS/ARM/ArmJit.cpp b/Core/MIPS/ARM/ArmJit.cpp index 727a0c223a..32dc5375d9 100644 --- a/Core/MIPS/ARM/ArmJit.cpp +++ b/Core/MIPS/ARM/ArmJit.cpp @@ -92,28 +92,19 @@ void Jit::FlushAll() void Jit::FlushPrefixV() { - if ((js.prefixSFlag & ArmJitState::PREFIX_DIRTY) != 0) - { - //if (js.prefixS & 0xF0000000) - // ERROR_LOG(CPU, "Flushing BAD S-flag prefix: %08x", js.prefixS); + if ((js.prefixSFlag & ArmJitState::PREFIX_DIRTY) != 0) { MOVI2R(R0, js.prefixS); STR(R0, CTXREG, offsetof(MIPSState, vfpuCtrl[VFPU_CTRL_SPREFIX])); js.prefixSFlag = (ArmJitState::PrefixState) (js.prefixSFlag & ~ArmJitState::PREFIX_DIRTY); } - if ((js.prefixTFlag & ArmJitState::PREFIX_DIRTY) != 0) - { - //if (js.prefixT & 0xF0000000) - // ERROR_LOG(CPU, "Flushing BAD T-flag prefix: %08x", js.prefixS); + if ((js.prefixTFlag & ArmJitState::PREFIX_DIRTY) != 0) { MOVI2R(R0, js.prefixT); STR(R0, CTXREG, offsetof(MIPSState, vfpuCtrl[VFPU_CTRL_TPREFIX])); js.prefixTFlag = (ArmJitState::PrefixState) (js.prefixTFlag & ~ArmJitState::PREFIX_DIRTY); } - if ((js.prefixDFlag & ArmJitState::PREFIX_DIRTY) != 0) - { - //if (js.prefixD & 0xF0000000) - // ERROR_LOG(CPU, "Flushing BAD D-flag prefix: %08x", js.prefixS); + if ((js.prefixDFlag & ArmJitState::PREFIX_DIRTY) != 0) { MOVI2R(R0, js.prefixD); STR(R0, CTXREG, offsetof(MIPSState, vfpuCtrl[VFPU_CTRL_DPREFIX])); js.prefixDFlag = (ArmJitState::PrefixState) (js.prefixDFlag & ~ArmJitState::PREFIX_DIRTY); diff --git a/Core/MIPS/ARM/ArmJit.h b/Core/MIPS/ARM/ArmJit.h index 45bde5d629..e12e4a6e58 100644 --- a/Core/MIPS/ARM/ArmJit.h +++ b/Core/MIPS/ARM/ArmJit.h @@ -70,9 +70,10 @@ struct ArmJitState PrefixState prefixTFlag; PrefixState prefixDFlag; void PrefixStart() { - PrefixUnknown(); if (startDefaultPrefix) { EatPrefix(); + } else { + PrefixUnknown(); } } void PrefixUnknown() { diff --git a/Core/MIPS/x86/CompVFPU.cpp b/Core/MIPS/x86/CompVFPU.cpp index b145fc7fe3..b7580f63d4 100644 --- a/Core/MIPS/x86/CompVFPU.cpp +++ b/Core/MIPS/x86/CompVFPU.cpp @@ -601,7 +601,7 @@ void Jit::Comp_VecDo3(u32 op) { // There are no immediates for floating point, so we need to load these // from RAM. Might as well have a table ready. -static const float mulTable[32] = { +extern const float mulTableVi2f[32] = { 1.0f/(1UL<<0),1.0f/(1UL<<1),1.0f/(1UL<<2),1.0f/(1UL<<3), 1.0f/(1UL<<4),1.0f/(1UL<<5),1.0f/(1UL<<6),1.0f/(1UL<<7), 1.0f/(1UL<<8),1.0f/(1UL<<9),1.0f/(1UL<<10),1.0f/(1UL<<11), @@ -622,7 +622,7 @@ void Jit::Comp_Vi2f(u32 op) { int n = GetNumVectorElements(sz); int imm = (op >> 16) & 0x1f; - const float *mult = &mulTable[imm]; + const float *mult = &mulTableVi2f[imm]; u8 sregs[4], dregs[4]; GetVectorRegsPrefixS(sregs, sz, _VS); @@ -954,8 +954,6 @@ void Jit::Comp_Vmmov(u32 op) { void Jit::Comp_VScl(u32 op) { CONDITIONAL_DISABLE; - ERROR_LOG(CPU, "vscl @ %08x", js.compilerPC); - if (js.HasUnknownPrefix()) DISABLE; @@ -1205,6 +1203,18 @@ void Jit::Comp_Vcmov(u32 op) { void Jit::Comp_Viim(u32 op) { DISABLE; + CONDITIONAL_DISABLE; + + u8 dreg; + GetVectorRegs(&dreg, V_Single, _VT); + + s32 imm = (s32)(s16)(u16)(op & 0xFFFF); + MOV(32, R(EAX), Imm32(imm)); + fpr.MapRegV(dreg, MAP_DIRTY | MAP_NOINIT); + MOVD_xmm(fpr.VX(dreg), R(EAX)); + + ApplyPrefixD(&dreg, V_Single); + fpr.ReleaseSpillLocks(); } void Jit::Comp_Vfim(u32 op) { diff --git a/Core/MIPS/x86/Jit.h b/Core/MIPS/x86/Jit.h index 588ec4b560..e68576c837 100644 --- a/Core/MIPS/x86/Jit.h +++ b/Core/MIPS/x86/Jit.h @@ -84,9 +84,10 @@ struct JitState PrefixState prefixDFlag; void PrefixStart() { - PrefixUnknown(); if (startDefaultPrefix) { EatPrefix(); + } else { + PrefixUnknown(); } } void PrefixUnknown() {