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Initial FPU regcache
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bf7e5a4115
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021736c533
3 changed files with 312 additions and 7 deletions
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@ -30,7 +30,7 @@ void ArmRegCache::Init(ARMXEmitter *emitter) {
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}
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void ArmRegCache::Start(MIPSAnalyst::AnalysisResults &stats) {
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for (int i = 0; i < 16; i++) {
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for (int i = 0; i < NUM_ARMREG; i++) {
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ar[i].mipsReg = -1;
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ar[i].isDirty = false;
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}
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@ -18,3 +18,240 @@
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#include "Common/ArmEmitter.h"
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#include "Core/MIPS/ARM/ArmRegCacheFPU.h"
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using namespace ArmGen;
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#define CTXREG (R10)
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ArmRegCacheFPU::ArmRegCacheFPU(MIPSState *mips) : mips_(mips) {
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}
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void ArmRegCacheFPU::Init(ARMXEmitter *emitter) {
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emit = emitter;
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}
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void ArmRegCacheFPU::Start(MIPSAnalyst::AnalysisResults &stats) {
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for (int i = 0; i < NUM_ARMFPUREG; i++) {
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ar[i].mipsReg = -1;
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ar[i].isDirty = false;
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}
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for (int i = 0; i < NUM_MIPSFPUREG; i++) {
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mr[i].loc = ML_MEM;
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mr[i].reg = INVALID_REG;
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mr[i].imm = -1;
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mr[i].spillLock = false;
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}
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}
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static const ARMReg *GetMIPSAllocationOrder(int &count) {
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// We conservatively reserve both S0 and S1 as scratch for now.
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// Will probably really only need one, if that.
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static const ARMReg allocationOrder[] = {
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S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
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};
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count = sizeof(allocationOrder) / sizeof(const int);
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return allocationOrder;
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}
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ARMReg ArmRegCacheFPU::MapReg(MIPSReg mipsReg, int mapFlags) {
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// Let's see if it's already mapped. If so we just need to update the dirty flag.
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// We don't need to check for ML_NOINIT because we assume that anyone who maps
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// with that flag immediately writes a "known" value to the register.
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if (mr[mipsReg].loc == ML_ARMREG) {
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if (ar[mr[mipsReg].reg].mipsReg != mipsReg) {
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ERROR_LOG(HLE, "Register mapping out of sync! %i", mipsReg);
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}
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if (mapFlags & MAP_DIRTY) {
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ar[mr[mipsReg].reg].isDirty = true;
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}
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return mr[mipsReg].reg;
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}
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// Okay, not mapped, so we need to allocate an ARM register.
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int allocCount;
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const ARMReg *allocOrder = GetMIPSAllocationOrder(allocCount);
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allocate:
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for (int i = 0; i < allocCount; i++) {
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int reg = allocOrder[i] - S0;
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if (ar[reg].mipsReg == -1) {
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// That means it's free. Grab it, and load the value into it (if requested).
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ar[reg].isDirty = (mapFlags & MAP_DIRTY) ? true : false;
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if (!(mapFlags & MAP_NOINIT)) {
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if (mr[mipsReg].loc == ML_MEM) {
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emit->VLDR((ARMReg)(reg + S0), CTXREG, GetMipsRegOffset(mipsReg));
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}
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}
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ar[reg].mipsReg = mipsReg;
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mr[mipsReg].loc = ML_ARMREG;
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mr[mipsReg].reg = (ARMReg)reg;
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return (ARMReg)reg;
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}
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}
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// Still nothing. Let's spill a reg and goto 10.
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// TODO: Use age or something to choose which register to spill?
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// TODO: Spill dirty regs first? or opposite?
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int bestToSpill = -1;
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for (int i = 0; i < allocCount; i++) {
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int reg = allocOrder[i];
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if (ar[reg].mipsReg != -1 && mr[ar[reg].mipsReg].spillLock)
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continue;
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bestToSpill = reg;
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break;
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}
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if (bestToSpill != -1) {
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// ERROR_LOG(JIT, "Out of registers at PC %08x - spills register %i.", mips_->pc, bestToSpill);
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FlushArmReg((ARMReg)bestToSpill);
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goto allocate;
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}
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// Uh oh, we have all them spilllocked....
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ERROR_LOG(JIT, "Out of spillable registers at PC %08x!!!", mips_->pc);
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return INVALID_REG;
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}
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void ArmRegCacheFPU::MapInIn(MIPSReg rd, MIPSReg rs) {
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SpillLock(rd, rs);
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MapReg(rd);
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MapReg(rs);
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ReleaseSpillLocks();
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}
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void ArmRegCacheFPU::MapDirtyIn(MIPSReg rd, MIPSReg rs, bool avoidLoad) {
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SpillLock(rd, rs);
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bool overlap = avoidLoad && rd == rs;
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MapReg(rd, MAP_DIRTY | (overlap ? 0 : MAP_NOINIT));
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MapReg(rs);
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ReleaseSpillLocks();
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}
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void ArmRegCacheFPU::MapDirtyInIn(MIPSReg rd, MIPSReg rs, MIPSReg rt, bool avoidLoad) {
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SpillLock(rd, rs, rt);
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bool overlap = avoidLoad && (rd == rs || rd == rt);
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MapReg(rd, MAP_DIRTY | (overlap ? 0 : MAP_NOINIT));
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MapReg(rt);
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MapReg(rs);
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ReleaseSpillLocks();
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}
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void ArmRegCacheFPU::FlushArmReg(ARMReg r) {
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if (ar[r - S0].mipsReg == -1) {
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// Nothing to do, reg not mapped.
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return;
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}
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if (ar[r - S0].mipsReg != -1) {
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if (ar[r - S0].isDirty && mr[ar[r - S0].mipsReg].loc == ML_ARMREG)
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emit->VSTR(CTXREG, r, GetMipsRegOffset(ar[r - S0].mipsReg));
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// IMMs won't be in an ARM reg.
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mr[ar[r - S0].mipsReg].loc = ML_MEM;
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mr[ar[r - S0].mipsReg].reg = INVALID_REG;
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mr[ar[r - S0].mipsReg].imm = 0;
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} else {
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ERROR_LOG(HLE, "Dirty but no mipsreg?");
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}
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ar[r].isDirty = false;
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ar[r].mipsReg = -1;
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}
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void ArmRegCacheFPU::FlushMipsReg(MIPSReg r) {
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switch (mr[r].loc) {
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case ML_IMM:
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// IMM is always "dirty".
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emit->MOVI2R(R0, mr[r].imm);
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emit->STR(CTXREG, R0, GetMipsRegOffset(r));
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break;
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case ML_ARMREG:
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if (mr[r].reg == INVALID_REG) {
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ERROR_LOG(HLE, "FlushMipsReg: MipsReg had bad ArmReg");
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}
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if (ar[mr[r].reg].isDirty) {
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emit->STR(CTXREG, mr[r].reg, GetMipsRegOffset(r));
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ar[mr[r].reg].isDirty = false;
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}
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ar[mr[r].reg].mipsReg = -1;
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break;
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case ML_MEM:
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// Already there, nothing to do.
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break;
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default:
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//BAD
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break;
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}
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mr[r].loc = ML_MEM;
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mr[r].reg = INVALID_REG;
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mr[r].imm = 0;
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}
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void ArmRegCacheFPU::FlushAll() {
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for (int i = 0; i < NUM_MIPSFPUREG; i++) {
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FlushMipsReg(i);
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}
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// Sanity check
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for (int i = 0; i < NUM_ARMFPUREG; i++) {
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if (ar[i].mipsReg != -1) {
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ERROR_LOG(JIT, "Flush fail: ar[%i].mipsReg=%i", i, ar[i].mipsReg);
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}
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}
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}
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void ArmRegCacheFPU::SetImm(MIPSReg r, u32 immVal) {
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// Zap existing value if cached in a reg
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if (mr[r].loc == ML_ARMREG) {
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ar[mr[r].reg].mipsReg = -1;
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ar[mr[r].reg].isDirty = false;
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}
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mr[r].loc = ML_IMM;
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mr[r].imm = immVal;
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mr[r].reg = INVALID_REG;
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}
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bool ArmRegCacheFPU::IsImm(MIPSReg r) const {
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return mr[r].loc == ML_IMM;
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}
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u32 ArmRegCacheFPU::GetImm(MIPSReg r) const {
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if (mr[r].loc != ML_IMM) {
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ERROR_LOG(JIT, "Trying to get imm from non-imm register %i", r);
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}
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return mr[r].imm;
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}
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int ArmRegCacheFPU::GetMipsRegOffset(MIPSReg r) {
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// These are offsets within the MIPSState structure. First there are the GPRS, then FPRS, then the "VFPURs".
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if (r < 32)
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return (r + 32) * 4;
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else if (r < 32 + 128)
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return (r + 64) * 4;
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ERROR_LOG(JIT, "bad mips register %i", r);
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return 0; // or what?
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}
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void ArmRegCacheFPU::SpillLock(MIPSReg r1, MIPSReg r2, MIPSReg r3, MIPSReg r4) {
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mr[r1].spillLock = true;
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if (r2 != -1) mr[r2].spillLock = true;
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if (r3 != -1) mr[r3].spillLock = true;
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if (r4 != -1) mr[r4].spillLock = true;
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}
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// This is actually pretty slow with all the 160 regs...
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void ArmRegCacheFPU::ReleaseSpillLocks() {
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for (int i = 0; i < NUM_MIPSFPUREG; i++) {
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mr[i].spillLock = false;
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}
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}
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ARMReg ArmRegCacheFPU::R(int mipsReg) {
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if (mr[mipsReg].loc == ML_ARMREG) {
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return mr[mipsReg].reg;
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} else {
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ERROR_LOG(JIT, "Reg %i not in arm reg. compilerPC = %08x", mipsReg, compilerPC_);
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return INVALID_REG; // BAAAD
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}
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}
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@ -17,13 +17,81 @@
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#pragma once
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#include "Common/ArmEmitter.h"
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#pragma once
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#include "../MIPS.h"
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#include "../MIPSAnalyst.h"
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#include "ArmEmitter.h"
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#include "ArmRegCache.h"
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using namespace ArmGen;
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enum {
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TOTAL_MAPPABLE_MIPSFPUREGS = 32 + 128,
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};
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struct FPURegARM {
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int mipsReg; // if -1, no mipsreg attached.
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bool isDirty; // Should the register be written back?
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};
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struct FPURegMIPS {
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// Where is this MIPS register?
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RegMIPSLoc loc;
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// Data (only one of these is used, depending on loc. Could make a union).
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u32 imm;
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ARMReg reg;
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bool spillLock; // if true, this register cannot be spilled.
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// If loc == ML_MEM, it's back in its location in the CPU context struct.
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};
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// The PSP has 160 FP registers: 32 FPRs + 128 VFPU registers.
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class FPURegCache {
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class ArmRegCacheFPU
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{
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public:
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ArmRegCacheFPU(MIPSState *mips);
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~ArmRegCacheFPU() {}
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};
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void Init(ARMXEmitter *emitter);
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void Start(MIPSAnalyst::AnalysisResults &stats);
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// Protect the arm register containing a MIPS register from spilling, to ensure that
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// it's being kept allocated.
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void SpillLock(MIPSReg reg, MIPSReg reg2 = -1, MIPSReg reg3 = -1, MIPSReg reg4 = -1);
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void ReleaseSpillLocks();
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void SetImm(MIPSReg reg, u32 immVal);
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bool IsImm(MIPSReg reg) const;
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u32 GetImm(MIPSReg reg) const;
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// Returns an ARM register containing the requested MIPS register.
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ARMReg MapReg(MIPSReg reg, int mapFlags = 0);
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void MapInIn(MIPSReg rd, MIPSReg rs);
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void MapDirtyIn(MIPSReg rd, MIPSReg rs, bool avoidLoad = true);
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void MapDirtyInIn(MIPSReg rd, MIPSReg rs, MIPSReg rt, bool avoidLoad = true);
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void FlushArmReg(ARMReg r);
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void FlushMipsReg(MIPSReg r);
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void FlushAll();
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ARMReg R(int preg); // Returns a cached register
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void SetEmitter(ARMXEmitter *emitter) { emit = emitter; }
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// For better log output only.
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void SetCompilerPC(u32 compilerPC) { compilerPC_ = compilerPC; }
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private:
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int GetMipsRegOffset(MIPSReg r);
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MIPSState *mips_;
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ARMXEmitter *emit;
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u32 compilerPC_;
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enum {
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NUM_ARMFPUREG = 16, // TODO: Support 32, which you have with NEON
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NUM_MIPSFPUREG = TOTAL_MAPPABLE_MIPSFPUREGS,
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};
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RegARM ar[NUM_ARMFPUREG];
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RegMIPS mr[NUM_MIPSFPUREG];
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};
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