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118 lines
4.3 KiB
Text
118 lines
4.3 KiB
Text
NTSC NES PPU VBL/NMI Timing Tests
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---------------------------------
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These ROMs test the timing of the VBL flag and NMI to an accuracy of a
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single PPU clock, and also check special cases. They have been tested on
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an actual NES and all give a passing result. Sometimes the NES starts up
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with a different PPU timing that causes some of the tests to fail; these
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tests don't check that timing arrangement.
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Each ROM runs several tests and reports the result on screen and by
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beeping a number of times. See below for the meaning of failure codes
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for each test. It's best to run the tests in order, because later ROMs
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depend on things tested by earlier ROMs and will give erroneous results
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if any earlier ones failed.
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Source code for each test is included, and most tests are clearly
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divided into sections. Support code is also included, but it runs on a
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custom devcart and assembler so it will require some effort to assemble.
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Contact me if you'd like assistance porting them to your setup.
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1.frame_basics
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--------------
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Tests basic VBL flag operation and general timing of PPU frames.
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2) VBL flag isn't being set
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3) VBL flag should be cleared after being read
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4) PPU frame with BG enabled is too short
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5) PPU frame with BG enabled is too long
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6) PPU frame with BG disabled is too short
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7) PPU frame with BG disabled is too long
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2.vbl_timing
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------------
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Tests timing of VBL being set, and special case where reading VBL flag
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as it would be set causes it to not be set for that frame.
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2) Flag should read as clear 3 PPU clocks before VBL
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3) Flag should read as set 0 PPU clocks after VBL
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4) Flag should read as clear 2 PPU clocks before VBL
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5) Flag should read as set 1 PPU clock after VBL
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6) Flag should read as clear 1 PPU clock before VBL
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7) Flag should read as set 2 PPU clocks after VBL
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8) Reading 1 PPU clock before VBL should suppress setting
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3.even_odd_frames
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-----------------
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Test clock skipped when BG is enabled on odd PPU frames. Tests
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enable/disable BG during 5 consecutive frames, then see how many clocks
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were skipped. Patterns are shown as XXXXX, where each X can either be B
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(BG enabled) or - (BG disabled).
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2) Pattern ----- should not skip any clocks
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3) Pattern BB--- should skip 1 clock
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4) Pattern B--B- (one even, one odd) should skip 1 clock
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5) Pattern -B--B (one odd, one even) should skip 1 clock
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6) Pattern BB-BB (two pairs) should skip 2 clocks
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4.vbl_clear_timing
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------------------
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Tests timing of VBL flag clearing.
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2) Cleared 3 or more PPU clocks too early
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3) Cleared 2 PPU clocks too early
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4) Cleared 1 PPU clock too early
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5) Cleared 3 or more PPU clocks too late
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6) Cleared 2 PPU clocks too late
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7) Cleared 1 PPU clock too late
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5.nmi_suppression
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-----------------
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Tests timing of NMI suppression when reading VBL flag just as it's set,
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and that this doesn't occur when reading one clock before or after.
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2) Reading flag 3 PPU clocks before set shouldn't suppress NMI
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3) Reading flag when it's set should suppress NMI
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4) Reading flag 3 PPU clocks after set shouldn't suppress NMI
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5) Reading flag 2 PPU clocks before set shouldn't suppress NMI
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6) Reading flag 1 PPU clock after set should suppress NMI
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7) Reading flag 4 PPU clocks after set shouldn't suppress NMI
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8) Reading flag 4 PPU clocks before set shouldn't suppress NMI
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9) Reading flag 1 PPU clock before set should suppress NMI
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10)Reading flag 2 PPU clocks after set shouldn't suppress NMI
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6.nmi_disable
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-------------
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Tests NMI occurrence when disabling NMI just as VBL flag is set, and
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just after.
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2) NMI shouldn't occur when disabled 0 PPU clocks after VBL
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3) NMI should occur when disabled 3 PPU clocks after VBL
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4) NMI shouldn't occur when disabled 1 PPU clock after VBL
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5) NMI should occur when disabled 4 PPU clocks after VBL
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6) NMI shouldn't occur when disabled 1 PPU clock before VBL
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7) NMI should occur when disabled 2 PPU clocks after VBL
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7.nmi_timing
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------------
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Tests timing of NMI and immediate occurrence when enabled with VBL flag
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already set.
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2) NMI occurred 3 or more PPU clocks too early
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3) NMI occurred 2 PPU clocks too early
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4) NMI occurred 1 PPU clock too early
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5) NMI occurred 3 or more PPU clocks too late
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6) NMI occurred 2 PPU clocks too late
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7) NMI occurred 1 PPU clock too late
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8) NMI should occur if enabled when VBL already set
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9) NMI enabled when VBL already set should delay 1 instruction
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10)NMI should be possible multiple times in VBL
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--
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Shay Green <hotpop.com@blargg> (swap to e-mail)
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