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124 lines
2.2 KiB
Text
124 lines
2.2 KiB
Text
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; Same as sync_ppu_20 plus next frame is odd (clock subtracted) or even
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; (no clock subtracted).
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sync_ppu_odd_20:
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lda #$80
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bne sync_ppu_frame_
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sync_ppu_even_20:
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lda #$00
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sync_ppu_frame_:
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pha
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; Synchronize with PPU
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jsr sync_ppu_20 ; synchronize with PPU
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; Run for two frames with BG enabled. One of the two frames will
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; be one PPU clock shorter. Note whether the first frame was the
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; shorter one.
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lda #$08 ; 6 enable bg
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sta $2001
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ldy #41 ; 29785 delay
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lda #144
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jsr delay_ya2
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nop ; 2 delay
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pla ; 4
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eor $2002 ; 4 find whether frame was odd or even
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pha ; 3
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; run another enabled frame so that clock will
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; have been subtracted on one of the two frames
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ldy #43 ; 29730+ delay
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lda #137
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jsr delay_ya1
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lda #$00 ; 6 disable bg
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sta $2001
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; If the first frame was shorter, wait three frames to switch
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; the even/odd synchronization without changing the CPU clock's
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; synchronization with the PPU clock.
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pla ; 4
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pha ; 3
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bpl + ; 3
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; -1
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ldy #75 ; 89343 delay
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lda #237
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jsr delay_ya1
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: pla ; 4
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rts ; 6
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.code
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; After return, 30 clocks until VBL flag will read
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; as set, then 29781, 29780, 29781, 29781, 29780, etc.
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; Turns off PPU rendering, NMI, IRQ, and DMC.
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sync_ppu_align2_30:
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pha
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txa
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pha
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tya
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pha
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lda #0 ; disable dmc and irq
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sta $4015
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sei
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jsr wait_vbl
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lda #0 ; disable bg and nmi
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sta $2000
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sta $2001
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bit $2002
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: bit $2002 ; 1
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bpl - ; 2
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ldy #141 ; 29774 delay
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lda #41
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jsr delay_ya6
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: ldy #86 ; 29774 delay
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lda #68
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jsr delay_ya1
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bit $2002 ; 1
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bpl - ; 2
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ldy #28 ; 29726 delay
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lda #211
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jsr delay_ya1
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pla ; 16
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tay
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pla
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tax
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pla
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rts ; 6
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.code
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sync_ppu_align1_30:
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jsr sync_ppu_align2_30
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ldy #86 ; 29775 delay
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lda #68
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jsr delay_ya2
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rts
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.code
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sync_ppu_align1_31:
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jsr sync_ppu_align2_30
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ldy #86 ; 29774 delay
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lda #68
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jsr delay_ya1
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rts
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.code
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sync_ppu_align0_30:
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jsr sync_ppu_align1_30
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ldy #86 ; 29774 delay
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lda #68
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jsr delay_ya1
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rts
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.code
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sync_ppu_20:
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jsr sync_ppu_align2_30
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nop ; 4
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nop
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rts ; 6
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.code
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