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162 lines
2.2 KiB
ArmAsm
162 lines
2.2 KiB
ArmAsm
; Utilities for writing test ROMs
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zp_res test_code,1 ; code of current test
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zp_res test_name,2 ; address of name of current test, or 0 of none
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; Reports that all tests passed
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tests_passed:
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.if !BUILD_MULTI
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jsr print_filename
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print_str "Passed"
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.endif
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lda #0
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jmp exit
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; Reports that the current test failed. Prints code and
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; name last set with set_test, or just "Failed" if none
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; have been set yet.
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test_failed:
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lda test_code
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; Treat 0 as 1, in case it wasn't ever set
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bne :+
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lda #1
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sta test_code
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:
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; If code >= 2, print name
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cmp #2
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blt :+
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lda test_name+1
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beq :+
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jsr print_newline
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sta addr+1
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lda test_name
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sta addr
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jsr print_str_addr
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jsr print_newline
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:
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.if !BUILD_MULTI
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jsr print_filename
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.endif
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; End program
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lda test_code
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jmp exit
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; Sets current test code and optional name. Also resets
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; checksum.
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.macro set_test code,name
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pha
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lda #code
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jsr set_test_
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.local Addr
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lda #<Addr
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sta <test_name
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lda #>Addr
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sta <test_name+1
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seg_data "STRINGS",{Addr: .byte name,0}
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pla
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.endmacro
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set_test_:
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sta test_code
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jmp reset_crc
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; If checksum doesn't match expected, reports failed test.
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; Passing 0 just prints checksum.
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; Preserved: A, X, Y
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.macro check_crc expected
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.if expected
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jsr_with_addr check_crc_,{.dword expected}
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.else
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; print checksum if 0 is passed
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jsr print_newline
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jsr print_crc
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jsr print_newline
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.endif
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.endmacro
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check_crc_:
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pha
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tya
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pha
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; Compare with complemented checksum
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ldy #3
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: lda (addr),y
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sec
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adc checksum,y
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bne @wrong
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dey
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bpl :-
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pla
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tay
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pla
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rts
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@wrong: jsr print_newline
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jsr print_crc
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jsr print_newline
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jmp test_failed
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; Reports value of A via low/high beeps.
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; Preserved: A, X, Y
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beep_bits:
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pha
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; Make reference low beep
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clc
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jsr @beep
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; End marker
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sec
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; Remove high zero bits
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: rol a
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beq @zero
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bcc :-
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; Play remaining bits
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: php
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jsr @beep
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plp
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asl a
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bne :-
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@zero: pla
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rts
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@beep: pha
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; Set LSB of pitch based on carry
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lda #0
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adc #$FF
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sta $4002
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; Set up square
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lda #1
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sta SNDCHN
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sta $4003
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sta $4001
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; Fade volume
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lda #15
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: pha
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eor #$30
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sta $4000
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delay_msec 8
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pla
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clc
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adc #-1
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bne :-
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; Silence
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sta SNDCHN
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delay_msec 120
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pla
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rts
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