mirror of
https://github.com/PCSX2/pcsx2.git
synced 2025-04-02 10:52:54 -04:00
fe6f45e45e
Updated the pcsx2_suite_2008.sln; changed SPU2ghz to SPU2-X. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@502 96395faa-99c1-11dd-bbfe-3dabce05a288
693 lines
20 KiB
C++
693 lines
20 KiB
C++
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2009 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include "PrecompiledHeader.h"
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#include "Common.h"
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#include "Counters.h"
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#include "Memory.h"
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#include "Hw.h"
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#include "DebugTools/Debug.h"
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#include "R3000A.h"
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#include "VUmicro.h"
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#include "COP0.h"
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#include "GS.h"
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#include "IPU/IPU.h"
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#include "Vif.h"
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#include "VifDma.h"
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#include "SPR.h"
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#include "Sif.h"
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#include "Paths.h"
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using namespace R5900; // for R5900 disasm tools
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s32 EEsCycle; // used to sync the IOP to the EE
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u32 EEoCycle;
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//static int inter;
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PCSX2_ALIGNED16(cpuRegisters cpuRegs);
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PCSX2_ALIGNED16(fpuRegisters fpuRegs);
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PCSX2_ALIGNED16(tlbs tlb[48]);
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R5900cpu *Cpu = NULL;
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u32 bExecBIOS = 0; // set if the BIOS has already been executed
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static bool cpuIsInitialized = false;
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static uint eeWaitCycles = 1024;
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bool eeEventTestIsActive = false;
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// A run-once procedure for initializing the emulation state.
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// Can be done anytime after allocating memory, and before calling Cpu->Execute().
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// Multiple calls to this function are automatically ignored.
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/*void cpuInit()
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{
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DevCon::WriteLn( "cpuInit > %s", params cpuIsInitialized ? "Initializing..." : "Skipping (already initialized)" );
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if( cpuIsInitialized ) return;
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cpuIsInitialized = true;
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// non memInit() currently since we don't support soft resets. memory is initialized in full
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// instead during cpuReset() [using memReset()]
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//memInit();
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}*/
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void cpuReset()
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{
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mtgsWaitGS(); // GS better be done processing before we reset the EE, just in case.
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//cpuInit(); // more just-in-caseness!
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//if( !cpuIsInitialized )
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{
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cpuIsInitialized = true;
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}
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memReset();
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psxMemReset();
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vuMicroMemReset();
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memzero_obj(cpuRegs);
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memzero_obj(fpuRegs);
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memzero_obj(tlb);
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cpuRegs.pc = 0xbfc00000; ///set pc reg to stack
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cpuRegs.CP0.n.Config = 0x440;
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cpuRegs.CP0.n.Status.val = 0x70400004; //0x10900000 <-- wrong; // COP0 enabled | BEV = 1 | TS = 1
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cpuRegs.CP0.n.PRid = 0x00002e20; // PRevID = Revision ID, same as R5900
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fpuRegs.fprc[0] = 0x00002e00; // fpu Revision..
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fpuRegs.fprc[31] = 0x01000001; // fpu Status/Control
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g_nextBranchCycle = cpuRegs.cycle + 4;
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EEsCycle = 0;
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EEoCycle = cpuRegs.cycle;
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eeWaitCycles = CHECK_WAITCYCLE_HACK ? 3072 : 768;
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// Cyclerate hacks effectively speed up the rate of event tests, so we can safely boost
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// the WaitCycles value here for x2 and x3 modes:
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if( CHECK_EE_CYCLERATE > 1 )
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eeWaitCycles += 1024;
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hwReset();
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vif0Reset();
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vif1Reset();
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rcntInit();
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psxReset();
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}
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void cpuShutdown()
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{
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//if( !cpuIsInitialized ) return;
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//cpuIsInitialized = false;
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mtgsWaitGS();
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hwShutdown();
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// biosShutdown();
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psxShutdown();
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disR5900FreeSyms();
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}
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void cpuException(u32 code, u32 bd)
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{
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cpuRegs.branch = 0; // Tells the interpreter that an exception occurred during a branch.
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u32 offset;
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cpuRegs.CP0.n.Cause = code & 0xffff;
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if(cpuRegs.CP0.n.Status.b.ERL == 0){ //Error Level 0-1
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if(((code & 0x7C) >= 0x8) && ((code & 0x7C) <= 0xC)) offset = 0x0; //TLB Refill
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else if ((code & 0x7C) == 0x0) offset = 0x200; //Interrupt
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else offset = 0x180; // Everything else
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if (cpuRegs.CP0.n.Status.b.EXL == 0) {
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cpuRegs.CP0.n.Status.b.EXL = 1;
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if (bd) {
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Console::Notice("branch delay!!");
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cpuRegs.CP0.n.EPC = cpuRegs.pc - 4;
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cpuRegs.CP0.n.Cause |= 0x80000000;
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} else {
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cpuRegs.CP0.n.EPC = cpuRegs.pc;
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cpuRegs.CP0.n.Cause &= ~0x80000000;
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}
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} else {
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offset = 0x180; //Overrride the cause
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//Console::Notice("cpuException: Status.EXL = 1 cause %x", params code);
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}
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if (cpuRegs.CP0.n.Status.b.BEV == 0) {
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cpuRegs.pc = 0x80000000 + offset;
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} else {
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cpuRegs.pc = 0xBFC00200 + offset;
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}
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} else { //Error Level 2
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Console::Error("*PCSX2* FIX ME: Level 2 cpuException");
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if((code & 0x38000) <= 0x8000 ) { //Reset / NMI
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cpuRegs.pc = 0xBFC00000;
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Console::Notice("Reset request");
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UpdateCP0Status();
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return;
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} else if((code & 0x38000) == 0x10000) offset = 0x80; //Performance Counter
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else if((code & 0x38000) == 0x18000) offset = 0x100; //Debug
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else Console::Error("Unknown Level 2 Exception!! Cause %x", params code);
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if (cpuRegs.CP0.n.Status.b.EXL == 0) {
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cpuRegs.CP0.n.Status.b.EXL = 1;
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if (bd) {
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Console::Notice("branch delay!!");
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cpuRegs.CP0.n.EPC = cpuRegs.pc - 4;
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cpuRegs.CP0.n.Cause |= 0x80000000;
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} else {
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cpuRegs.CP0.n.EPC = cpuRegs.pc;
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cpuRegs.CP0.n.Cause &= ~0x80000000;
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}
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} else {
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offset = 0x180; //Overrride the cause
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Console::Notice("cpuException: Status.EXL = 1 cause %x", params code);
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}
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if (cpuRegs.CP0.n.Status.b.DEV == 0) {
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cpuRegs.pc = 0x80000000 + offset;
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} else {
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cpuRegs.pc = 0xBFC00200 + offset;
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}
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}
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UpdateCP0Status();
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}
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void cpuTlbMiss(u32 addr, u32 bd, u32 excode) {
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Console::Error("cpuTlbMiss pc:%x, cycl:%x, addr: %x, status=%x, code=%x", params cpuRegs.pc, cpuRegs.cycle, addr, cpuRegs.CP0.n.Status.val, excode);
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if (bd) {
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Console::Notice("branch delay!!");
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}
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assert(0); // temporary
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cpuRegs.CP0.n.BadVAddr = addr;
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cpuRegs.CP0.n.Context &= 0xFF80000F;
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cpuRegs.CP0.n.Context |= (addr >> 9) & 0x007FFFF0;
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cpuRegs.CP0.n.EntryHi = (addr & 0xFFFFE000) | (cpuRegs.CP0.n.EntryHi & 0x1FFF);
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cpuRegs.CP0.n.Cause = excode;
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if (!(cpuRegs.CP0.n.Status.val & 0x2)) { // EXL bit
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cpuRegs.CP0.n.EPC = cpuRegs.pc - 4;
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}
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if ((cpuRegs.CP0.n.Status.val & 0x1) == 0) {
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cpuRegs.pc = 0x80000000;
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} else {
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cpuRegs.pc = 0x80000180;
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}
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cpuRegs.CP0.n.Status.b.EXL = 1;
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UpdateCP0Status();
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// Log=1; varLog|= 0x40000000;
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}
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void cpuTlbMissR(u32 addr, u32 bd) {
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cpuTlbMiss(addr, bd, EXC_CODE_TLBL);
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}
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void cpuTlbMissW(u32 addr, u32 bd) {
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cpuTlbMiss(addr, bd, EXC_CODE_TLBS);
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}
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void JumpCheckSym(u32 addr, u32 pc) {
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#if 0
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// if (addr == 0x80051770) { SysPrintf("Log!: %s\n", PSM(cpuRegs.GPR.n.a0.UL[0])); Log=1; varLog|= 0x40000000; }
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if (addr == 0x8002f150) { SysPrintf("printk: %s\n", PSM(cpuRegs.GPR.n.a0.UL[0])); }
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if (addr == 0x8002aba0) return;
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if (addr == 0x8002f450) return;
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if (addr == 0x800dd520) return;
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// if (addr == 0x80049300) SysPrintf("register_blkdev: %x\n", cpuRegs.GPR.n.a0.UL[0]);
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if (addr == 0x8013cb70) { SysPrintf("change_root: %x\n", cpuRegs.GPR.n.a0.UL[0]); }
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// if (addr == 0x8013d1e8) { SysPrintf("Log!\n"); Log++; if (Log==2) exit(0); varLog|= 0x40000000; }
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// if (addr == 0x00234e88) { SysPrintf("StoreImage\n"); Log=1; /*psMu32(0x234e88) = 0x03e00008; psMu32(0x234e8c) = 0;*/ }
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#endif
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/* if ((pc >= 0x00131D50 &&
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pc < 0x00132454) ||
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(pc >= 0x00786a90 &&
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pc < 0x00786ac8))*/
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/*if (varLog & 0x40000000) {
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char *str;
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char *strf;
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str = disR5900GetSym(addr);
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if (str != NULL) {
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strf = disR5900GetUpperSym(pc);
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if (strf) {
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SysPrintf("Func %8.8x: %s (called by %8.8x: %s)\n", addr, str, pc, strf);
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} else {
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SysPrintf("Func %8.8x: %s (called by %x)\n", addr, str, pc);
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}
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if (!strcmp(str, "printf")) { SysPrintf("%s\n", (char*)PSM(cpuRegs.GPR.n.a0.UL[0])); }
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if (!strcmp(str, "printk")) { SysPrintf("%s\n", (char*)PSM(cpuRegs.GPR.n.a0.UL[0])); }
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}
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}*/
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}
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void JumpCheckSymRet(u32 addr) {
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/*if (varLog & 0x40000000) {
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char *str;
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str = disR5900GetUpperSym(addr);
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if (str != NULL) {
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SysPrintf("Return : %s, v0=%8.8x\n", str, cpuRegs.GPR.n.v0.UL[0]);
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}
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}*/
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}
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__forceinline void _cpuTestMissingINTC() {
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if (cpuRegs.CP0.n.Status.val & 0x400 &&
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psHu32(INTC_STAT) & psHu32(INTC_MASK)) {
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if ((cpuRegs.interrupt & (1 << 30)) == 0) {
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SysPrintf("*PCSX2*: Error, missing INTC Interrupt\n");
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}
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}
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}
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__forceinline void _cpuTestMissingDMAC() {
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if (cpuRegs.CP0.n.Status.val & 0x800 &&
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(psHu16(0xe012) & psHu16(0xe010) ||
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psHu16(0xe010) & 0x8000)) {
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if ((cpuRegs.interrupt & (1 << 31)) == 0) {
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SysPrintf("*PCSX2*: Error, missing DMAC Interrupt\n");
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}
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}
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}
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void cpuTestMissingHwInts() {
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if ((cpuRegs.CP0.n.Status.val & 0x10007) == 0x10001) {
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_cpuTestMissingINTC();
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_cpuTestMissingDMAC();
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// _cpuTestTIMR();
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}
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}
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// sets a branch test to occur some time from an arbitrary starting point.
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__forceinline int cpuSetNextBranch( u32 startCycle, s32 delta )
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{
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// typecast the conditional to signed so that things don't blow up
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// if startCycle is greater than our next branch cycle.
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if( (int)(g_nextBranchCycle - startCycle) > delta )
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{
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g_nextBranchCycle = startCycle + delta;
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return 1;
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}
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return 0;
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}
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// sets a branch to occur some time from the current cycle
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__forceinline int cpuSetNextBranchDelta( s32 delta )
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{
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return cpuSetNextBranch( cpuRegs.cycle, delta );
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}
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// tests the cpu cycle agaisnt the given start and delta values.
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// Returns true if the delta time has passed.
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__forceinline int cpuTestCycle( u32 startCycle, s32 delta )
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{
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// typecast the conditional to signed so that things don't explode
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// if the startCycle is ahead of our current cpu cycle.
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return (int)(cpuRegs.cycle - startCycle) >= delta;
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}
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// tells the EE to run the branch test the next time it gets a chance.
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__forceinline void cpuSetBranch()
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{
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g_nextBranchCycle = cpuRegs.cycle;
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}
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void cpuClearInt( uint i )
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{
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jASSUME( i < 32 );
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cpuRegs.interrupt &= ~(1 << i);
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}
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static __forceinline void TESTINT( u8 n, void (*callback)() )
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{
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if( !(cpuRegs.interrupt & (1 << n)) ) return;
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if( cpuTestCycle( cpuRegs.sCycle[n], cpuRegs.eCycle[n] ) )
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{
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cpuClearInt( n );
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callback();
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}
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else
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cpuSetNextBranch( cpuRegs.sCycle[n], cpuRegs.eCycle[n] );
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}
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static __forceinline void _cpuTestInterrupts()
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{
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/* These are 'pcsx2 interrupts', they handle asynchronous stuff
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that depends on the cycle timings */
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TESTINT(1, vif1Interrupt);
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TESTINT(2, gsInterrupt);
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TESTINT(5, EEsif0Interrupt);
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TESTINT(6, EEsif1Interrupt);
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// Profile-guided Optimization (sorta)
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// The following ints are rarely called. Encasing them in a conditional
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// as follows helps speed up most games.
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if( cpuRegs.interrupt & ( 1 | (3 << 3) | (3<<8) | (3<<10)) )
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{
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TESTINT(0, vif0Interrupt);
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#ifndef IPU_INLINE_IRQS
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TESTINT(3, ipu0Interrupt);
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TESTINT(4, ipu1Interrupt);
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#endif
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TESTINT(8, SPRFROMinterrupt);
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TESTINT(9, SPRTOinterrupt);
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TESTINT(10, vifMFIFOInterrupt);
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TESTINT(11, gifMFIFOInterrupt);
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}
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}
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static __forceinline void _cpuTestTIMR()
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{
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cpuRegs.CP0.n.Count += cpuRegs.cycle-s_iLastCOP0Cycle;
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s_iLastCOP0Cycle = cpuRegs.cycle;
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// fixme: this looks like a hack to make up for the fact that the TIMR
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// doesn't yet have a proper mechanism for setting itself up on a nextBranchCycle.
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// A proper fix would schedule the TIMR to trigger at a specific cycle anytime
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// the Count or Compare registers are modified.
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if ( (cpuRegs.CP0.n.Status.val & 0x8000) &&
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cpuRegs.CP0.n.Count >= cpuRegs.CP0.n.Compare && cpuRegs.CP0.n.Count < cpuRegs.CP0.n.Compare+1000 )
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{
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Console::Status("timr intr: %x, %x", params cpuRegs.CP0.n.Count, cpuRegs.CP0.n.Compare);
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cpuException(0x808000, cpuRegs.branch);
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}
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}
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static __forceinline void _cpuTestPERF()
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{
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// fixme - The interpreter and recompiler both re-calculate these values
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// whenever they are read, so updating them at regular intervals *should be*
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// merely a common courtesy. But when I set them up to be called less
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// frequently some games would crash. I'd like to figure out why someday. [Air]
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if((cpuRegs.PERF.n.pccr & 0x800003E0) == 0x80000020) {
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cpuRegs.PERF.n.pcr0 += cpuRegs.cycle-s_iLastPERFCycle[0];
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s_iLastPERFCycle[0] = cpuRegs.cycle;
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}
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if((cpuRegs.PERF.n.pccr & 0x800F8000) == 0x80008000) {
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cpuRegs.PERF.n.pcr1 += cpuRegs.cycle-s_iLastPERFCycle[1];
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s_iLastPERFCycle[1] = cpuRegs.cycle;
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}
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}
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// Checks the COP0.Status for exception enablings.
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// Exception handling for certain modes is *not* currently supported, this function filters
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// them out. Exceptions while the exception handler is active (EIE), or exceptions of any
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// level other than 0 are ignored here.
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static bool cpuIntsEnabled()
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{
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return cpuRegs.CP0.n.Status.b.EIE && cpuRegs.CP0.n.Status.b.IE &&
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!cpuRegs.CP0.n.Status.b.EXL && (cpuRegs.CP0.n.Status.b.ERL == 0);
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}
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// if cpuRegs.cycle is greater than this cycle, should check cpuBranchTest for updates
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u32 g_nextBranchCycle = 0;
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// Shared portion of the branch test, called from both the Interpreter
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// and the recompiler. (moved here to help alleviate redundant code)
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__forceinline bool _cpuBranchTest_Shared()
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{
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eeEventTestIsActive = true;
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g_nextBranchCycle = cpuRegs.cycle + eeWaitCycles;
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EEsCycle += cpuRegs.cycle - EEoCycle;
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EEoCycle = cpuRegs.cycle;
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if( EEsCycle > 0 )
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iopBranchAction = true;
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// ---- Counters -------------
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bool vsyncEvent = false;
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rcntUpdate_hScanline();
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if( cpuTestCycle( nextsCounter, nextCounter ) )
|
|
{
|
|
vsyncEvent = rcntUpdate();
|
|
_cpuTestPERF();
|
|
}
|
|
|
|
_cpuTestTIMR();
|
|
|
|
// ---- Interrupts -------------
|
|
// Handles all interrupts except 30 and 31, which are handled later.
|
|
|
|
if( cpuRegs.interrupt & ~(3<<30) )
|
|
_cpuTestInterrupts();
|
|
|
|
// ---- IOP -------------
|
|
// * It's important to run a psxBranchTest before calling ExecuteBlock. This
|
|
// is because the IOP does not always perform branch tests before returning
|
|
// (during the prev branch) and also so it can act on the state the EE has
|
|
// given it before executing any code.
|
|
//
|
|
// * The IOP cannot always be run. If we run IOP code every time through the
|
|
// cpuBranchTest, the IOP generally starts to run way ahead of the EE.
|
|
|
|
psxBranchTest();
|
|
|
|
if( iopBranchAction )
|
|
{
|
|
//if( EEsCycle < -450 )
|
|
// Console::WriteLn( " IOP ahead by: %d cycles", params -EEsCycle );
|
|
|
|
// Experimental and Probably Unnecessry Logic -->
|
|
// Check if the EE already has an exception pending, and if so we shouldn't
|
|
// waste too much time updating the IOP. Theory being that the EE and IOP should
|
|
// run closely in sync during raised exception events. But in practice it didn't
|
|
// seem to make much of a difference.
|
|
|
|
// Note: The IOP is very good about chaining blocks together so it tends to
|
|
// run lots of cycles, even with only 32 (4 IOP) cycles specified here. That's
|
|
// probably why it doesn't improve sync much.
|
|
|
|
/*bool eeExceptPending = cpuIntsEnabled() &&
|
|
//( cpuRegs.CP0.n.Status.b.EIE && cpuRegs.CP0.n.Status.b.IE && (cpuRegs.CP0.n.Status.b.ERL == 0) ) &&
|
|
//( (cpuRegs.CP0.n.Status.val & 0x10007) == 0x10001 ) &&
|
|
( (cpuRegs.interrupt & (3<<30)) != 0 );
|
|
|
|
if( eeExceptPending )
|
|
{
|
|
// ExecuteBlock returns a negative value, so subtract it from the cycle count
|
|
// specified to get the total cycles processed! :D
|
|
int cycleCount = std::min( EEsCycle, (s32)(eeWaitCycles>>4) );
|
|
int cyclesRun = cycleCount - psxCpu->ExecuteBlock( cycleCount );
|
|
EEsCycle -= cyclesRun;
|
|
//Console::Notice( "IOP Exception-Pending Execution -- EEsCycle: %d", params EEsCycle );
|
|
}
|
|
else*/
|
|
{
|
|
EEsCycle = psxCpu->ExecuteBlock( EEsCycle );
|
|
}
|
|
|
|
iopBranchAction = false;
|
|
}
|
|
|
|
// ---- VU0 -------------
|
|
|
|
if (VU0.VI[REG_VPU_STAT].UL & 0x1)
|
|
{
|
|
// We're in a BranchTest. All dynarec registers are flushed
|
|
// so there is no need to freeze registers here.
|
|
CpuVU0.ExecuteBlock();
|
|
|
|
// This might be needed to keep the EE and VU0 in sync.
|
|
// A better fix will require hefty changes to the VU recs. -_-
|
|
if(VU0.VI[REG_VPU_STAT].UL & 0x1)
|
|
cpuSetNextBranchDelta( 768 );
|
|
}
|
|
|
|
// Note: We don't update the VU1 here because it runs it's micro-programs in
|
|
// one shot always. That is, when a program is executed the VU1 doesn't even
|
|
// bother to return until the program is completely finished.
|
|
|
|
// ---- Schedule Next Event Test --------------
|
|
|
|
if( EEsCycle > 192 )
|
|
{
|
|
// EE's running way ahead of the IOP still, so we should branch quickly to give the
|
|
// IOP extra timeslices in short order.
|
|
|
|
cpuSetNextBranchDelta( 48 );
|
|
//Console::Notice( "EE ahead of the IOP -- Rapid Branch! %d", params EEsCycle );
|
|
}
|
|
|
|
// The IOP could be running ahead/behind of us, so adjust the iop's next branch by its
|
|
// relative position to the EE (via EEsCycle)
|
|
cpuSetNextBranchDelta( ((g_psxNextBranchCycle-psxRegs.cycle)*8) - EEsCycle );
|
|
|
|
// Apply the hsync counter's nextCycle
|
|
cpuSetNextBranch( counters[4].sCycle, counters[4].CycleT );
|
|
|
|
// Apply vsync and other counter nextCycles
|
|
cpuSetNextBranch( nextsCounter, nextCounter );
|
|
|
|
eeEventTestIsActive = false;
|
|
|
|
// ---- INTC / DMAC Exceptions -----------------
|
|
// Raise the INTC and DMAC interrupts here, which usually throw exceptions.
|
|
// This should be done last since the IOP and the VU0 can raise several EE
|
|
// exceptions.
|
|
|
|
//if ((cpuRegs.CP0.n.Status.val & 0x10007) == 0x10001)
|
|
if( cpuIntsEnabled() )
|
|
{
|
|
TESTINT(30, intcInterrupt);
|
|
TESTINT(31, dmacInterrupt);
|
|
}
|
|
|
|
return vsyncEvent;
|
|
}
|
|
|
|
void cpuTestINTCInts()
|
|
{
|
|
if( cpuRegs.interrupt & (1 << 30) ) return;
|
|
//if( (cpuRegs.CP0.n.Status.val & 0x10407) != 0x10401 ) return;
|
|
if( !cpuIntsEnabled() ) return;
|
|
if( (psHu32(INTC_STAT) & psHu32(INTC_MASK)) == 0 ) return;
|
|
|
|
cpuRegs.interrupt|= 1 << 30;
|
|
cpuRegs.sCycle[30] = cpuRegs.cycle;
|
|
cpuRegs.eCycle[30] = 4; //Needs to be 4 to account for bus delays/pipelines etc
|
|
|
|
// only set the next branch delta if the exception won't be handled for
|
|
// the current branch...
|
|
if( !eeEventTestIsActive )
|
|
cpuSetNextBranchDelta( 4 );
|
|
else if(psxCycleEE > 0)
|
|
{
|
|
psxBreak += psxCycleEE; // record the number of cycles the IOP didn't run.
|
|
psxCycleEE = 0;
|
|
}
|
|
}
|
|
|
|
__forceinline void cpuTestDMACInts()
|
|
{
|
|
if ( cpuRegs.interrupt & (1 << 31) ) return;
|
|
if ((cpuRegs.CP0.n.Status.val & 0x10807) != 0x10801) return;
|
|
|
|
if ( ( (psHu16(0xe012) & psHu16(0xe010)) == 0) &&
|
|
( (psHu16(0xe010) & 0x8000) == 0) ) return;
|
|
|
|
cpuRegs.interrupt|= 1 << 31;
|
|
cpuRegs.sCycle[31] = cpuRegs.cycle;
|
|
cpuRegs.eCycle[31] = 4; //Needs to be 4 to account for bus delays/pipelines etc
|
|
|
|
// only set the next branch delta if the exception won't be handled for
|
|
// the current branch...
|
|
if( !eeEventTestIsActive )
|
|
cpuSetNextBranchDelta( 4 );
|
|
else if(psxCycleEE > 0)
|
|
{
|
|
psxBreak += psxCycleEE; // record the number of cycles the IOP didn't run.
|
|
psxCycleEE = 0;
|
|
}
|
|
}
|
|
|
|
__forceinline void cpuTestTIMRInts() {
|
|
if ((cpuRegs.CP0.n.Status.val & 0x10007) == 0x10001) {
|
|
_cpuTestPERF();
|
|
_cpuTestTIMR();
|
|
}
|
|
}
|
|
|
|
void cpuTestHwInts() {
|
|
cpuTestINTCInts();
|
|
cpuTestDMACInts();
|
|
cpuTestTIMRInts();
|
|
}
|
|
|
|
// This function performs a "hackish" execution of the BIOS stub, which initializes EE
|
|
// memory and hardware. It forcefully breaks execution when the stub is finished, prior
|
|
// to the PS2 logos being displayed. This allows us to "shortcut" right into a game
|
|
// without having to wait through the logos or endure game/bios localization checks.
|
|
void cpuExecuteBios()
|
|
{
|
|
// Set the video mode to user's default request:
|
|
// (right now we always default to NTSC)
|
|
gsSetVideoRegionType( Config.PsxType & 1 );
|
|
|
|
Console::Notice( "* PCSX2 *: ExecuteBios" );
|
|
|
|
bExecBIOS = TRUE;
|
|
while (cpuRegs.pc != 0x00200008 &&
|
|
cpuRegs.pc != 0x00100008) {
|
|
g_nextBranchCycle = cpuRegs.cycle;
|
|
Cpu->ExecuteBlock();
|
|
}
|
|
|
|
bExecBIOS = FALSE;
|
|
// {
|
|
// FILE* f = fopen("eebios.bin", "wb");
|
|
// fwrite(PSM(0x80000000), 0x100000, 1, f);
|
|
// fclose(f);
|
|
// exit(0);
|
|
|
|
// f = fopen("iopbios.bin", "wb");
|
|
// fwrite(PS2MEM_PSX, 0x80000, 1, f);
|
|
// fclose(f);
|
|
// }
|
|
|
|
// REC_CLEARM(0x00200008);
|
|
// REC_CLEARM(0x00100008);
|
|
// REC_CLEARM(cpuRegs.pc);
|
|
|
|
// Reset the EErecs here, because the bios generates "slow" blocks that have hacky
|
|
// bBiosEnd checks in them and stuff. This deletes them so that the recs replace them
|
|
// with new faster versions:
|
|
Cpu->Reset();
|
|
|
|
Console::Notice("* PCSX2 *: ExecuteBios Complete");
|
|
//GSprintf(5, "PCSX2 " PCSX2_VERSION "\nExecuteBios Complete\n");
|
|
}
|
|
|
|
__forceinline void CPU_INT( u32 n, s32 ecycle)
|
|
{
|
|
cpuRegs.interrupt|= 1 << n;
|
|
cpuRegs.sCycle[n] = cpuRegs.cycle;
|
|
cpuRegs.eCycle[n] = ecycle;
|
|
|
|
// Interrupt is happening soon: make sure both EE and IOP are aware.
|
|
|
|
if( ecycle <= 28 && psxCycleEE > 0 )
|
|
{
|
|
// If running in the IOP, force it to break immediately into the EE.
|
|
// the EE's branch test is due to run.
|
|
|
|
psxBreak += psxCycleEE; // record the number of cycles the IOP didn't run.
|
|
psxCycleEE = 0;
|
|
}
|
|
|
|
cpuSetNextBranchDelta( cpuRegs.eCycle[n] );
|
|
}
|