mirror of
https://github.com/PCSX2/pcsx2.git
synced 2025-04-02 10:52:54 -04:00
df521ae24f
git-svn-id: http://pcsx2.googlecode.com/svn/branches/pcsx2_0.9.4@186 96395faa-99c1-11dd-bbfe-3dabce05a288
516 lines
12 KiB
C++
516 lines
12 KiB
C++
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2007 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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// stop compiling if NORECBUILD build (only for Visual Studio)
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#if !(defined(_MSC_VER) && defined(PCSX2_NORECBUILD))
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#include "PS2Etypes.h"
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#if defined(_WIN32)
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#include <windows.h>
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#endif
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#include <assert.h>
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#include <vector>
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#include <list>
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using namespace std;
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extern "C" {
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#include "zlib.h"
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#include "Elfheader.h"
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#include "Misc.h"
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#include "System.h"
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#include "R5900.h"
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#include "Vif.h"
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#include "VU.h"
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#include "VifDma.h"
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#include "Memory.h"
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#include "Hw.h"
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#include "ix86/ix86.h"
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#include "iR5900.h"
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#include "Counters.h"
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#include "GS.h"
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extern u32 CSRw;
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}
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void CSRwrite(u32 value);
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#ifdef PCSX2_VIRTUAL_MEM
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#define PS2GS_BASE(mem) ((PS2MEM_BASE+0x12000000)+(mem&0x13ff))
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#else
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extern u8 g_RealGSMem[0x2000];
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#define PS2GS_BASE(mem) (g_RealGSMem+(mem&0x13ff))
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#endif
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void gsConstWrite8(u32 mem, int mmreg)
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{
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switch (mem&~3) {
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case 0x12001000: // GS_CSR
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_eeMoveMMREGtoR(EAX, mmreg);
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iFlushCall(0);
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MOV32MtoR(ECX, (uptr)&CSRw);
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AND32ItoR(EAX, 0xff<<(mem&3)*8);
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AND32ItoR(ECX, ~(0xff<<(mem&3)*8));
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OR32ItoR(EAX, ECX);
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_callFunctionArg1((uptr)CSRwrite, EAX|MEM_X86TAG, 0);
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break;
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default:
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_eeWriteConstMem8( (uptr)PS2GS_BASE(mem), mmreg );
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if( CHECK_MULTIGS ) {
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iFlushCall(0);
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_callFunctionArg3((uptr)GSRingBufSimplePacket, MEM_CONSTTAG, MEM_CONSTTAG, mmreg,
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GS_RINGTYPE_MEMWRITE8, mem&0x13ff, 0);
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}
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break;
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}
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}
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void recSetSMODE1()
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{
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iFlushCall(0);
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AND32ItoR(EAX, 0x6000);
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CMP32ItoR(EAX, 0x6000);
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j8Ptr[5] = JNE8(0);
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// PAL
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OR32ItoM( (uptr)&Config.PsxType, 1);
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j8Ptr[6] = JMP8(0);
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x86SetJ8( j8Ptr[5] );
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// NTSC
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AND32ItoM( (uptr)&Config.PsxType, ~1 );
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x86SetJ8( j8Ptr[6] );
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CALLFunc((uptr)UpdateVSyncRate);
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}
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void recSetSMODE2()
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{
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TEST32ItoR(EAX, 1);
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j8Ptr[5] = JZ8(0);
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// Interlaced
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OR32ItoM( (uptr)&Config.PsxType, 2);
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j8Ptr[6] = JMP8(0);
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x86SetJ8( j8Ptr[5] );
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// Non-Interlaced
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AND32ItoM( (uptr)&Config.PsxType, ~2 );
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x86SetJ8( j8Ptr[6] );
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}
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void gsConstWrite16(u32 mem, int mmreg)
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{
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switch (mem&~3) {
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case 0x12000010: // GS_SMODE1
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assert( !(mem&3));
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_eeMoveMMREGtoR(EAX, mmreg);
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_eeWriteConstMem16( (uptr)PS2GS_BASE(mem), mmreg );
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if( CHECK_MULTIGS )
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_callPushArg(MEM_X86TAG|EAX, 0, X86ARG3);
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recSetSMODE1();
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if( CHECK_MULTIGS ) {
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iFlushCall(0);
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_callPushArg(MEM_CONSTTAG, mem&0x13ff, X86ARG2);
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_callPushArg(MEM_CONSTTAG, GS_RINGTYPE_MEMWRITE16, X86ARG1);
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CALLFunc((uptr)GSRingBufSimplePacket);
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#ifndef __x86_64__
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ADD32ItoR(ESP, 12);
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#endif
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}
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break;
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case 0x12000020: // GS_SMODE2
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assert( !(mem&3));
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_eeMoveMMREGtoR(EAX, mmreg);
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_eeWriteConstMem16( (uptr)PS2GS_BASE(mem), mmreg );
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if( CHECK_MULTIGS )
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_callPushArg(MEM_X86TAG|EAX, 0, X86ARG3);
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recSetSMODE2();
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if( CHECK_MULTIGS ) {
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iFlushCall(0);
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_callPushArg(MEM_CONSTTAG, mem&0x13ff, X86ARG2);
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_callPushArg(MEM_CONSTTAG, GS_RINGTYPE_MEMWRITE16, X86ARG1);
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CALLFunc((uptr)GSRingBufSimplePacket);
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#ifndef __x86_64__
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ADD32ItoR(ESP, 12);
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#endif
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}
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break;
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case 0x12001000: // GS_CSR
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assert( !(mem&2) );
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_eeMoveMMREGtoR(EAX, mmreg);
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iFlushCall(0);
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MOV32MtoR(ECX, (uptr)&CSRw);
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AND32ItoR(EAX, 0xffff<<(mem&2)*8);
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AND32ItoR(ECX, ~(0xffff<<(mem&2)*8));
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OR32ItoR(EAX, ECX);
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_callFunctionArg1((uptr)CSRwrite, EAX|MEM_X86TAG, 0);
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break;
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default:
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_eeWriteConstMem16( (uptr)PS2GS_BASE(mem), mmreg );
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if( CHECK_MULTIGS ) {
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iFlushCall(0);
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_callFunctionArg3((uptr)GSRingBufSimplePacket, MEM_CONSTTAG, MEM_CONSTTAG, mmreg,
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GS_RINGTYPE_MEMWRITE16, mem&0x13ff, 0);
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}
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break;
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}
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}
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// (value&0x1f00)|0x6000
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void gsConstWriteIMR(int mmreg)
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{
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const u32 mem = 0x12001010;
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if( mmreg & MEM_XMMTAG ) {
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SSE2_MOVD_XMM_to_M32((uptr)PS2GS_BASE(mem), mmreg&0xf);
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AND32ItoM((uptr)PS2GS_BASE(mem), 0x1f00);
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OR32ItoM((uptr)PS2GS_BASE(mem), 0x6000);
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}
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#ifndef __x86_64__
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else if( mmreg & MEM_MMXTAG ) {
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SetMMXstate();
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MOVDMMXtoM((uptr)PS2GS_BASE(mem), mmreg&0xf);
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AND32ItoM((uptr)PS2GS_BASE(mem), 0x1f00);
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OR32ItoM((uptr)PS2GS_BASE(mem), 0x6000);
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}
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#endif
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else if( mmreg & MEM_EECONSTTAG ) {
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MOV32ItoM( (uptr)PS2GS_BASE(mem), (g_cpuConstRegs[(mmreg>>16)&0x1f].UL[0]&0x1f00)|0x6000);
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}
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else {
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AND32ItoR(mmreg, 0x1f00);
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OR32ItoR(mmreg, 0x6000);
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MOV32RtoM( (uptr)PS2GS_BASE(mem), mmreg );
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}
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// IMR doesn't need to be updated in MTGS mode
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}
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void gsConstWrite32(u32 mem, int mmreg) {
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switch (mem) {
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case 0x12000010: // GS_SMODE1
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_eeMoveMMREGtoR(EAX, mmreg);
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_eeWriteConstMem32( (uptr)PS2GS_BASE(mem), mmreg );
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if( CHECK_MULTIGS )
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_callPushArg(MEM_X86TAG|EAX, 0, X86ARG3);
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recSetSMODE1();
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if( CHECK_MULTIGS ) {
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iFlushCall(0);
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_callPushArg(MEM_CONSTTAG, mem&0x13ff, X86ARG2);
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_callPushArg(MEM_CONSTTAG, GS_RINGTYPE_MEMWRITE32, X86ARG1);
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CALLFunc((uptr)GSRingBufSimplePacket);
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#ifndef __x86_64__
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ADD32ItoR(ESP, 12);
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#endif
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}
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break;
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case 0x12000020: // GS_SMODE2
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_eeMoveMMREGtoR(EAX, mmreg);
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_eeWriteConstMem32( (uptr)PS2GS_BASE(mem), mmreg );
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if( CHECK_MULTIGS )
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_callPushArg(MEM_X86TAG|EAX, 0, X86ARG3);
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recSetSMODE2();
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if( CHECK_MULTIGS ) {
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iFlushCall(0);
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_callPushArg(MEM_CONSTTAG, mem&0x13ff, X86ARG2);
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_callPushArg(MEM_CONSTTAG, GS_RINGTYPE_MEMWRITE32, X86ARG1);
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CALLFunc((uptr)GSRingBufSimplePacket);
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#ifndef __x86_64__
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ADD32ItoR(ESP, 12);
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#endif
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}
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break;
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case 0x12001000: // GS_CSR
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iFlushCall(0);
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_callFunctionArg1((uptr)CSRwrite, mmreg, 0);
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break;
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case 0x12001010: // GS_IMR
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gsConstWriteIMR(mmreg);
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break;
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default:
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_eeWriteConstMem32( (uptr)PS2GS_BASE(mem), mmreg );
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if( CHECK_MULTIGS ) {
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iFlushCall(0);
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_callFunctionArg3((uptr)GSRingBufSimplePacket, MEM_CONSTTAG, MEM_CONSTTAG, mmreg,
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GS_RINGTYPE_MEMWRITE32, mem&0x13ff, 0);
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}
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break;
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}
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}
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void gsConstWrite64(u32 mem, int mmreg)
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{
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switch (mem) {
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case 0x12000010: // GS_SMODE1
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_eeMoveMMREGtoR(EAX, mmreg);
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_eeWriteConstMem64((uptr)PS2GS_BASE(mem), mmreg);
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if( CHECK_MULTIGS )
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_callPushArg(MEM_X86TAG|EAX, 0, X86ARG3);
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recSetSMODE1();
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if( CHECK_MULTIGS ) {
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iFlushCall(0);
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_callPushArg(MEM_CONSTTAG, mem&0x13ff, X86ARG2);
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_callPushArg(MEM_CONSTTAG, GS_RINGTYPE_MEMWRITE32, X86ARG1);
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CALLFunc((uptr)GSRingBufSimplePacket);
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#ifndef __x86_64__
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ADD32ItoR(ESP, 12);
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#endif
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}
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break;
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case 0x12000020: // GS_SMODE2
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_eeMoveMMREGtoR(EAX, mmreg);
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_eeWriteConstMem64((uptr)PS2GS_BASE(mem), mmreg);
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if( CHECK_MULTIGS )
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_callPushArg(MEM_X86TAG|EAX, 0, X86ARG3);
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recSetSMODE2();
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if( CHECK_MULTIGS ) {
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iFlushCall(0);
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_callPushArg(MEM_CONSTTAG, mem&0x13ff, X86ARG2);
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_callPushArg(MEM_CONSTTAG, GS_RINGTYPE_MEMWRITE32, X86ARG1);
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CALLFunc((uptr)GSRingBufSimplePacket);
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#ifndef __x86_64__
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ADD32ItoR(ESP, 12);
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#endif
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}
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break;
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case 0x12001000: // GS_CSR
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iFlushCall(0);
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_callFunctionArg1((uptr)CSRwrite, mmreg, 0);
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break;
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case 0x12001010: // GS_IMR
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gsConstWriteIMR(mmreg);
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break;
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default:
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_eeWriteConstMem64((uptr)PS2GS_BASE(mem), mmreg);
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if( CHECK_MULTIGS ) {
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iFlushCall(0);
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_callPushArg(MEM_MEMORYTAG, (uptr)PS2GS_BASE(mem)+4, X86ARG4);
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_callPushArg(MEM_MEMORYTAG, (uptr)PS2GS_BASE(mem), X86ARG3);
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_callPushArg(MEM_CONSTTAG, mem&0x13ff, X86ARG2);
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_callPushArg(MEM_CONSTTAG, GS_RINGTYPE_MEMWRITE64, X86ARG1);
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CALLFunc((uptr)GSRingBufSimplePacket);
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#ifndef __x86_64__
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ADD32ItoR(ESP, 16);
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#endif
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}
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break;
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}
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}
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void gsConstWrite128(u32 mem, int mmreg)
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{
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switch (mem) {
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case 0x12000010: // GS_SMODE1
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_eeMoveMMREGtoR(EAX, mmreg);
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_eeWriteConstMem128( (uptr)PS2GS_BASE(mem), mmreg);
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if( CHECK_MULTIGS )
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_callPushArg(MEM_X86TAG|EAX, 0, X86ARG3);
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recSetSMODE1();
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if( CHECK_MULTIGS ) {
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iFlushCall(0);
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_callPushArg(MEM_CONSTTAG, mem&0x13ff, X86ARG2);
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_callPushArg(MEM_CONSTTAG, GS_RINGTYPE_MEMWRITE32, X86ARG1);
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CALLFunc((uptr)GSRingBufSimplePacket);
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#ifndef __x86_64__
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ADD32ItoR(ESP, 12);
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#endif
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}
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break;
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case 0x12000020: // GS_SMODE2
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_eeMoveMMREGtoR(EAX, mmreg);
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_eeWriteConstMem128( (uptr)PS2GS_BASE(mem), mmreg);
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if( CHECK_MULTIGS )
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_callPushArg(MEM_X86TAG|EAX, 0, X86ARG3);
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recSetSMODE2();
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if( CHECK_MULTIGS ) {
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iFlushCall(0);
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_callPushArg(MEM_CONSTTAG, mem&0x13ff, X86ARG2);
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_callPushArg(MEM_CONSTTAG, GS_RINGTYPE_MEMWRITE32, X86ARG1);
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CALLFunc((uptr)GSRingBufSimplePacket);
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#ifndef __x86_64__
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ADD32ItoR(ESP, 12);
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#endif
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}
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break;
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case 0x12001000: // GS_CSR
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iFlushCall(0);
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_callFunctionArg1((uptr)CSRwrite, mmreg, 0);
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break;
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case 0x12001010: // GS_IMR
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// (value&0x1f00)|0x6000
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gsConstWriteIMR(mmreg);
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break;
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default:
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_eeWriteConstMem128( (uptr)PS2GS_BASE(mem), mmreg);
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if( CHECK_MULTIGS ) {
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iFlushCall(0);
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_callPushArg(MEM_MEMORYTAG, (uptr)PS2GS_BASE(mem)+4, X86ARG4);
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_callPushArg(MEM_MEMORYTAG, (uptr)PS2GS_BASE(mem), X86ARG3);
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_callPushArg(MEM_CONSTTAG, mem&0x13ff, X86ARG2);
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_callPushArg(MEM_CONSTTAG, GS_RINGTYPE_MEMWRITE64, X86ARG1);
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CALLFunc((uptr)GSRingBufSimplePacket);
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#ifndef __x86_64__
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ADD32ItoR(ESP, 16);
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#endif
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_callPushArg(MEM_MEMORYTAG, (uptr)PS2GS_BASE(mem)+12, X86ARG4);
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_callPushArg(MEM_MEMORYTAG, (uptr)PS2GS_BASE(mem)+8, X86ARG3);
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_callPushArg(MEM_CONSTTAG, (mem&0x13ff)+8, X86ARG2);
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_callPushArg(MEM_CONSTTAG, GS_RINGTYPE_MEMWRITE64, X86ARG1);
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CALLFunc((uptr)GSRingBufSimplePacket);
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#ifndef __x86_64__
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ADD32ItoR(ESP, 16);
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#endif
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}
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break;
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}
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}
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int gsConstRead8(u32 x86reg, u32 mem, u32 sign)
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{
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#ifdef GIF_LOG
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GIF_LOG("GS read 8 %8.8lx (%8.8x), at %8.8lx\n", (uptr)PS2GS_BASE(mem), mem);
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#endif
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_eeReadConstMem8(x86reg, (uptr)PS2GS_BASE(mem), sign);
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return 0;
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}
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int gsConstRead16(u32 x86reg, u32 mem, u32 sign)
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{
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#ifdef GIF_LOG
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GIF_LOG("GS read 16 %8.8lx (%8.8x), at %8.8lx\n", (uptr)PS2GS_BASE(mem), mem);
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#endif
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_eeReadConstMem16(x86reg, (uptr)PS2GS_BASE(mem), sign);
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return 0;
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}
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int gsConstRead32(u32 x86reg, u32 mem)
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{
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#ifdef GIF_LOG
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GIF_LOG("GS read 32 %8.8lx (%8.8x), at %8.8lx\n", (uptr)PS2GS_BASE(mem), mem);
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#endif
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_eeReadConstMem32(x86reg, (uptr)PS2GS_BASE(mem));
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return 0;
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}
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void gsConstRead64(u32 mem, int mmreg)
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{
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#ifdef GIF_LOG
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GIF_LOG("GS read 64 %8.8lx (%8.8x), at %8.8lx\n", (uptr)PS2GS_BASE(mem), mem);
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#endif
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if( IS_XMMREG(mmreg) ) SSE_MOVLPS_M64_to_XMM(mmreg&0xff, (uptr)PS2GS_BASE(mem));
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else {
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#ifndef __x86_64__
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MOVQMtoR(mmreg, (uptr)PS2GS_BASE(mem));
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SetMMXstate();
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#else
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assert(0);
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#endif
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|
}
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|
}
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|
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void gsConstRead128(u32 mem, int xmmreg)
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|
{
|
|
#ifdef GIF_LOG
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|
GIF_LOG("GS read 128 %8.8lx (%8.8x), at %8.8lx\n", (uptr)PS2GS_BASE(mem), mem);
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#endif
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_eeReadConstMem128( xmmreg, (uptr)PS2GS_BASE(mem));
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}
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|
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#endif // PCSX2_NORECBUILD
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