mirror of
https://github.com/PCSX2/pcsx2.git
synced 2025-04-02 10:52:54 -04:00
df521ae24f
git-svn-id: http://pcsx2.googlecode.com/svn/branches/pcsx2_0.9.4@186 96395faa-99c1-11dd-bbfe-3dabce05a288
364 lines
9.3 KiB
C
364 lines
9.3 KiB
C
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2005 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#if !(defined(_MSC_VER) && defined(PCSX2_NORECBUILD))
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#include "Common.h"
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#include "InterTables.h"
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#include "ix86/ix86.h"
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#include "iR5900.h"
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#include "iCP0.h"
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/*********************************************************
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* COP0 opcodes *
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* *
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*********************************************************/
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#ifndef CP0_RECOMPILE
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REC_SYS(MFC0);
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REC_SYS(MTC0);
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REC_SYS(BC0F);
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REC_SYS(BC0T);
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REC_SYS(BC0FL);
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REC_SYS(BC0TL);
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REC_SYS(TLBR);
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REC_SYS(TLBWI);
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REC_SYS(TLBWR);
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REC_SYS(TLBP);
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REC_SYS(ERET);
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REC_SYS(DI);
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REC_SYS(EI);
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#else
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////////////////////////////////////////////////////
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//REC_SYS(MTC0);
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////////////////////////////////////////////////////
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REC_SYS(BC0F);
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////////////////////////////////////////////////////
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REC_SYS(BC0T);
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////////////////////////////////////////////////////
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REC_SYS(BC0FL);
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////////////////////////////////////////////////////
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REC_SYS(BC0TL);
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////////////////////////////////////////////////////
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REC_SYS(TLBR);
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////////////////////////////////////////////////////
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REC_SYS(TLBWI);
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////////////////////////////////////////////////////
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REC_SYS(TLBWR);
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////////////////////////////////////////////////////
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REC_SYS(TLBP);
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////////////////////////////////////////////////////
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REC_SYS(ERET);
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////////////////////////////////////////////////////
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REC_SYS(DI);
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////////////////////////////////////////////////////
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REC_SYS(EI);
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////////////////////////////////////////////////////
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extern u32 s_iLastCOP0Cycle;
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extern u32 s_iLastPERFCycle[2];
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void recMFC0( void )
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{
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int mmreg;
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if ( ! _Rt_ ) return;
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if( _Rd_ == 9 ) {
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MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
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MOV32RtoR(EAX,ECX);
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SUB32MtoR(EAX, (uptr)&s_iLastCOP0Cycle);
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ADD32RtoM((uptr)&cpuRegs.CP0.n.Count, EAX);
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MOV32RtoM((uptr)&s_iLastCOP0Cycle, ECX);
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MOV32MtoR( EAX, (uptr)&cpuRegs.CP0.r[ _Rd_ ] );
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_deleteEEreg(_Rt_, 0);
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[0],EAX);
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if(EEINST_ISLIVE1(_Rt_)) {
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CDQ();
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[1], EDX);
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}
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else EEINST_RESETHASLIVE1(_Rt_);
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return;
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}
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if( _Rd_ == 25 ) {
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_deleteEEreg(_Rt_, 0);
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switch(_Imm_ & 0x3F){
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case 0:
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MOV32MtoR(EAX, (uptr)&cpuRegs.PERF.n.pccr);
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break;
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case 1:
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// check if needs to be incremented
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MOV32MtoR(ECX, (uptr)&cpuRegs.PERF.n.pccr);
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MOV32MtoR(EAX, (uptr)&cpuRegs.PERF.n.pcr0);
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AND32ItoR(ECX, 0x800003E0);
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CMP32ItoR(ECX, 0x80000020);
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j8Ptr[0] = JNE8(0);
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MOV32MtoR(EDX, (uptr)&cpuRegs.cycle);
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SUB32MtoR(EAX, (uptr)&s_iLastPERFCycle[0]);
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ADD32RtoR(EAX, EDX);
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MOV32RtoM((uptr)&s_iLastPERFCycle[0], EDX);
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MOV32RtoM((uptr)&cpuRegs.PERF.n.pcr0, EAX);
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x86SetJ8(j8Ptr[0]);
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break;
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case 3:
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// check if needs to be incremented
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MOV32MtoR(ECX, (uptr)&cpuRegs.PERF.n.pccr);
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MOV32MtoR(EAX, (uptr)&cpuRegs.PERF.n.pcr1);
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AND32ItoR(ECX, 0x800F8000);
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CMP32ItoR(ECX, 0x80008000);
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j8Ptr[0] = JNE8(0);
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MOV32MtoR(EDX, (uptr)&cpuRegs.cycle);
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SUB32MtoR(EAX, (uptr)&s_iLastPERFCycle[1]);
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ADD32RtoR(EAX, EDX);
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MOV32RtoM((uptr)&s_iLastPERFCycle[1], EDX);
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MOV32RtoM((uptr)&cpuRegs.PERF.n.pcr1, EAX);
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x86SetJ8(j8Ptr[0]);
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break;
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}
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[0],EAX);
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if(EEINST_ISLIVE1(_Rt_)) {
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CDQ();
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[1], EDX);
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}
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else EEINST_RESETHASLIVE1(_Rt_);
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#ifdef PCSX2_DEVBUILD
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SysPrintf("MFC0 PCCR = %x PCR0 = %x PCR1 = %x IMM= %x\n",
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cpuRegs.PERF.n.pccr, cpuRegs.PERF.n.pcr0, cpuRegs.PERF.n.pcr1, _Imm_ & 0x3F);
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#endif
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return;
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}
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else if( _Rd_ == 24){
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SysPrintf("MFC0 Breakpoint debug Registers code = %x\n", cpuRegs.code & 0x3FF);
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return;
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}
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_eeOnWriteReg(_Rt_, 1);
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if( EEINST_ISLIVE1(_Rt_) ) {
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_deleteEEreg(_Rt_, 0);
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MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.r[ _Rd_ ]);
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CDQ();
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[0], EAX);
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[1], EDX);
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}
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else {
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EEINST_RESETHASLIVE1(_Rt_);
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#ifndef __x86_64__
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if( (mmreg = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rt_, MODE_WRITE)) >= 0 ) {
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MOVDMtoMMX(mmreg, (uptr)&cpuRegs.CP0.r[ _Rd_ ]);
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SetMMXstate();
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}
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else
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#endif
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if( (mmreg = _checkXMMreg(XMMTYPE_GPRREG, _Rt_, MODE_READ)) >= 0) {
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if( EEINST_ISLIVE2(_Rt_) ) {
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if( xmmregs[mmreg].mode & MODE_WRITE ) {
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SSE_MOVHPS_XMM_to_M64((uptr)&cpuRegs.GPR.r[_Rt_].UL[2], mmreg);
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}
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xmmregs[mmreg].inuse = 0;
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MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.r[ _Rd_ ]);
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[0],EAX);
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}
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else {
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SSE_MOVLPS_M64_to_XMM(mmreg, (uptr)&cpuRegs.CP0.r[ _Rd_ ]);
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}
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}
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else {
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MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.r[ _Rd_ ]);
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if(_Rd_ == 12) AND32ItoR(EAX, 0xf0c79c1f);
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[0],EAX);
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if(EEINST_ISLIVE1(_Rt_)) {
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CDQ();
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[1], EDX);
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}
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else {
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EEINST_RESETHASLIVE1(_Rt_);
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}
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}
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}
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}
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void updatePCCR()
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{
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// read the old pccr and update pcr0/1
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MOV32MtoR(EAX, (uptr)&cpuRegs.PERF.n.pccr);
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MOV32RtoR(EDX, EAX);
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MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
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AND32ItoR(EAX, 0x800003E0);
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CMP32ItoR(EAX, 0x80000020);
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j8Ptr[0] = JNE8(0);
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MOV32MtoR(EAX, (uptr)&s_iLastPERFCycle[0]);
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ADD32RtoM((uptr)&cpuRegs.PERF.n.pcr0, ECX);
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SUB32RtoM((uptr)&cpuRegs.PERF.n.pcr0, EAX);
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x86SetJ8(j8Ptr[0]);
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AND32ItoR(EDX, 0x800F8000);
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CMP32ItoR(EDX, 0x80008000);
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j8Ptr[0] = JNE8(0);
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MOV32MtoR(EAX, (uptr)&s_iLastPERFCycle[1]);
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ADD32RtoM((uptr)&cpuRegs.PERF.n.pcr1, ECX);
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SUB32RtoM((uptr)&cpuRegs.PERF.n.pcr1, EAX);
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x86SetJ8(j8Ptr[0]);
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}
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void recMTC0()
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{
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if( GPR_IS_CONST1(_Rt_) ) {
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switch (_Rd_) {
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case 12:
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iFlushCall(FLUSH_NODESTROY);
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//_flushCachedRegs(); //NOTE: necessary?
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_callFunctionArg1((uptr)WriteCP0Status, MEM_CONSTTAG, g_cpuConstRegs[_Rt_].UL[0]);
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break;
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case 9:
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MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
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MOV32RtoM((uptr)&s_iLastCOP0Cycle, ECX);
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MOV32ItoM((uptr)&cpuRegs.CP0.r[9], g_cpuConstRegs[_Rt_].UL[0]);
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break;
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case 25:
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SysPrintf("MTC0 PCCR = %x PCR0 = %x PCR1 = %x IMM= %x\n",
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cpuRegs.PERF.n.pccr, cpuRegs.PERF.n.pcr0, cpuRegs.PERF.n.pcr1, _Imm_ & 0x3F);
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switch(_Imm_ & 0x3F){
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case 0:
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updatePCCR();
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MOV32ItoM((uptr)&cpuRegs.PERF.n.pccr, g_cpuConstRegs[_Rt_].UL[0]);
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// update the cycles
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MOV32RtoM((uptr)&s_iLastPERFCycle[0], ECX);
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MOV32RtoM((uptr)&s_iLastPERFCycle[1], ECX);
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break;
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case 1:
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MOV32MtoR(EAX, (uptr)&cpuRegs.cycle);
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MOV32ItoM((uptr)&cpuRegs.PERF.n.pcr0, g_cpuConstRegs[_Rt_].UL[0]);
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MOV32RtoM((uptr)&s_iLastPERFCycle[0], EAX);
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break;
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case 3:
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MOV32MtoR(EAX, (uptr)&cpuRegs.cycle);
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MOV32ItoM((uptr)&cpuRegs.PERF.n.pcr1, g_cpuConstRegs[_Rt_].UL[0]);
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MOV32RtoM((uptr)&s_iLastPERFCycle[1], EAX);
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break;
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}
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break;
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case 24:
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SysPrintf("MTC0 Breakpoint debug Registers code = %x\n", cpuRegs.code & 0x3FF);
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break;
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default:
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MOV32ItoM((uptr)&cpuRegs.CP0.r[_Rd_], g_cpuConstRegs[_Rt_].UL[0]);
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break;
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}
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}
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else {
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switch (_Rd_) {
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case 12:
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iFlushCall(FLUSH_NODESTROY);
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//_flushCachedRegs(); //NOTE: necessary?
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_callFunctionArg1((uptr)WriteCP0Status, MEM_GPRTAG|_Rt_, 0);
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break;
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case 9:
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MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
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_eeMoveGPRtoM((uptr)&cpuRegs.CP0.r[9], _Rt_);
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MOV32RtoM((uptr)&s_iLastCOP0Cycle, ECX);
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break;
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case 25:
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SysPrintf("MTC0 PCCR = %x PCR0 = %x PCR1 = %x IMM= %x\n",
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cpuRegs.PERF.n.pccr, cpuRegs.PERF.n.pcr0, cpuRegs.PERF.n.pcr1, _Imm_ & 0x3F);
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switch(_Imm_ & 0x3F){
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case 0:
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updatePCCR();
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_eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pccr, _Rt_);
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// update the cycles
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MOV32RtoM((uptr)&s_iLastPERFCycle[0], ECX);
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MOV32RtoM((uptr)&s_iLastPERFCycle[1], ECX);
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break;
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case 1:
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MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
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_eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pcr0, _Rt_);
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MOV32RtoM((uptr)&s_iLastPERFCycle[0], ECX);
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break;
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case 3:
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MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
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_eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pcr1, _Rt_);
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MOV32RtoM((uptr)&s_iLastPERFCycle[1], ECX);
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break;
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}
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break;
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case 24:
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SysPrintf("MTC0 Breakpoint debug Registers code = %x\n", cpuRegs.code & 0x3FF);
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break;
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default:
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_eeMoveGPRtoM((uptr)&cpuRegs.CP0.r[_Rd_], _Rt_);
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break;
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}
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}
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}
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/*void rec(COP0) {
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}
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void rec(BC0F) {
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}
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void rec(BC0T) {
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}
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void rec(BC0FL) {
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}
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void rec(BC0TL) {
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}
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void rec(TLBR) {
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}
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void rec(TLBWI) {
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}
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void rec(TLBWR) {
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}
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void rec(TLBP) {
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}
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void rec(ERET) {
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}
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*/
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#endif
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#endif // PCSX2_NORECBUILD
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