mirror of
https://github.com/PCSX2/pcsx2.git
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df521ae24f
git-svn-id: http://pcsx2.googlecode.com/svn/branches/pcsx2_0.9.4@186 96395faa-99c1-11dd-bbfe-3dabce05a288
349 lines
7.1 KiB
ArmAsm
349 lines
7.1 KiB
ArmAsm
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2005 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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// Fast assembly routines for x86-64
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// zerofrog(@gmail.com)
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.intel_syntax
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.extern g_EEFreezeRegs
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.extern FreezeMMXRegs_
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// mmx memcmp implementation, size has to be a multiple of 8
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// returns 0 is equal, nonzero value if not equal
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// ~10 times faster than standard memcmp
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// (zerofrog)
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// u8 memcmp_mmx(const void* src1, const void* src2, int cmpsize)
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#ifdef __x86_64__
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#define MEMCMP_SRC1 %rdi
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#define MEMCMP_SRC2 %rsi
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#define MEMCMP_SIZE %edx
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#else
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#define MEMCMP_SRC1 %edx
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#define MEMCMP_SRC2 %esi
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#define MEMCMP_SIZE %ecx
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#endif
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.globl memcmp_mmx
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memcmp_mmx:
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#ifndef __x86_64__
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// make sure mmx regs are stored
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// FreezeMMXRegs(1);
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cmp dword ptr [g_EEFreezeRegs], 0
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je memcmp_mmx_begin
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push 1
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call FreezeMMXRegs_
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add %esp, 4
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memcmp_mmx_begin:
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push %esi
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mov MEMCMP_SRC1, dword ptr [%esp+8]
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mov MEMCMP_SRC2, dword ptr [%esp+12]
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mov MEMCMP_SIZE, dword ptr [%esp+16]
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#endif
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cmp MEMCMP_SIZE, 32
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jl memcmp_Done4
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// custom test first 8 to make sure things are ok
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movq %mm0, [MEMCMP_SRC2]
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movq %mm1, [MEMCMP_SRC2+8]
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pcmpeqd %mm0, [MEMCMP_SRC1]
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pcmpeqd %mm1, [MEMCMP_SRC1+8]
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pand %mm0, %mm1
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movq %mm2, [MEMCMP_SRC2+16]
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pmovmskb %eax, %mm0
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movq %mm3, [MEMCMP_SRC2+24]
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// check if eq
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cmp %eax, 0xff
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je memcmp_NextComp
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mov %eax, 1
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jmp memcmp_End
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memcmp_NextComp:
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pcmpeqd %mm2, [MEMCMP_SRC1+16]
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pcmpeqd %mm3, [MEMCMP_SRC1+24]
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pand %mm2, %mm3
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pmovmskb %eax, %mm2
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sub MEMCMP_SIZE, 32
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add MEMCMP_SRC2, 32
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add MEMCMP_SRC1, 32
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// check if eq
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cmp %eax, 0xff
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je memcmp_ContinueTest
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mov %eax, 1
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jmp memcmp_End
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cmp MEMCMP_SIZE, 64
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jl memcmp_Done8
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memcmp_Cmp8:
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movq %mm0, [MEMCMP_SRC2]
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movq %mm1, [MEMCMP_SRC2+8]
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movq %mm2, [MEMCMP_SRC2+16]
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movq %mm3, [MEMCMP_SRC2+24]
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movq %mm4, [MEMCMP_SRC2+32]
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movq %mm5, [MEMCMP_SRC2+40]
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movq %mm6, [MEMCMP_SRC2+48]
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movq %mm7, [MEMCMP_SRC2+56]
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pcmpeqd %mm0, [MEMCMP_SRC1]
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pcmpeqd %mm1, [MEMCMP_SRC1+8]
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pcmpeqd %mm2, [MEMCMP_SRC1+16]
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pcmpeqd %mm3, [MEMCMP_SRC1+24]
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pand %mm0, %mm1
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pcmpeqd %mm4, [MEMCMP_SRC1+32]
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pand %mm0, %mm2
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pcmpeqd %mm5, [MEMCMP_SRC1+40]
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pand %mm0, %mm3
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pcmpeqd %mm6, [MEMCMP_SRC1+48]
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pand %mm0, %mm4
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pcmpeqd %mm7, [MEMCMP_SRC1+56]
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pand %mm0, %mm5
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pand %mm0, %mm6
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pand %mm0, %mm7
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pmovmskb %eax, %mm0
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// check if eq
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cmp %eax, 0xff
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je memcmp_Continue
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mov %eax, 1
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jmp memcmp_End
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memcmp_Continue:
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sub MEMCMP_SIZE, 64
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add MEMCMP_SRC2, 64
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add MEMCMP_SRC1, 64
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memcmp_ContinueTest:
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cmp MEMCMP_SIZE, 64
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jge memcmp_Cmp8
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memcmp_Done8:
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test MEMCMP_SIZE, 0x20
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jz memcmp_Done4
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movq %mm0, [MEMCMP_SRC2]
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movq %mm1, [MEMCMP_SRC2+8]
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movq %mm2, [MEMCMP_SRC2+16]
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movq %mm3, [MEMCMP_SRC2+24]
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pcmpeqd %mm0, [MEMCMP_SRC1]
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pcmpeqd %mm1, [MEMCMP_SRC1+8]
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pcmpeqd %mm2, [MEMCMP_SRC1+16]
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pcmpeqd %mm3, [MEMCMP_SRC1+24]
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pand %mm0, %mm1
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pand %mm0, %mm2
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pand %mm0, %mm3
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pmovmskb %eax, %mm0
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sub MEMCMP_SIZE, 32
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add MEMCMP_SRC2, 32
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add MEMCMP_SRC1, 32
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// check if eq
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cmp %eax, 0xff
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je memcmp_Done4
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mov %eax, 1
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jmp memcmp_End
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memcmp_Done4:
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cmp MEMCMP_SIZE, 24
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jne memcmp_Done2
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movq %mm0, [MEMCMP_SRC2]
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movq %mm1, [MEMCMP_SRC2+8]
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movq %mm2, [MEMCMP_SRC2+16]
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pcmpeqd %mm0, [MEMCMP_SRC1]
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pcmpeqd %mm1, [MEMCMP_SRC1+8]
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pcmpeqd %mm2, [MEMCMP_SRC1+16]
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pand %mm0, %mm1
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pand %mm0, %mm2
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pmovmskb %eax, %mm0
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// check if eq
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cmp %eax, 0xff
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je memcmp_Done
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mov %eax, 1
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jmp memcmp_End
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memcmp_Done2:
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cmp MEMCMP_SIZE, 16
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jne memcmp_Done1
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movq %mm0, [MEMCMP_SRC2]
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movq %mm1, [MEMCMP_SRC2+8]
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pcmpeqd %mm0, [MEMCMP_SRC1]
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pcmpeqd %mm1, [MEMCMP_SRC1+8]
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pand %mm0, %mm1
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pmovmskb %eax, %mm0
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// check if eq
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cmp %eax, 0xff
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je memcmp_Done
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mov %eax, 1
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jmp memcmp_End
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memcmp_Done1:
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cmp MEMCMP_SIZE, 8
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jne memcmp_Done
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mov %eax, [MEMCMP_SRC2]
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mov MEMCMP_SRC2, [MEMCMP_SRC2+4]
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cmp %eax, [MEMCMP_SRC1]
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je memcmp_Next
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mov %eax, 1
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jmp memcmp_End
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memcmp_Next:
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cmp MEMCMP_SRC2, [MEMCMP_SRC1+4]
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je memcmp_Done
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mov %eax, 1
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jmp memcmp_End
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memcmp_Done:
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xor %eax, %eax
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memcmp_End:
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emms
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#ifndef __x86_64__
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pop %esi
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#endif
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ret
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// memxor_mmx
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#ifdef __x86_64__
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#define MEMXOR_SRC1 %rdi
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#define MEMXOR_SRC2 %rsi
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#define MEMXOR_SIZE %edx
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#else
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#define MEMXOR_SRC1 %edx
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#define MEMXOR_SRC2 %esi
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#define MEMXOR_SIZE %ecx
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#endif
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.globl memxor_mmx
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memxor_mmx:
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#ifndef __x86_64__
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// make sure mmx regs are stored
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// FreezeMMXRegs(1);
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cmp dword ptr [g_EEFreezeRegs], 0
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je memxor_mmx_begin
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push 1
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call FreezeMMXRegs_
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add %esp, 4
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memxor_mmx_begin:
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push %esi
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mov MEMXOR_SRC1, dword ptr [%esp+8]
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mov MEMXOR_SRC2, dword ptr [%esp+12]
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mov MEMXOR_SIZE, dword ptr [%esp+16]
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#endif
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cmp MEMXOR_SIZE, 64
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jl memxor_Setup4
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movq %mm0, [MEMXOR_SRC2]
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movq %mm1, [MEMXOR_SRC2+8]
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movq %mm2, [MEMXOR_SRC2+16]
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movq %mm3, [MEMXOR_SRC2+24]
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movq %mm4, [MEMXOR_SRC2+32]
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movq %mm5, [MEMXOR_SRC2+40]
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movq %mm6, [MEMXOR_SRC2+48]
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movq %mm7, [MEMXOR_SRC2+56]
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sub MEMXOR_SIZE, 64
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add MEMXOR_SRC2, 64
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cmp MEMXOR_SIZE, 64
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jl memxor_End8
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memxor_Cmp8:
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pxor %mm0, [MEMXOR_SRC2]
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pxor %mm1, [MEMXOR_SRC2+8]
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pxor %mm2, [MEMXOR_SRC2+16]
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pxor %mm3, [MEMXOR_SRC2+24]
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pxor %mm4, [MEMXOR_SRC2+32]
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pxor %mm5, [MEMXOR_SRC2+40]
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pxor %mm6, [MEMXOR_SRC2+48]
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pxor %mm7, [MEMXOR_SRC2+56]
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sub MEMXOR_SIZE, 64
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add MEMXOR_SRC2, 64
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cmp MEMXOR_SIZE, 64
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jge memxor_Cmp8
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memxor_End8:
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pxor %mm0, %mm4
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pxor %mm1, %mm5
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pxor %mm2, %mm6
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pxor %mm3, %mm7
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cmp MEMXOR_SIZE, 32
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jl memxor_End4
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pxor %mm0, [MEMXOR_SRC2]
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pxor %mm1, [MEMXOR_SRC2+8]
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pxor %mm2, [MEMXOR_SRC2+16]
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pxor %mm3, [MEMXOR_SRC2+24]
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sub MEMXOR_SIZE, 32
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add MEMXOR_SRC2, 32
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jmp memxor_End4
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memxor_Setup4:
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cmp MEMXOR_SIZE, 32
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jl memxor_Setup2
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movq %mm0, [MEMXOR_SRC2]
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movq %mm1, [MEMXOR_SRC2+8]
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movq %mm2, [MEMXOR_SRC2+16]
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movq %mm3, [MEMXOR_SRC2+24]
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sub MEMXOR_SIZE, 32
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add MEMXOR_SRC2, 32
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memxor_End4:
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pxor %mm0, %mm2
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pxor %mm1, %mm3
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cmp MEMXOR_SIZE, 16
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jl memxor_End2
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pxor %mm0, [MEMXOR_SRC2]
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pxor %mm1, [MEMXOR_SRC2+8]
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sub MEMXOR_SIZE, 16
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add MEMXOR_SRC2, 16
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jmp memxor_End2
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memxor_Setup2:
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cmp MEMXOR_SIZE, 16
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jl memxor_Setup1
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movq %mm0, [MEMXOR_SRC2]
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movq %mm1, [MEMXOR_SRC2+8]
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sub MEMXOR_SIZE, 16
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add MEMXOR_SRC2, 16
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memxor_End2:
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pxor %mm0, %mm1
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cmp MEMXOR_SIZE, 8
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jl memxor_End1
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pxor %mm0, [MEMXOR_SRC2]
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memxor_End1:
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movq [MEMXOR_SRC1], %mm0
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jmp memxor_End
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memxor_Setup1:
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movq %mm0, [MEMXOR_SRC2]
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movq [MEMXOR_SRC1], %mm0
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memxor_End:
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emms
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#ifndef __x86_64__
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pop %esi
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#endif
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ret
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