mirror of
https://github.com/PCSX2/pcsx2.git
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afcd1c9784
git-svn-id: http://pcsx2.googlecode.com/svn/branches/pcsx2_0.9.2@159 96395faa-99c1-11dd-bbfe-3dabce05a288
631 lines
18 KiB
C
631 lines
18 KiB
C
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2003 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <string.h>
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#include <math.h>
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#include "PsxCommon.h"
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psxCounter psxCounters[8];
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u32 psxNextCounter, psxNextsCounter;
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static int cnts = 6;
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u8 psxhblankgate = 0;
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u8 psxvblankgate = 0;
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u8 psxcntmask = 0;
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static void psxRcntUpd16(u32 index) {
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//psxCounters[index].sCycle = psxRegs.cycle;
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psxCounters[index].sCycleT = psxRegs.cycle - (psxRegs.cycle % psxCounters[index].rate);
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//psxCounters[index].Cycle = (0xffff - psxCounters[index].count) * psxCounters[index].rate;
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//psxCounters[index].CycleT = (psxCounters[index].target - psxCounters[index].count) * psxCounters[index].rate;
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}
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static void psxRcntUpd32(u32 index) {
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//psxCounters[index].sCycle = psxRegs.cycle;
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psxCounters[index].sCycleT = psxRegs.cycle - (psxRegs.cycle % psxCounters[index].rate);
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//psxCounters[index].Cycle = (0xfffee000 - psxCounters[index].count) * psxCounters[index].rate;
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//psxCounters[index].CycleT = (psxCounters[index].target - psxCounters[index].count) * psxCounters[index].rate;
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}
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static void psxRcntReset16(u32 index) {
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psxCounters[index].count = 0;
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psxCounters[index].mode&= ~0x18301C00;
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psxRcntUpd16(index);
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}
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static void psxRcntReset32(u32 index) {
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psxCounters[index].count = 0;
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psxCounters[index].mode&= ~0x18301C00;
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psxRcntUpd32(index);
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}
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static void psxRcntSet() {
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u32 c;
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int i;
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psxNextCounter = 0xffffffff;
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psxNextsCounter = psxRegs.cycle;
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for (i=0; i<3; i++) {
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c = (u32)(0xffff - psxRcntCycles(i)) * psxCounters[i].rate;
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if (c < psxNextCounter) {
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psxNextCounter = c;
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}
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//if(psxCounters[i].mode & 0x0800) continue;
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c = (u32)(psxCounters[i].target - psxRcntCycles(i)) * psxCounters[i].rate;
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if (c < psxNextCounter) {
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psxNextCounter = c;
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}
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}
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for (i=3; i<6; i++) {
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c = (u32)(0xfffee000 - psxRcntCycles(i)) * psxCounters[i].rate;
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if (c < psxNextCounter) {
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psxNextCounter = c;
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}
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//if(psxCounters[i].mode & 0x0800) continue;
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c = (u32)(psxCounters[i].target - psxRcntCycles(i)) * psxCounters[i].rate;
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if (c < psxNextCounter) {
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psxNextCounter = c;
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}
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}
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c = (u32)(psxCounters[6].CycleT - (psxRegs.cycle - psxCounters[6].sCycleT)) ;
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if (c < psxNextCounter) {
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psxNextCounter = c;
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}
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}
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void psxRcntInit() {
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int i;
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memset(psxCounters, 0, sizeof(psxCounters));
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for (i=0; i<3; i++) {
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psxCounters[i].rate = 1;
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psxCounters[i].mode|= 0x0400;
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psxCounters[i].target = 0x0;
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}
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for (i=3; i<6; i++) {
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psxCounters[i].rate = 1;
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psxCounters[i].mode|= 0x0400;
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psxCounters[i].target = 0x0;
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}
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psxCounters[0].interrupt = 0x10;
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psxCounters[1].interrupt = 0x20;
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psxCounters[2].interrupt = 0x40;
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psxCounters[3].interrupt = 0x04000;
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psxCounters[4].interrupt = 0x08000;
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psxCounters[5].interrupt = 0x10000;
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if (SPU2async != NULL) {
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cnts = 7;
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psxCounters[6].rate = 1;
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psxCounters[6].CycleT = 48000;
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psxCounters[6].mode = 0x8;
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} else cnts = 6;
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for (i=0; i<3; i++)
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psxCounters[i].sCycleT = psxRegs.cycle;
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for (i=3; i<6; i++)
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psxCounters[i].sCycleT = psxRegs.cycle;
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for (i=6; i<cnts; i++)
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psxCounters[i].sCycleT = psxRegs.cycle;
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psxRcntSet();
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}
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void psxVSyncStart() {
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cdvdVsync();
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psxHu32(0x1070)|= 1;
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if(psxvblankgate & 1) psxCheckStartGate(1);
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if(psxvblankgate & (1 << 3)) psxCheckStartGate(3);
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}
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void psxVSyncEnd() {
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psxHu32(0x1070)|= 0x800;
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if(psxvblankgate & 1) psxCheckEndGate(1);
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if(psxvblankgate & (1 << 3)) psxCheckEndGate(3);
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}
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void psxCheckEndGate(int counter) { //Check Gate events when Vsync Ends
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int i = counter;
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//SysPrintf("End Gate %x\n", counter);
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if(counter < 3){ //Gates for 16bit counters
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if((psxCounters[i].mode & 0x1) == 0) return; //Ignore Gate
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switch((psxCounters[i].mode & 0x6) >> 1) {
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case 0x0: //GATE_ON_count
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psxCounters[i].count += (u16)psxRcntRcount16(i); //Only counts when signal is on
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break;
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case 0x1: //GATE_ON_ClearStart
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if(psxCounters[i].mode & 0x10000000)psxRcntUpd16(i);
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psxCounters[i].mode &= ~0x10000000;
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break;
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case 0x2: //GATE_ON_Clear_OFF_Start
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psxCounters[i].mode &= ~0x10000000;
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psxRcntUpd16(i);
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break;
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case 0x3: //GATE_ON_Start
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break;
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default:
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SysPrintf("PCSX2 Warning: 16bit IOP Counter Gate Not Set!\n");
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break;
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}
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}
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if(counter >= 3){ //Gates for 32bit counters
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if((psxCounters[i].mode & 0x1) == 0) return; //Ignore Gate
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switch((psxCounters[i].mode & 0x6) >> 1) {
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case 0x0: //GATE_ON_count
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psxCounters[i].count += (u32)psxRcntRcount32(i); //Only counts when signal is on
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break;
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case 0x1: //GATE_ON_ClearStart
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if(psxCounters[i].mode & 0x10000000)psxRcntUpd32(i);
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psxCounters[i].mode &= ~0x10000000;
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break;
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case 0x2: //GATE_ON_Clear_OFF_Start
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psxCounters[i].mode &= ~0x10000000;
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psxRcntUpd32(i);
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break;
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case 0x3: //GATE_ON_Start
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break;
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default:
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SysPrintf("PCSX2 Warning: 32bit IOP Counter Gate Not Set!\n");
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break;
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}
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}
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}
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void psxCheckStartGate(int counter) { //Check Gate events when Vsync Starts
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int i = counter;
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if(counter < 3){ //Gates for 16bit counters
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if((psxCounters[i].mode & 0x1) == 0) return; //Ignore Gate
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SysPrintf("PSX Gate %x\n", i);
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switch((psxCounters[i].mode & 0x6) >> 1) {
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case 0x0: //GATE_ON_count
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psxRcntUpd32(i);
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psxCounters[i].mode |= 0x10000000;
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break;
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case 0x1: //GATE_ON_ClearStart
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if(psxCounters[i].mode & 0x10000000)psxRcntUpd16(i);
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psxCounters[i].mode &= ~0x10000000;
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break;
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case 0x2: //GATE_ON_Clear_OFF_Start
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psxRcntReset32(i);
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psxCounters[i].mode |= 0x10000000;
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break;
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case 0x3: //GATE_ON_Start
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psxCounters[i].mode &= ~0x10000000;
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break;
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default:
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SysPrintf("PCSX2 Warning: 16bit IOP Counter Gate Not Set!\n");
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break;
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}
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}
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if(counter >= 3){ //Gates for 32bit counters
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if((psxCounters[i].mode & 0x1) == 0) return; //Ignore Gate
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SysPrintf("PSX Gate %x\n", i);
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switch((psxCounters[i].mode & 0x6) >> 1) {
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case 0x0: //GATE_ON_count
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psxRcntUpd32(i);
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psxCounters[i].mode &= ~0x10000000;
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break;
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case 0x1: //GATE_ON_ClearStart
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if(psxCounters[i].mode & 0x10000000)psxRcntUpd32(i);
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psxCounters[i].mode &= ~0x10000000;
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break;
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case 0x2: //GATE_ON_Clear_OFF_Start
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psxRcntReset32(i);
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psxCounters[i].mode |= 0x10000000;
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break;
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case 0x3: //GATE_ON_Start
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psxCounters[i].mode &= ~0x10000000;
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break;
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default:
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SysPrintf("PCSX2 Warning: 32bit IOP Counter Gate Not Set!\n");
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break;
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}
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}
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}
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void _testRcnt16target(int i) {
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#ifdef PSXCNT_LOG
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PSXCNT_LOG("[%d] target 0x%x >= 0x%x (CycleT); count=0x%x, target=0x%x\n", i, (psxRegs.cycle - psxCounters[i].sCycleT), psxCounters[i].CycleT, psxRcntRcount16(i), psxCounters[i].target);
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#endif
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psxCounters[i].mode|= 0x0800; // Target flag
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if(psxCounters[i].mode & 0x80)
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if (psxCounters[i].mode & 0x10)psxCounters[i].mode&= ~0x0400; // Interrupt flag
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if (psxCounters[i].mode & 0x10) // Target interrupt
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psxHu32(0x1070)|= psxCounters[i].interrupt;
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if (psxCounters[i].mode & 0x08) { // Reset on target
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psxCounters[i].count = 0;
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psxRcntUpd16(i);
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return;
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}
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if(!(psxCounters[i].mode & 0x40))psxcntmask |= (1<<i);
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else psxcntmask &= ~(1<<i);
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}
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void _testRcnt16overflow(int i) {
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#ifdef PSXCNT_LOG
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PSXCNT_LOG("[%d] overflow 0x%x >= 0x%x (Cycle); Rcount=0x%x, count=0x%x\n", i, (psxRegs.cycle - psxCounters[i].sCycle) / psxCounters[i].rate, psxCounters[i].Cycle, psxRcntRcount16(i), psxCounters[i].count);
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#endif
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psxCounters[i].mode|= 0x1000; // Overflow flag
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if (psxCounters[i].mode & 0x0020) { // Overflow interrupt
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psxHu32(0x1070)|= psxCounters[i].interrupt;
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if(psxCounters[i].mode & 0x80)
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psxCounters[i].mode&= ~0x0400; // Interrupt flag
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}
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psxCounters[i].count = 0;
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psxcntmask &= ~(1<<i);
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psxRcntUpd16(i);
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}
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void _testRcnt32target(int i) {
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#ifdef PSXCNT_LOG
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PSXCNT_LOG("[%d] target 0x%x >= 0x%x (CycleT); count=0x%x, target=0x%x\n", i, (psxRegs.cycle - psxCounters[i].sCycleT), psxCounters[i].CycleT, psxRcntRcount32(i), psxCounters[i].target);
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#endif
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psxCounters[i].mode|= 0x0800; // Target flag
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if(psxCounters[i].mode & 0x80)
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if (psxCounters[i].mode & 0x10)psxCounters[i].mode&= ~0x0400; // Interrupt flag
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if (psxCounters[i].mode & 0x10) // Target interrupt
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psxHu32(0x1070)|= psxCounters[i].interrupt;
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if (psxCounters[i].mode & 0x8) { // Reset on target
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psxCounters[i].count = 0;
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psxRcntUpd32(i);
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return;
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}
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if(!(psxCounters[i].mode & 0x40))psxcntmask |= (1<<i);
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else psxcntmask &= ~(1<<i);
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}
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void _testRcnt32overflow(int i) {
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#ifdef PSXCNT_LOG
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PSXCNT_LOG("[%d] overflow 0x%x >= 0x%x (Cycle); Rcount=0x%x, count=0x%x\n", i, (psxRegs.cycle - psxCounters[i].sCycle), psxCounters[i].Cycle, psxRcntRcount32(i), psxCounters[i].count);
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#endif
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psxCounters[i].mode|= 0x1000; // Overflow flag
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if (psxCounters[i].mode & 0x0020) { // Overflow interrupt
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psxHu32(0x1070)|= psxCounters[i].interrupt;
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if(psxCounters[i].mode & 0x80)
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psxCounters[i].mode&= ~0x0400; // Interrupt flag
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}
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psxCounters[i].count = 0;
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psxcntmask &= ~(1<<i);
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psxRcntUpd32(i);
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}
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void _testRcnt16(int i) {
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if(!(psxHu32(0x1070) & psxCounters[i].interrupt)) {
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psxCounters[i].mode &= ~0x1800;
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psxCounters[i].mode |= 0x400;
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}
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if (!(psxcntmask & (1<<i)) && psxCounters[i].count >= psxCounters[i].target){
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_testRcnt16target(i);
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}
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if ((u32)psxRcntCycles(i) >= 0xffff)
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_testRcnt16overflow(i);
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}
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void _testRcnt32(int i) {
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if(!(psxHu32(0x1070) & psxCounters[i].interrupt)) {
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psxCounters[i].mode &= ~0x1800;
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psxCounters[i].mode |= 0x400;
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}
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if (!(psxcntmask & (1<<i)) && psxCounters[i].count >= psxCounters[i].target){
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_testRcnt32target(i);
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}
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if (psxRcntCycles(i) >= 0xfffee000)
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_testRcnt32overflow(i);
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}
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void psxRcntUpdate() {
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int i;
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for (i=0; i<=5; i++) {
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psxCounters[i].count += (psxRegs.cycle - psxCounters[i].sCycleT) / psxCounters[i].rate;
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psxCounters[i].sCycleT = psxRegs.cycle - (psxRegs.cycle % psxCounters[i].rate);
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}
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_testRcnt16(0);
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_testRcnt16(1);
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_testRcnt16(2);
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_testRcnt32(3);
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_testRcnt32(4);
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_testRcnt32(5);
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if (cnts >= 7 && (psxRegs.cycle - psxCounters[6].sCycleT) >= psxCounters[6].CycleT) {
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SPU2async(psxRegs.cycle - psxCounters[6].sCycleT);//(u32)(psxRegs.cycle - psxNextsCounter));
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psxCounters[6].sCycleT = psxRegs.cycle;
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}
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psxRcntSet();
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}
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void psxRcntWcount16(int index, u32 value) {
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#ifdef PSXCNT_LOG
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PSXCNT_LOG("writeCcount[%d] = %x\n", index, value);
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#endif
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SysPrintf("Write to 16bit count reg counter %x\n",index);
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psxCounters[index].count = value & 0xffff;
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SysPrintf("Counter %x count write %x\n", index, value);
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psxRcntUpd16(index);
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psxRcntSet();
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}
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void psxRcntWcount32(int index, u32 value) {
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#ifdef PSXCNT_LOG
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PSXCNT_LOG("writeCcount[%d] = %x\n", index, value);
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#endif
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SysPrintf("Write to 32bit count reg counter %x\n", index);
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psxCounters[index].count = value;
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SysPrintf("Counter %x count write %x\n", index, value);
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psxRcntUpd32(index);
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psxRcntSet();
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}
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void psxRcnt0Wmode(u32 value) {
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#ifdef PSXCNT_LOG
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//PSXCNT_LOG("IOP writeCmode[0] = %lx\n", value);
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#endif
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if (value & 0x1c00) {
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SysPrintf("Counter 0 Value write %x\n", value & 0x1c00);
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}
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psxCounters[0].mode = value;
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psxCounters[0].mode|= 0x0400;
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psxCounters[0].rate = 1;
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psxcntmask &= ~(1);
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if(value & 0x100) psxCounters[0].rate = PSXPIXEL;
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if(psxCounters[0].mode & 0x1){
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SysPrintf("Gate Check set on Counter 0\n");
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psxCounters[0].mode|= 0x1000000;
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psxhblankgate |= 1;
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}else
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psxhblankgate &= ~1;
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psxCounters[0].count = 0;
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psxRcntUpd16(0);
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psxRcntSet();
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//}
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}
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void psxRcnt1Wmode(u32 value) {
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#ifdef PSXCNT_LOG
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PSXCNT_LOG("IOP writeCmode[1] = %lx\n", value);
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#endif
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|
if (value & 0x1c00) {
|
|
SysPrintf("Counter 1 Value write %x\n", value & 0x1c00);
|
|
}
|
|
|
|
psxCounters[1].mode = value;
|
|
psxCounters[1].mode|= 0x0400;
|
|
psxCounters[1].rate = 1;
|
|
psxcntmask &= ~(1<<1);
|
|
if(value & 0x100)psxCounters[1].rate = PSXHBLANK;
|
|
|
|
if(psxCounters[1].mode & 0x1){
|
|
SysPrintf("Gate Check set on Counter 1\n");
|
|
psxCounters[1].mode|= 0x1000000;
|
|
psxvblankgate |= 1<<1;
|
|
}else
|
|
psxvblankgate &= ~(1<<1);
|
|
|
|
psxCounters[1].count = 0;
|
|
psxRcntUpd16(1);
|
|
psxRcntSet();
|
|
//}
|
|
}
|
|
|
|
void psxRcnt2Wmode(u32 value) {
|
|
#ifdef PSXCNT_LOG
|
|
PSXCNT_LOG("IOP writeCmode[2] = %lx\n", value);
|
|
#endif
|
|
if (value & 0x1c00) {
|
|
SysPrintf("Counter 2 Value write %x\n", value & 0x1c00);
|
|
}
|
|
|
|
psxcntmask &= ~(1<<2);
|
|
psxCounters[2].mode = value;
|
|
psxCounters[2].mode|= 0x0400;
|
|
|
|
switch(value & 0x200){
|
|
case 0x200:
|
|
psxCounters[2].rate = 8;
|
|
break;
|
|
case 0x000:
|
|
psxCounters[2].rate = 1;
|
|
break;
|
|
}
|
|
|
|
if((psxCounters[2].mode & 0x7) == 0x7 || (psxCounters[2].mode & 0x7) == 0x1){
|
|
SysPrintf("Gate set on IOP C2, disabling\n");
|
|
psxCounters[2].mode|= 0x1000000;
|
|
}
|
|
// Need to set a rate and target
|
|
psxCounters[2].count = 0;
|
|
psxRcntUpd16(2);
|
|
psxRcntSet();
|
|
}
|
|
|
|
void psxRcnt3Wmode(u32 value) {
|
|
#ifdef PSXCNT_LOG
|
|
PSXCNT_LOG("IOP writeCmode[3] = %lx\n", value);
|
|
#endif
|
|
if (value & 0x1c00) {
|
|
SysPrintf("Counter 3 Value write %x\n", value & 0x1c00);
|
|
}
|
|
|
|
psxcntmask &= ~(1<<3);
|
|
psxCounters[3].mode = value;
|
|
psxCounters[3].rate = 1;
|
|
psxCounters[3].mode|= 0x0400;
|
|
|
|
if(value & 0x100)psxCounters[3].rate = PSXHBLANK;
|
|
|
|
if(psxCounters[3].mode & 0x1){
|
|
SysPrintf("Gate Check set on Counter 3\n");
|
|
psxCounters[3].mode|= 0x1000000;
|
|
psxvblankgate |= 1<<3;
|
|
}else
|
|
psxvblankgate &= ~(1<<3);
|
|
|
|
psxCounters[3].count = 0;
|
|
psxRcntUpd32(3);
|
|
psxRcntSet();
|
|
//}
|
|
}
|
|
|
|
void psxRcnt4Wmode(u32 value) {
|
|
#ifdef PSXCNT_LOG
|
|
PSXCNT_LOG("IOP writeCmode[4] = %lx\n", value);
|
|
#endif
|
|
if (value & 0x1c00) {
|
|
SysPrintf("Counter 4 Value write %x\n", value & 0x1c00);
|
|
}
|
|
|
|
psxcntmask &= ~(1<<4);
|
|
psxCounters[4].mode = value;
|
|
psxCounters[4].mode|= 0x0400;
|
|
|
|
switch(value & 0x6000){
|
|
case 0x0000:
|
|
psxCounters[4].rate = 1;
|
|
break;
|
|
case 0x2000:
|
|
psxCounters[4].rate = 8;
|
|
break;
|
|
case 0x4000:
|
|
psxCounters[4].rate = 16;
|
|
break;
|
|
case 0x6000:
|
|
psxCounters[4].rate = 256;
|
|
break;
|
|
}
|
|
// Need to set a rate and target
|
|
if((psxCounters[4].mode & 0x7) == 0x7 || (psxCounters[4].mode & 0x7) == 0x1){
|
|
SysPrintf("Gate set on IOP C4, disabling\n");
|
|
psxCounters[4].mode|= 0x1000000;
|
|
}
|
|
psxCounters[4].count = 0;
|
|
psxRcntUpd32(4);
|
|
psxRcntSet();
|
|
}
|
|
|
|
void psxRcnt5Wmode(u32 value) {
|
|
#ifdef PSXCNT_LOG
|
|
PSXCNT_LOG("IOP writeCmode[5] = %lx\n", value);
|
|
#endif
|
|
if (value & 0x1c00) {
|
|
SysPrintf("Counter 5 Value write %x\n", value & 0x1c00);
|
|
}
|
|
psxcntmask &= ~(1<<5);
|
|
psxCounters[5].mode = value;
|
|
psxCounters[5].mode|= 0x0400;
|
|
|
|
switch(value & 0x6000){
|
|
case 0x0000:
|
|
psxCounters[5].rate = 1;
|
|
break;
|
|
case 0x2000:
|
|
psxCounters[5].rate = 8;
|
|
break;
|
|
case 0x4000:
|
|
psxCounters[5].rate = 16;
|
|
break;
|
|
case 0x6000:
|
|
psxCounters[5].rate = 256;
|
|
break;
|
|
}
|
|
// Need to set a rate and target
|
|
if((psxCounters[5].mode & 0x7) == 0x7 || (psxCounters[5].mode & 0x7) == 0x1){
|
|
SysPrintf("Gate set on IOP C5, disabling\n");
|
|
psxCounters[5].mode|= 0x1000000;
|
|
}
|
|
psxCounters[5].count = 0;
|
|
psxRcntUpd32(5);
|
|
psxRcntSet();
|
|
}
|
|
|
|
void psxRcntWtarget16(int index, u32 value) {
|
|
//if(psxCounters[index].sCycleT > psxRegs.cycle) ReSyncTarget(index);
|
|
#ifdef PSXCNT_LOG
|
|
PSXCNT_LOG("writeCtarget16[%ld] = %lx\n", index, value);
|
|
#endif
|
|
psxCounters[index].target = value & 0xffff;
|
|
psxRcntSet();
|
|
}
|
|
|
|
void psxRcntWtarget32(int index, u32 value) {
|
|
//if(psxCounters[index].sCycleT > psxRegs.cycle) ReSyncTarget(index);
|
|
psxCounters[index].target = value;
|
|
|
|
#ifdef PSXCNT_LOG
|
|
PSXCNT_LOG("writeCtarget32[%ld] = %lx (count=%lx) ; sCycleT: %x CycleT: %x\n",
|
|
index, value, psxRcntRcount32(index), psxCounters[index].sCycleT, psxCounters[index].CycleT);
|
|
#endif
|
|
//if(index == 5) SysPrintf("Counter 5 tar set CT %x, Tar %x, mode %x, psx.cycle %x\n", psxCounters[index].CycleT + psxCounters[index].sCycleT, psxCounters[index].target, psxCounters[index].mode, psxRegs.cycle);
|
|
psxRcntSet();
|
|
}
|
|
|
|
u16 psxRcntRcount16(int index) {
|
|
if(psxCounters[index].mode & 0x1000000) return psxCounters[index].count;
|
|
return (u16)(psxCounters[index].count + (psxRegs.cycle - psxCounters[index].sCycleT) / psxCounters[index].rate);
|
|
}
|
|
|
|
u32 psxRcntRcount32(int index) {
|
|
if(psxCounters[index].mode & 0x1000000) return psxCounters[index].count;
|
|
return (u32)(psxCounters[index].count + (psxRegs.cycle - psxCounters[index].sCycleT) / psxCounters[index].rate);
|
|
}
|
|
|
|
u64 psxRcntCycles(int index) {
|
|
if(psxCounters[index].mode & 0x1000000) return psxCounters[index].count;
|
|
return (u64)(psxCounters[index].count + (psxRegs.cycle - psxCounters[index].sCycleT) / psxCounters[index].rate);
|
|
}
|
|
|
|
int psxRcntFreeze(gzFile f, int Mode) {
|
|
gzfreezel(psxCounters);
|
|
|
|
return 0;
|
|
}
|