mirror of
https://github.com/PCSX2/pcsx2.git
synced 2025-04-02 10:52:54 -04:00
638e0b30f6
git-svn-id: http://pcsx2.googlecode.com/svn/branches/pcsx2_0.9.1@159 96395faa-99c1-11dd-bbfe-3dabce05a288
761 lines
18 KiB
C
761 lines
18 KiB
C
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2003 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdlib.h>
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#include <string.h>
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#include <assert.h>
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#include "Common.h"
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#include "InterTables.h"
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#include "ix86/ix86.h"
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#include "iR5900.h"
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#ifdef __WIN32__
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#pragma warning(disable:4244)
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#pragma warning(disable:4761)
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#endif
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/*********************************************************
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* Shift arithmetic with constant shift *
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* Format: OP rd, rt, sa *
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*********************************************************/
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#ifndef SHIFT_RECOMPILE
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REC_FUNC(SLL);
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REC_FUNC(SRL);
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REC_FUNC(SRA);
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REC_FUNC(DSLL);
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REC_FUNC(DSRL);
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REC_FUNC(DSRA);
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REC_FUNC(DSLL32);
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REC_FUNC(DSRL32);
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REC_FUNC(DSRA32);
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REC_FUNC(SLLV);
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REC_FUNC(SRLV);
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REC_FUNC(SRAV);
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REC_FUNC(DSLLV);
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REC_FUNC(DSRLV);
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REC_FUNC(DSRAV);
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#else
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////////////////////////////////////////////////////
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void recDSRA( void ) {
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int rdreg;
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int rtreg;
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if (!_Rd_) return;
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#ifdef ENABLE_REGCACHING
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if (_Rd_ == _Rt_) {
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
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SAR64ItoR(rdreg, _Sa_);
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} else {
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_addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
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MOV64RtoR(rdreg, rtreg);
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if (_Sa_) {
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SAR64ItoR(rdreg, _Sa_);
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}
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}
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_clearNeededX86regs();
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#else
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MOV64MtoR( RAX, (u64)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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if ( _Sa_ != 0 ) {
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SAR64ItoR( RAX, _Sa_ );
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}
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MOV64RtoM( (u64)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], RAX );
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#endif
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}
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////////////////////////////////////////////////////
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void recDSRA32(void) {
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int rdreg;
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int rtreg;
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if (!_Rd_) return;
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#ifdef ENABLE_REGCACHING
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if (_Rd_ == _Rt_) {
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
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SAR64ItoR(rdreg, _Sa_ + 32);
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} else {
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_addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
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MOV64RtoR(rdreg, rtreg);
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SAR64ItoR(rdreg, _Sa_ + 32);
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}
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_clearNeededX86regs();
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#else
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MOV64MtoR( RAX, (u64)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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SAR64ItoR( RAX, _Sa_ + 32 );
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MOV64RtoM( (u64)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], RAX );
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#endif
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}
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////////////////////////////////////////////////////
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void recSLL(void) {
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int rdreg;
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int rtreg;
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if (!_Rd_) return;
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#ifdef ENABLE_REGCACHING
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if (_Rd_ == _Rt_) {
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
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SHL64ItoR(rdreg, _Sa_ + 32);
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SAR64ItoR(rdreg, 32);
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} else {
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_addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
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MOV32RtoR(rdreg, rtreg);
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SHL64ItoR(rdreg, _Sa_ + 32);
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SAR64ItoR(rdreg, 32);
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}
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_clearNeededX86regs();
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#else
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MOV32MtoR(EAX, (u32)&cpuRegs.GPR.r[_Rt_].UL[0]);
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if (_Sa_ != 0) {
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SHL32ItoR(EAX, _Sa_);
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}
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CDQ();
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MOV32RtoM((u32)&cpuRegs.GPR.r[_Rd_].UL[0], EAX);
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MOV32RtoM((u32)&cpuRegs.GPR.r[_Rd_].UL[1], EDX);
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#endif
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}
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////////////////////////////////////////////////////
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void recSRL(void) {
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int rdreg;
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int rtreg;
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if (!_Rd_) return;
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#ifdef ENABLE_REGCACHING
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if (_Rd_ == _Rt_) {
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
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SHR32ItoR(rdreg, _Sa_);
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SHL64ItoR(rdreg, 32);
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SAR64ItoR(rdreg, 32);
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} else {
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_addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
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MOV32RtoR(rdreg, rtreg);
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if (_Sa_) {
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SHR32ItoR(rdreg, _Sa_);
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}
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SHL64ItoR(rdreg, 32);
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SAR64ItoR(rdreg, 32);
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}
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_clearNeededX86regs();
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#else
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MOV32MtoR( EAX, (u32)&cpuRegs.GPR.r[_Rt_].UL[0]);
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if (_Sa_ != 0) {
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SHR32ItoR(EAX, _Sa_);
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}
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CDQ();
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MOV32RtoM((u32)&cpuRegs.GPR.r[_Rd_].UL[0], EAX);
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MOV32RtoM((u32)&cpuRegs.GPR.r[_Rd_].UL[1], EDX);
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#endif
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}
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////////////////////////////////////////////////////
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void recSRA(void) {
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int rdreg;
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int rtreg;
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if (!_Rd_) return;
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#ifdef ENABLE_REGCACHING
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if (_Rd_ == _Rt_) {
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
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SAR32ItoR(rdreg, _Sa_);
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SHL64ItoR(rdreg, 32);
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SAR64ItoR(rdreg, 32);
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} else {
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_addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
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MOV32RtoR(rdreg, rtreg);
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if (_Sa_) {
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SAR32ItoR(rdreg, _Sa_);
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}
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SHL64ItoR(rdreg, 32);
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SAR64ItoR(rdreg, 32);
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}
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_clearNeededX86regs();
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#else
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MOV32MtoR( EAX, (u32)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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if ( _Sa_ != 0 ) {
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SAR32ItoR( EAX, _Sa_);
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}
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CDQ();
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MOV32RtoM( (u32)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
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MOV32RtoM( (u32)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
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#endif
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}
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////////////////////////////////////////////////////
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void recDSLL(void) {
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int rdreg;
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int rtreg;
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if (!_Rd_) return;
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#ifdef ENABLE_REGCACHING
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if (_Rd_ == _Rt_) {
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
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SHL64ItoR(rdreg, _Sa_);
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} else {
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_addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
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MOV64RtoR(rdreg, rtreg);
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if (_Sa_) {
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SHL64ItoR(rdreg, _Sa_);
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}
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}
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_clearNeededX86regs();
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#else
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MOV64MtoR( RAX, (u64)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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if ( _Sa_ != 0 ) {
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SHL64ItoR( RAX, _Sa_ );
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}
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MOV64RtoM( (u64)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], RAX );
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#endif
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}
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////////////////////////////////////////////////////
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void recDSRL( void ) {
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int rdreg;
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int rtreg;
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if (!_Rd_) return;
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#ifdef ENABLE_REGCACHING
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if (_Rd_ == _Rt_) {
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
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SHR64ItoR(rdreg, _Sa_);
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} else {
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_addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
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MOV64RtoR(rdreg, rtreg);
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if (_Sa_) {
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SHR64ItoR(rdreg, _Sa_);
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}
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}
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_clearNeededX86regs();
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#else
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MOV64MtoR( RAX, (u64)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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if ( _Sa_ != 0 ) {
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SHR64ItoR( RAX, _Sa_ );
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}
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MOV64RtoM( (u64)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], RAX );
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#endif
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}
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////////////////////////////////////////////////////
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void recDSLL32(void) {
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int rdreg;
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int rtreg;
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if (!_Rd_) return;
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#ifdef ENABLE_REGCACHING
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if (_Rd_ == _Rt_) {
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
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SHL64ItoR(rdreg, _Sa_ + 32);
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} else {
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_addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
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MOV64RtoR(rdreg, rtreg);
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SHL64ItoR(rdreg, _Sa_ + 32);
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}
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_clearNeededX86regs();
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#else
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MOV64MtoR( RAX, (u64)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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SHL64ItoR( RAX, _Sa_ + 32 );
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MOV64RtoM( (u64)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], RAX );
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#endif
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}
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////////////////////////////////////////////////////
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void recDSRL32( void ) {
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int rdreg;
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int rtreg;
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if (!_Rd_) return;
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#ifdef ENABLE_REGCACHING
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if (_Rd_ == _Rt_) {
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
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SHR64ItoR(rdreg, _Sa_ + 32);
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} else {
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_addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
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MOV64RtoR(rdreg, rtreg);
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SHR64ItoR(rdreg, _Sa_ + 32);
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}
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_clearNeededX86regs();
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#else
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MOV64MtoR( RAX, (u64)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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SHR64ItoR( RAX, _Sa_ + 32 );
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MOV64RtoM( (u64)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], RAX );
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#endif
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}
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/*********************************************************
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* Shift arithmetic with variant register shift *
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* Format: OP rd, rt, rs *
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*********************************************************/
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////////////////////////////////////////////////////
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void recSLLV( void ) {
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int rdreg;
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int rsreg;
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int rtreg;
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int clreg;
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if (!_Rd_) return;
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#ifdef ENABLE_REGCACHING
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clreg = _allocTempX86reg(ECX);
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if (_Rd_ == _Rs_) {
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_addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
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MOV32RtoR(clreg, rdreg);
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MOV32RtoR(rdreg, rtreg);
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AND32ItoR(clreg, 0x1f);
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SHL32CLtoR(rdreg);
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SHL64ItoR(rdreg, 32);
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SAR64ItoR(rdreg, 32);
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} else
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if (_Rd_ == _Rt_) {
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_addNeededGPRtoX86reg(_Rs_);
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_addNeededGPRtoX86reg(_Rd_);
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rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
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MOV32RtoR(clreg, rsreg);
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AND32ItoR(clreg, 0x1f);
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SHL32CLtoR(rdreg);
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SHL64ItoR(rdreg, 32);
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SAR64ItoR(rdreg, 32);
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} else {
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_addNeededGPRtoX86reg(_Rs_); _addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
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MOV32RtoR(clreg, rsreg);
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MOV32RtoR(rdreg, rtreg);
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AND32ItoR(clreg, 0x1f);
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SHL32CLtoR(rdreg);
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SHL64ItoR(rdreg, 32);
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SAR64ItoR(rdreg, 32);
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}
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_freeX86reg(clreg);
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_clearNeededX86regs();
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#else
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MOV32MtoR( EAX, (u32)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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if ( _Rs_ != 0 ) {
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MOV32MtoR( ECX, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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AND32ItoR( ECX, 0x1f );
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SHL32CLtoR( EAX );
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}
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CDQ();
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MOV32RtoM( (u32)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
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MOV32RtoM( (u32)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
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#endif
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}
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////////////////////////////////////////////////////
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void recSRLV( void ) {
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int rdreg;
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int rsreg;
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int rtreg;
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int clreg;
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if (!_Rd_) return;
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#ifdef ENABLE_REGCACHING
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clreg = _allocTempX86reg(ECX);
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if (_Rd_ == _Rs_) {
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_addNeededGPRtoX86reg(_Rt_);
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_addNeededGPRtoX86reg(_Rd_);
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rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
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MOV32RtoR(clreg, rdreg);
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MOV32RtoR(rdreg, rtreg);
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AND32ItoR(clreg, 0x1f);
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SHR32CLtoR(rdreg);
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SHL64ItoR(rdreg, 32);
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SAR64ItoR(rdreg, 32);
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} else
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if (_Rd_ == _Rt_) {
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_addNeededGPRtoX86reg(_Rs_);
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_addNeededGPRtoX86reg(_Rd_);
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rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
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rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
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MOV32RtoR(clreg, rsreg);
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AND32ItoR(clreg, 0x1f);
|
|
SHR32CLtoR(rdreg);
|
|
SHL64ItoR(rdreg, 32);
|
|
SAR64ItoR(rdreg, 32);
|
|
} else {
|
|
_addNeededGPRtoX86reg(_Rs_); _addNeededGPRtoX86reg(_Rt_);
|
|
_addNeededGPRtoX86reg(_Rd_);
|
|
rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
|
|
rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
|
|
rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
|
|
|
|
MOV32RtoR(clreg, rsreg);
|
|
MOV32RtoR(rdreg, rtreg);
|
|
AND32ItoR(clreg, 0x1f);
|
|
SHR32CLtoR(rdreg);
|
|
SHL64ItoR(rdreg, 32);
|
|
SAR64ItoR(rdreg, 32);
|
|
}
|
|
|
|
_freeX86reg(clreg);
|
|
_clearNeededX86regs();
|
|
#else
|
|
MOV32MtoR( EAX, (u32)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
if ( _Rs_ != 0 )
|
|
{
|
|
MOV32MtoR( ECX, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
AND32ItoR( ECX, 0x1f );
|
|
SHR32CLtoR( EAX );
|
|
}
|
|
CDQ( );
|
|
MOV32RtoM( (u32)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
MOV32RtoM( (u32)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
|
#endif
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recSRAV( void ) {
|
|
int rdreg;
|
|
int rsreg;
|
|
int rtreg;
|
|
int clreg;
|
|
|
|
if (!_Rd_) return;
|
|
|
|
#ifdef ENABLE_REGCACHING
|
|
|
|
clreg = _allocTempX86reg(ECX);
|
|
if (_Rd_ == _Rs_) {
|
|
_addNeededGPRtoX86reg(_Rt_);
|
|
_addNeededGPRtoX86reg(_Rd_);
|
|
rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
|
|
rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
|
|
|
|
MOV32RtoR(clreg, rdreg);
|
|
MOV32RtoR(rdreg, rtreg);
|
|
AND32ItoR(clreg, 0x1f);
|
|
SAR32CLtoR(rdreg);
|
|
SHL64ItoR(rdreg, 32);
|
|
SAR64ItoR(rdreg, 32);
|
|
} else
|
|
if (_Rd_ == _Rt_) {
|
|
_addNeededGPRtoX86reg(_Rs_);
|
|
_addNeededGPRtoX86reg(_Rd_);
|
|
rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
|
|
rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
|
|
|
|
MOV32RtoR(clreg, rsreg);
|
|
AND32ItoR(clreg, 0x1f);
|
|
SAR32CLtoR(rdreg);
|
|
SHL64ItoR(rdreg, 32);
|
|
SAR64ItoR(rdreg, 32);
|
|
} else {
|
|
_addNeededGPRtoX86reg(_Rs_); _addNeededGPRtoX86reg(_Rt_);
|
|
_addNeededGPRtoX86reg(_Rd_);
|
|
rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
|
|
rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
|
|
rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
|
|
|
|
MOV32RtoR(clreg, rsreg);
|
|
MOV32RtoR(rdreg, rtreg);
|
|
AND32ItoR(clreg, 0x1f);
|
|
SAR32CLtoR(rdreg);
|
|
SHL64ItoR(rdreg, 32);
|
|
SAR64ItoR(rdreg, 32);
|
|
}
|
|
|
|
_freeX86reg(clreg);
|
|
_clearNeededX86regs();
|
|
#else
|
|
MOV32MtoR( EAX, (u32)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
if ( _Rs_ != 0 )
|
|
{
|
|
MOV32MtoR( ECX, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
AND32ItoR( ECX, 0x1f );
|
|
SAR32CLtoR( EAX );
|
|
}
|
|
CDQ( );
|
|
MOV32RtoM( (u32)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
MOV32RtoM( (u32)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
|
#endif
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recDSLLV( void ) {
|
|
int rdreg;
|
|
int rsreg;
|
|
int rtreg;
|
|
int clreg;
|
|
|
|
if (!_Rd_) return;
|
|
|
|
#ifdef ENABLE_REGCACHING
|
|
|
|
clreg = _allocTempX86reg(ECX);
|
|
if (_Rd_ == _Rs_) {
|
|
_addNeededGPRtoX86reg(_Rt_);
|
|
_addNeededGPRtoX86reg(_Rd_);
|
|
rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
|
|
rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
|
|
|
|
MOV32RtoR(clreg, rdreg);
|
|
MOV64RtoR(rdreg, rtreg);
|
|
AND32ItoR(clreg, 0x1f);
|
|
SHL64CLtoR(rdreg);
|
|
} else
|
|
if (_Rd_ == _Rt_) {
|
|
_addNeededGPRtoX86reg(_Rs_);
|
|
_addNeededGPRtoX86reg(_Rd_);
|
|
rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
|
|
rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
|
|
|
|
MOV32RtoR(clreg, rsreg);
|
|
AND32ItoR(clreg, 0x1f);
|
|
SHL64CLtoR(rdreg);
|
|
} else {
|
|
_addNeededGPRtoX86reg(_Rs_); _addNeededGPRtoX86reg(_Rt_);
|
|
_addNeededGPRtoX86reg(_Rd_);
|
|
rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
|
|
rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
|
|
rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
|
|
|
|
MOV32RtoR(clreg, rsreg);
|
|
MOV64RtoR(rdreg, rtreg);
|
|
AND32ItoR(clreg, 0x1f);
|
|
SHL64CLtoR(rdreg);
|
|
}
|
|
|
|
_freeX86reg(clreg);
|
|
_clearNeededX86regs();
|
|
#else
|
|
MOV64MtoR( RAX, (u64)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
if ( _Rs_ != 0 )
|
|
{
|
|
MOV32MtoR( ECX, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
AND32ItoR( ECX, 0x3f );
|
|
SHL64CLtoR( RAX );
|
|
}
|
|
MOV64RtoM( (u64)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], RAX );
|
|
#endif
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recDSRLV( void ) {
|
|
int rdreg;
|
|
int rsreg;
|
|
int rtreg;
|
|
int clreg;
|
|
|
|
if (!_Rd_) return;
|
|
|
|
#ifdef ENABLE_REGCACHING
|
|
|
|
clreg = _allocTempX86reg(ECX);
|
|
if (_Rd_ == _Rs_) {
|
|
_addNeededGPRtoX86reg(_Rt_);
|
|
_addNeededGPRtoX86reg(_Rd_);
|
|
rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
|
|
rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
|
|
|
|
MOV32RtoR(clreg, rdreg);
|
|
MOV64RtoR(rdreg, rtreg);
|
|
AND32ItoR(clreg, 0x1f);
|
|
SHR64CLtoR(rdreg);
|
|
} else
|
|
if (_Rd_ == _Rt_) {
|
|
_addNeededGPRtoX86reg(_Rs_);
|
|
_addNeededGPRtoX86reg(_Rd_);
|
|
rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
|
|
rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
|
|
|
|
MOV32RtoR(clreg, rsreg);
|
|
AND32ItoR(clreg, 0x1f);
|
|
SHR64CLtoR(rdreg);
|
|
} else {
|
|
_addNeededGPRtoX86reg(_Rs_); _addNeededGPRtoX86reg(_Rt_);
|
|
_addNeededGPRtoX86reg(_Rd_);
|
|
rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
|
|
rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
|
|
rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
|
|
|
|
MOV32RtoR(clreg, rsreg);
|
|
MOV64RtoR(rdreg, rtreg);
|
|
AND32ItoR(clreg, 0x1f);
|
|
SHR64CLtoR(rdreg);
|
|
}
|
|
|
|
_freeX86reg(clreg);
|
|
_clearNeededX86regs();
|
|
#else
|
|
MOV64MtoR( RAX, (u64)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
if ( _Rs_ != 0 )
|
|
{
|
|
MOV32MtoR( ECX, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
AND32ItoR( ECX, 0x3f );
|
|
SHR64CLtoR( RAX );
|
|
}
|
|
MOV64RtoM( (u64)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], RAX );
|
|
#endif
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recDSRAV( void ) {
|
|
int rdreg;
|
|
int rsreg;
|
|
int rtreg;
|
|
int clreg;
|
|
|
|
if (!_Rd_) return;
|
|
|
|
#ifdef ENABLE_REGCACHING
|
|
|
|
clreg = _allocTempX86reg(ECX);
|
|
if (_Rd_ == _Rs_) {
|
|
_addNeededGPRtoX86reg(_Rt_);
|
|
_addNeededGPRtoX86reg(_Rd_);
|
|
rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
|
|
rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
|
|
|
|
MOV32RtoR(clreg, rdreg);
|
|
MOV64RtoR(rdreg, rtreg);
|
|
AND32ItoR(clreg, 0x1f);
|
|
SAR64CLtoR(rdreg);
|
|
} else
|
|
if (_Rd_ == _Rt_) {
|
|
_addNeededGPRtoX86reg(_Rs_);
|
|
_addNeededGPRtoX86reg(_Rd_);
|
|
rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
|
|
rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE | MODE_READ);
|
|
|
|
MOV32RtoR(clreg, rsreg);
|
|
AND32ItoR(clreg, 0x1f);
|
|
SAR64CLtoR(rdreg);
|
|
} else {
|
|
_addNeededGPRtoX86reg(_Rs_); _addNeededGPRtoX86reg(_Rt_);
|
|
_addNeededGPRtoX86reg(_Rd_);
|
|
rsreg = _allocGPRtoX86reg(-1, _Rs_, MODE_READ);
|
|
rtreg = _allocGPRtoX86reg(-1, _Rt_, MODE_READ);
|
|
rdreg = _allocGPRtoX86reg(-1, _Rd_, MODE_WRITE);
|
|
|
|
MOV32RtoR(clreg, rsreg);
|
|
MOV64RtoR(rdreg, rtreg);
|
|
AND32ItoR(clreg, 0x1f);
|
|
SAR64CLtoR(rdreg);
|
|
}
|
|
|
|
_freeX86reg(clreg);
|
|
_clearNeededX86regs();
|
|
#else
|
|
MOV64MtoR( RAX, (u64)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
if ( _Rs_ != 0 )
|
|
{
|
|
MOV32MtoR( ECX, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
AND32ItoR( ECX, 0x3f );
|
|
SAR64CLtoR( RAX );
|
|
}
|
|
MOV64RtoM( (u64)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], RAX );
|
|
#endif
|
|
}
|
|
|
|
#endif
|
|
|