mirror of
https://github.com/PCSX2/pcsx2.git
synced 2025-04-02 10:52:54 -04:00
638e0b30f6
git-svn-id: http://pcsx2.googlecode.com/svn/branches/pcsx2_0.9.1@159 96395faa-99c1-11dd-bbfe-3dabce05a288
341 lines
8.5 KiB
C
341 lines
8.5 KiB
C
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2003 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdlib.h>
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#include <string.h>
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#include <assert.h>
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#include "Common.h"
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#include "InterTables.h"
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#include "ix86/ix86.h"
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#include "iR5900.h"
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#ifdef __WIN32__
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#pragma warning(disable:4244)
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#pragma warning(disable:4761)
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#endif
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/*********************************************************
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* Register branch logic *
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* Format: OP rs, rt, offset *
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*********************************************************/
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#ifndef BRANCH_RECOMPILE
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REC_SYS(BEQ);
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REC_SYS(BEQL);
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REC_SYS(BNE);
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REC_SYS(BNEL);
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REC_SYS(BLTZ);
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REC_SYS(BGTZ);
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REC_SYS(BLEZ);
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REC_SYS(BGEZ);
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REC_SYS(BGTZL);
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REC_SYS(BLTZL);
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REC_SYS(BLTZAL);
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REC_SYS(BLTZALL);
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REC_SYS(BLEZL);
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REC_SYS(BGEZL);
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REC_SYS(BGEZAL);
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REC_SYS(BGEZALL);
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#else
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////////////////////////////////////////////////////
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void recBEQ( void )
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{
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if ( _Rs_ == _Rt_ )
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{
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SetBranchImm( _Imm_ * 4 + pc/*, 1*/ );
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}
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else
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{
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u32 branchTo = _Imm_ * 4 + pc;
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// SetFPUstate();
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MOV64MtoR( EAX, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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CMP64MtoR( EAX, (u32)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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j8Ptr[ 0 ] = JNE8( 0 );
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MOV32ItoM( (u32)&target, branchTo );
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j8Ptr[ 2 ] = JMP8( 0 );
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x86SetJ8( j8Ptr[ 0 ] );
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MOV32ItoM( (u32)&target, pc + 4 );
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x86SetJ8( j8Ptr[ 2 ] );
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SetBranch( );
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}
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}
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////////////////////////////////////////////////////
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void recBNE( void )
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{
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u32 branchTo = _Imm_ * 4 + pc;
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if ( _Rs_ == _Rt_ )
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{
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return;
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}
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// SetFPUstate();
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MOV64MtoR( EAX, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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CMP64MtoR( EAX, (u32)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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j8Ptr[ 0 ] = JE8( 0 );
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MOV32ItoM( (u32)&target, branchTo );
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j8Ptr[ 2 ] = JMP8( 0 );
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x86SetJ8( j8Ptr[ 0 ] );
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MOV32ItoM( (u32)&target, pc + 4 );
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x86SetJ8( j8Ptr[ 2 ] );
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SetBranch( );
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}
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/*********************************************************
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* Register branch logic *
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* Format: OP rs, offset *
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*********************************************************/
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//#if 0
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////////////////////////////////////////////////////
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void recBLTZAL( void )
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{
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MOV32ItoM( (u32)&cpuRegs.code, cpuRegs.code );
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MOV32ItoM( (u32)&cpuRegs.pc, pc );
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iFlushCall();
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CALLFunc( (u32)BLTZAL );
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branch = 2;
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}
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////////////////////////////////////////////////////
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void recBGEZAL( void )
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{
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MOV32ItoM( (u32)&cpuRegs.code, cpuRegs.code );
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MOV32ItoM( (u32)&cpuRegs.pc, pc );
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iFlushCall();
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CALLFunc( (u32)BGEZAL );
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branch = 2;
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}
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////////////////////////////////////////////////////
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void recBLEZ( void )
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{
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u32 branchTo = _Imm_ * 4 + pc;
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CMP32ItoM( (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], 0 );
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j8Ptr[ 0 ] = JL8( 0 );
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j8Ptr[ 1 ] = JG8( 0 );
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CMP32ItoM( (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], 0 );
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j8Ptr[ 2 ] = JNZ8( 0 );
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x86SetJ8( j8Ptr[ 0 ] );
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MOV32ItoM( (u32)&target, branchTo );
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j8Ptr[ 3 ] = JMP8( 0 );
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x86SetJ8( j8Ptr[ 1 ] );
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x86SetJ8( j8Ptr[ 2 ] );
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MOV32ItoM( (u32)&target, pc + 4 );
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x86SetJ8( j8Ptr[ 3 ] );
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SetBranch( );
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}
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////////////////////////////////////////////////////
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void recBGTZ( void )
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{
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u32 branchTo = _Imm_ * 4 + pc;
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CMP32ItoM( (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], 0 );
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j8Ptr[ 0 ] = JG8( 0 );
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j8Ptr[ 1 ] = JL8( 0 );
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CMP32ItoM( (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], 0 );
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j8Ptr[ 2 ] = JZ8( 0 );
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x86SetJ8( j8Ptr[ 0 ] );
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MOV32ItoM( (u32)&target, branchTo );
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j8Ptr[ 3 ] = JMP8( 0 );
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x86SetJ8( j8Ptr[ 1 ] );
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x86SetJ8( j8Ptr[ 2 ] );
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MOV32ItoM( (u32)&target, pc + 4 );
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x86SetJ8( j8Ptr[ 3 ] );
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SetBranch( );
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}
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////////////////////////////////////////////////////
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void recBLTZ( void )
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{
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u32 branchTo = _Imm_ * 4 + pc;
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CMP32ItoM( (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], 0 );
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j8Ptr[ 0 ] = JGE8( 0 );
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MOV32ItoM( (u32)&target, branchTo );
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j8Ptr[ 1 ] = JMP8( 0 );
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x86SetJ8( j8Ptr[ 0 ] );
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MOV32ItoM( (u32)&target, pc + 4 );
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x86SetJ8( j8Ptr[ 1 ] );
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SetBranch( );
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}
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////////////////////////////////////////////////////
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void recBGEZ( void )
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{
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u32 branchTo = _Imm_ * 4 + pc;
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CMP32ItoM( (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], 0 );
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j8Ptr[ 0 ] = JL8( 0 );
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MOV32ItoM( (u32)&target, branchTo );
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j8Ptr[ 1 ] = JMP8( 0 );
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x86SetJ8( j8Ptr[ 0 ] );
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MOV32ItoM( (u32)&target, pc + 4 );
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x86SetJ8( j8Ptr[ 1 ] );
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SetBranch( );
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}
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/*********************************************************
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* Register branch logic Likely *
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* Format: OP rs, offset *
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*********************************************************/
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////////////////////////////////////////////////////
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void recBLEZL( void )
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{
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MOV32ItoM( (u32)&cpuRegs.code, cpuRegs.code );
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MOV32ItoM( (u32)&cpuRegs.pc, pc );
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iFlushCall();
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CALLFunc( (u32)BLEZL );
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branch = 2;
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}
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////////////////////////////////////////////////////
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void recBGTZL( void )
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{
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MOV32ItoM( (u32)&cpuRegs.code, cpuRegs.code );
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MOV32ItoM( (u32)&cpuRegs.pc, pc );
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iFlushCall();
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CALLFunc( (u32)BGTZL );
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branch = 2;
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}
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////////////////////////////////////////////////////
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void recBLTZL( void )
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{
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MOV32ItoM( (u32)&cpuRegs.code, cpuRegs.code );
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MOV32ItoM( (u32)&cpuRegs.pc, pc );
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iFlushCall();
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CALLFunc( (u32)BLTZL );
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branch = 2;
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}
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////////////////////////////////////////////////////
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void recBLTZALL( void )
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{
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MOV32ItoM( (u32)&cpuRegs.code, cpuRegs.code );
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MOV32ItoM( (u32)&cpuRegs.pc, pc );
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iFlushCall();
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CALLFunc( (u32)BLTZALL );
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branch = 2;
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}
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////////////////////////////////////////////////////
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void recBGEZALL( void )
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{
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MOV32ItoM( (u32)&cpuRegs.code, cpuRegs.code );
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MOV32ItoM( (u32)&cpuRegs.pc, pc );
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iFlushCall();
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CALLFunc( (u32)BGEZALL );
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branch = 2;
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}
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////////////////////////////////////////////////////
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void recBEQL( void )
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{
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MOV32MtoR( ECX, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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MOV32MtoR( EDX, (u32)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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CMP32RtoR( ECX, EDX );
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j8Ptr[ 0 ] = JNE8( 0 );
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MOV32MtoR( ECX, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
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MOV32MtoR( EDX, (u32)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
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CMP32RtoR( ECX, EDX );
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j8Ptr[ 1 ] = JNE8( 0 );
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MOV32ItoM( (u32)&target, _Imm_ * 4 + pc );
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j8Ptr[ 2 ] = JMP8( 0 );
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x86SetJ8( j8Ptr[ 0 ] );
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x86SetJ8( j8Ptr[ 1 ] );
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MOV32ItoM( (u32)&cpuRegs.pc, pc + 4 );
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iRet( TRUE );
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x86SetJ8( j8Ptr[ 2 ] );
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SetBranch( );
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}
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////////////////////////////////////////////////////
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void recBNEL( void )
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{
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MOV32MtoR( ECX, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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MOV32MtoR( EDX, (u32)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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CMP32RtoR( ECX, EDX );
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j8Ptr[ 0 ] = JNE8( 0 );
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MOV32MtoR( ECX, (u32)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
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MOV32MtoR( EDX, (u32)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
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CMP32RtoR( ECX, EDX );
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j8Ptr[ 1 ] = JNE8( 0 );
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MOV32ItoM( (u32)&cpuRegs.pc, pc + 4 );
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iRet( TRUE );
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x86SetJ8( j8Ptr[ 0 ] );
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x86SetJ8( j8Ptr[ 1 ] );
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MOV32ItoM( (u32)&target, _Imm_ * 4 + pc );
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SetBranch( );
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}
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////////////////////////////////////////////////////
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void recBGEZL( void )
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{
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MOV32ItoM( (u32)&cpuRegs.code, cpuRegs.code );
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MOV32ItoM( (u32)&cpuRegs.pc, pc );
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iFlushCall();
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CALLFunc( (u32)BGEZL );
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branch = 2;
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}
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#endif
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