mirror of
https://github.com/PCSX2/pcsx2.git
synced 2025-04-02 10:52:54 -04:00
638e0b30f6
git-svn-id: http://pcsx2.googlecode.com/svn/branches/pcsx2_0.9.1@159 96395faa-99c1-11dd-bbfe-3dabce05a288
1349 lines
31 KiB
C
1349 lines
31 KiB
C
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2003 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdlib.h>
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#include <string.h>
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#include <assert.h>
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#include "Common.h"
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#include "InterTables.h"
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#include "ix86/ix86.h"
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#include "iR5900.h"
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#ifdef __WIN32__
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#pragma warning(disable:4244)
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#pragma warning(disable:4761)
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#endif
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/*********************************************************
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* Shift arithmetic with constant shift *
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* Format: OP rd, rt, sa *
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*********************************************************/
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#ifndef SHIFT_RECOMPILE
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REC_FUNC(SLL);
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REC_FUNC(SRL);
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REC_FUNC(SRA);
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REC_FUNC(DSLL);
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REC_FUNC(DSRL);
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REC_FUNC(DSRA);
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REC_FUNC(DSLL32);
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REC_FUNC(DSRL32);
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REC_FUNC(DSRA32);
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REC_FUNC(SLLV);
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REC_FUNC(SRLV);
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REC_FUNC(SRAV);
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REC_FUNC(DSLLV);
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REC_FUNC(DSRLV);
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REC_FUNC(DSRAV);
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#elif defined(EE_CONST_PROP)
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//// SLL
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void recSLL_const()
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{
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g_cpuConstRegs[_Rd_].SD[0] = (s32)(g_cpuConstRegs[_Rt_].UL[0] << _Sa_);
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}
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void recSLLs_(int info, int sa)
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{
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int rtreg, rdreg, t0reg;
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assert( !(info & PROCESS_EE_XMM) );
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if( info & PROCESS_EE_MMX ) {
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rtreg = EEREC_T;
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rdreg = EEREC_D;
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}
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else if( g_pCurInstInfo->regs[_Rd_]&EEINST_MMX ) {
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_addNeededMMXreg(MMX_GPR+_Rd_);
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rtreg = rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
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SetMMXstate();
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MOVDMtoMMX(rtreg, (u32)&cpuRegs.GPR.r[_Rt_].UL[0]);
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}
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else {
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MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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if ( sa != 0 )
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{
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SHL32ItoR( EAX, sa );
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}
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if( EEINST_ISLIVE1(_Rd_) ) {
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CDQ( );
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
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}
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else {
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EEINST_RESETHASLIVE1(_Rd_);
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
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}
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return;
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}
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if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
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if( !EEINST_ISLIVE1(_Rd_) ) {
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EEINST_RESETHASLIVE1(_Rd_);
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PSLLDItoR(rdreg, sa);
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return;
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}
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if ( sa != 0 ) {
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t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
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// it is a signed shift
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PSLLDItoR(rdreg, sa);
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MOVQRtoR(t0reg, rdreg);
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PSRADItoR(t0reg, 31);
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// take lower dword of rdreg and lower dword of t0reg
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PUNPCKLDQRtoR(rdreg, t0reg);
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_freeMMXreg(t0reg);
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}
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else {
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if( EEINST_ISLIVE1(_Rd_) ) _signExtendGPRtoMMX(rdreg, _Rd_, 0);
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else EEINST_RESETHASLIVE1(_Rd_);
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}
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}
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void recSLL_(int info)
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{
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recSLLs_(info, _Sa_);
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EEINST_SETSIGNEXT(_Rd_);
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}
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EERECOMPILE_CODEX(eeRecompileCode2, SLL);
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//// SRL
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void recSRL_const()
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{
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g_cpuConstRegs[_Rd_].SD[0] = (s32)(g_cpuConstRegs[_Rt_].UL[0] >> _Sa_);
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}
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void recSRLs_(int info, int sa)
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{
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int rtreg, rdreg;
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assert( !(info & PROCESS_EE_XMM) );
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if( info & PROCESS_EE_MMX ) {
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rtreg = EEREC_T;
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rdreg = EEREC_D;
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}
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else if( (g_pCurInstInfo->regs[_Rt_]&EEINST_MMX) || (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) ) {
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_addNeededMMXreg(MMX_GPR+_Rd_);
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rtreg = rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
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SetMMXstate();
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MOVDMtoMMX(rtreg, (u32)&cpuRegs.GPR.r[_Rt_].UL[0]);
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}
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else {
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MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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if ( sa != 0 ) SHR32ItoR( EAX, sa);
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if( EEINST_ISLIVE1(_Rd_) ) {
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CDQ( );
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
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}
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else {
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EEINST_RESETHASLIVE1(_Rd_);
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
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}
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return;
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}
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if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
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if( !EEINST_ISLIVE1(_Rd_) ) {
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EEINST_RESETHASLIVE1(_Rd_);
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PSRLDItoR(rdreg, sa);
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return;
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}
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if ( sa != 0 ) {
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// rdreg already sign extended
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PSLLQItoR(rdreg, 32);
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PSRLQItoR(rdreg, 32+sa);
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// t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
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//
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// // it is a signed shift
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// PSRLDItoR(rdreg, sa);
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// MOVQRtoR(t0reg, rdreg);
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// PSRADItoR(t0reg, 31);
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//
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// take lower dword of rdreg and lower dword of t0reg
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// PUNPCKLDQRtoR(rdreg, t0reg);
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// _freeMMXreg(t0reg);
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}
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}
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void recSRL_(int info)
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{
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recSRLs_(info, _Sa_);
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EEINST_SETSIGNEXT(_Rd_);
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}
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EERECOMPILE_CODEX(eeRecompileCode2, SRL);
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//// SRA
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void recSRA_const()
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{
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g_cpuConstRegs[_Rd_].SD[0] = (s32)(g_cpuConstRegs[_Rt_].SL[0] >> _Sa_);
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}
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void recSRAs_(int info, int sa)
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{
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int rtreg, rdreg, t0reg;
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assert( !(info & PROCESS_EE_XMM) );
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if( info & PROCESS_EE_MMX ) {
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rtreg = EEREC_T;
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rdreg = EEREC_D;
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}
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else if( (g_pCurInstInfo->regs[_Rt_]&EEINST_MMX) || (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) ) {
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_addNeededMMXreg(MMX_GPR+_Rd_);
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rtreg = rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
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SetMMXstate();
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MOVDMtoMMX(rtreg, (u32)&cpuRegs.GPR.r[_Rt_].UL[0]);
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}
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else {
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MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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if ( sa != 0 ) SAR32ItoR( EAX, sa);
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if( EEINST_ISLIVE1(_Rd_) ) {
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CDQ();
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
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}
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else {
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EEINST_RESETHASLIVE1(_Rd_);
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
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}
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return;
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}
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if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
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if( EEINST_ISSIGNEXT(_Rt_) && EEINST_HASLIVE1(_Rt_) ) {
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PSRADItoR(rdreg, sa);
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return;
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}
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if( !EEINST_ISLIVE1(_Rd_) ) {
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EEINST_RESETHASLIVE1(_Rd_);
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PSRADItoR(rdreg, sa);
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return;
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}
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if ( sa != 0 ) {
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t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
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// it is a signed shift
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PSRADItoR(rdreg, sa);
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MOVQRtoR(t0reg, rdreg);
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PSRADItoR(rdreg, 31);
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// take lower dword of rdreg and lower dword of t0reg
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PUNPCKLDQRtoR(t0reg, rdreg);
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// swap regs
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mmxregs[t0reg] = mmxregs[rdreg];
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mmxregs[rdreg].inuse = 0;
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}
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}
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void recSRA_(int info)
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{
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recSRAs_(info, _Sa_);
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EEINST_SETSIGNEXT(_Rd_);
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}
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EERECOMPILE_CODEX(eeRecompileCode2, SRA);
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////////////////////////////////////////////////////
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void recDSLL_const()
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{
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g_cpuConstRegs[_Rd_].UD[0] = (u64)(g_cpuConstRegs[_Rt_].UD[0] << _Sa_);
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}
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void recDSLLs_(int info, int sa)
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{
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int rtreg, rdreg;
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assert( !(info & PROCESS_EE_XMM) );
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if( info & PROCESS_EE_MMX ) {
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rtreg = EEREC_T;
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rdreg = EEREC_D;
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}
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else {
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_addNeededMMXreg(MMX_GPR+_Rt_);
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_addNeededMMXreg(MMX_GPR+_Rd_);
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rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
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rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
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SetMMXstate();
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}
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if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
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PSLLQItoR(rdreg, sa);
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}
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void recDSLL_(int info)
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{
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recDSLLs_(info, _Sa_);
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}
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EERECOMPILE_CODEX(eeRecompileCode2, DSLL);
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////////////////////////////////////////////////////
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void recDSRL_const()
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{
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g_cpuConstRegs[_Rd_].UD[0] = (u64)(g_cpuConstRegs[_Rt_].UD[0] >> _Sa_);
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}
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void recDSRLs_(int info, int sa)
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{
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int rtreg, rdreg;
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assert( !(info & PROCESS_EE_XMM) );
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if( info & PROCESS_EE_MMX ) {
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rtreg = EEREC_T;
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rdreg = EEREC_D;
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}
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else {
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_addNeededMMXreg(MMX_GPR+_Rt_);
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_addNeededMMXreg(MMX_GPR+_Rd_);
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rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
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rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
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SetMMXstate();
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}
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if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
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PSRLQItoR(rdreg, sa);
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}
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void recDSRL_(int info)
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{
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recDSRLs_(info, _Sa_);
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}
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EERECOMPILE_CODEX(eeRecompileCode2, DSRL);
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//// DSRA
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void recDSRA_const()
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{
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g_cpuConstRegs[_Rd_].SD[0] = (u64)(g_cpuConstRegs[_Rt_].SD[0] >> _Sa_);
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}
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void recDSRAs_(int info, int sa)
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{
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int rtreg, rdreg, t0reg;
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assert( !(info & PROCESS_EE_XMM) );
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if( info & PROCESS_EE_MMX ) {
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rtreg = EEREC_T;
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rdreg = EEREC_D;
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}
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else {
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_addNeededMMXreg(MMX_GPR+_Rt_);
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_addNeededMMXreg(MMX_GPR+_Rd_);
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rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
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rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
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SetMMXstate();
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}
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if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
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if( EEINST_ISSIGNEXT(_Rt_) && EEINST_HASLIVE1(_Rt_) ) {
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PSRADItoR(rdreg, sa);
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return;
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}
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if( !EEINST_ISLIVE1(_Rd_) ) {
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EEINST_RESETHASLIVE1(_Rd_);
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PSRLQItoR(rdreg, sa);
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return;
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}
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if ( sa != 0 ) {
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t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
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MOVQRtoR(t0reg, rtreg);
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// it is a signed shift
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PSRADItoR(t0reg, sa);
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PSRLQItoR(rdreg, sa);
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PUNPCKHDQRtoR(t0reg, t0reg); // shift to lower
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// take lower dword of rdreg and lower dword of t0reg
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PUNPCKLDQRtoR(rdreg, t0reg);
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_freeMMXreg(t0reg);
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}
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}
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void recDSRA_(int info)
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{
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recDSRAs_(info, _Sa_);
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}
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EERECOMPILE_CODEX(eeRecompileCode2, DSRA);
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///// DSLL32
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void recDSLL32_const()
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{
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g_cpuConstRegs[_Rd_].UD[0] = (u64)(g_cpuConstRegs[_Rt_].UD[0] << (_Sa_+32));
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}
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void recDSLL32s_(int info, int sa)
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{
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int rtreg, rdreg;
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assert( !(info & PROCESS_EE_XMM) );
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if( info & PROCESS_EE_MMX ) {
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rtreg = EEREC_T;
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rdreg = EEREC_D;
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}
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else if( (g_pCurInstInfo->regs[_Rt_]&EEINST_MMX) || (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) ) {
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_addNeededMMXreg(MMX_GPR+_Rt_);
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_addNeededMMXreg(MMX_GPR+_Rd_);
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rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
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rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
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SetMMXstate();
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}
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else {
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MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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if ( sa != 0 )
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{
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SHL32ItoR( EAX, sa );
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}
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MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], 0 );
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EAX );
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return;
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}
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if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
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PSLLQItoR(rdreg, sa+32);
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}
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void recDSLL32_(int info)
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{
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recDSLL32s_(info, _Sa_);
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}
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EERECOMPILE_CODEX(eeRecompileCode2, DSLL32);
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//// DSRL32
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void recDSRL32_const()
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{
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g_cpuConstRegs[_Rd_].UD[0] = (u64)(g_cpuConstRegs[_Rt_].UD[0] >> (_Sa_+32));
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}
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void recDSRL32s_(int info, int sa)
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{
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int rtreg, rdreg;
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assert( !(info & PROCESS_EE_XMM) );
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if( info & PROCESS_EE_MMX ) {
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rtreg = EEREC_T;
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rdreg = EEREC_D;
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}
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else if( (g_pCurInstInfo->regs[_Rt_]&EEINST_MMX) || (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) ) {
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_addNeededMMXreg(MMX_GPR+_Rt_);
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_addNeededMMXreg(MMX_GPR+_Rd_);
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rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
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rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
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SetMMXstate();
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}
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else {
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MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
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if ( sa != 0 ) SHR32ItoR( EAX, sa );
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
if( EEINST_ISLIVE1(_Rd_) ) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], 0 );
|
|
else EEINST_RESETHASLIVE1(_Rd_);
|
|
return;
|
|
}
|
|
|
|
if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
|
|
PSRLQItoR(rdreg, sa+32);
|
|
}
|
|
|
|
void recDSRL32_(int info)
|
|
{
|
|
recDSRL32s_(info, _Sa_);
|
|
}
|
|
|
|
EERECOMPILE_CODEX(eeRecompileCode2, DSRL32);
|
|
|
|
//// DSRA32
|
|
void recDSRA32_const()
|
|
{
|
|
g_cpuConstRegs[_Rd_].SD[0] = (u64)(g_cpuConstRegs[_Rt_].SD[0] >> (_Sa_+32));
|
|
}
|
|
|
|
void recDSRA32s_(int info, int sa)
|
|
{
|
|
int rtreg, rdreg, t0reg;
|
|
assert( !(info & PROCESS_EE_XMM) );
|
|
|
|
if( info & PROCESS_EE_MMX ) {
|
|
rtreg = EEREC_T;
|
|
rdreg = EEREC_D;
|
|
}
|
|
else if( (g_pCurInstInfo->regs[_Rt_]&EEINST_MMX) || (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) ) {
|
|
_addNeededMMXreg(MMX_GPR+_Rt_);
|
|
_addNeededMMXreg(MMX_GPR+_Rd_);
|
|
rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
|
|
rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
|
|
SetMMXstate();
|
|
}
|
|
else {
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
|
|
CDQ( );
|
|
if ( sa != 0 ) SAR32ItoR( EAX, sa );
|
|
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
if( EEINST_ISLIVE1(_Rd_) ) MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
|
else EEINST_RESETHASLIVE1(_Rd_);
|
|
return;
|
|
}
|
|
|
|
if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
|
|
|
|
if( EEINST_ISSIGNEXT(_Rt_) && EEINST_HASLIVE1(_Rt_) ) {
|
|
PSRADItoR(rdreg, 31);
|
|
return;
|
|
}
|
|
|
|
if( !EEINST_ISLIVE1(_Rd_) ) {
|
|
EEINST_RESETHASLIVE1(_Rd_);
|
|
if( sa ) PSRADItoR(rdreg, sa);
|
|
PUNPCKHDQRtoR(rdreg, rdreg);
|
|
return;
|
|
}
|
|
|
|
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
MOVQRtoR(t0reg, rtreg);
|
|
|
|
// it is a signed shift
|
|
if( sa ) {
|
|
PSRADItoR(rdreg, sa);
|
|
PSRADItoR(t0reg, 31);
|
|
|
|
// take higher dword of rdreg and lower dword of t0reg
|
|
PUNPCKHDQRtoR(rdreg, t0reg);
|
|
_freeMMXreg(t0reg);
|
|
}
|
|
else {
|
|
// better timing
|
|
PSRADItoR(rdreg, 31);
|
|
|
|
// take higher dword of rdreg and lower dword of t0reg
|
|
PUNPCKHDQRtoR(t0reg, rdreg);
|
|
|
|
// swap
|
|
mmxregs[t0reg] = mmxregs[rdreg];
|
|
mmxregs[rdreg].inuse = 0;
|
|
}
|
|
}
|
|
|
|
void recDSRA32_(int info)
|
|
{
|
|
recDSRA32s_(info, _Sa_);
|
|
}
|
|
|
|
EERECOMPILE_CODEX(eeRecompileCode2, DSRA32);
|
|
|
|
/*********************************************************
|
|
* Shift arithmetic with variant register shift *
|
|
* Format: OP rd, rt, rs *
|
|
*********************************************************/
|
|
|
|
__declspec(align(16)) u32 s_sa[4] = {0x1f, 0, 0x3f, 0};
|
|
|
|
int recSetShiftV(int info, int* rsreg, int* rtreg, int* rdreg, int* rstemp, int forcemmx, int shift64)
|
|
{
|
|
assert( !(info & PROCESS_EE_XMM) );
|
|
|
|
if( info & PROCESS_EE_MMX ) {
|
|
*rtreg = EEREC_T;
|
|
*rdreg = EEREC_D;
|
|
*rsreg = EEREC_S;
|
|
|
|
// make sure to take only low 5 bits of *rsreg
|
|
if( !(g_pCurInstInfo->regs[_Rs_]&EEINST_LASTUSE) && EEINST_ISLIVEMMX(_Rs_)) {
|
|
*rstemp = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
MOVQRtoR(*rstemp, *rsreg);
|
|
*rsreg = *rstemp;
|
|
}
|
|
else {
|
|
if( *rsreg != *rdreg ) {
|
|
_freeMMXreg(*rsreg);
|
|
mmxregs[*rsreg].inuse = 0;
|
|
}
|
|
}
|
|
|
|
PANDMtoR(*rsreg, (u32)&s_sa[shift64?2:0]);
|
|
|
|
if( EEREC_D == EEREC_S ) {
|
|
// need to be separate
|
|
int mmreg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
*rdreg = mmreg;
|
|
mmxregs[mmreg] = mmxregs[EEREC_S];
|
|
mmxregs[EEREC_S].inuse = 0;
|
|
}
|
|
}
|
|
else if( forcemmx || (g_pCurInstInfo->regs[_Rt_]&EEINST_MMX) || (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) ) {
|
|
_addNeededMMXreg(MMX_GPR+_Rt_);
|
|
_addNeededMMXreg(MMX_GPR+_Rd_);
|
|
*rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
|
|
*rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
|
|
SetMMXstate();
|
|
|
|
*rstemp = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
MOV32MtoR(EAX, (u32)&cpuRegs.GPR.r[_Rs_].UL[0]);
|
|
AND32ItoR(EAX, shift64?0x3f:0x1f);
|
|
MOVD32RtoMMX(*rstemp, EAX);
|
|
*rsreg = *rstemp;
|
|
}
|
|
else {
|
|
return 0;
|
|
}
|
|
|
|
if( *rtreg != *rdreg ) MOVQRtoR(*rdreg, *rtreg);
|
|
return 1;
|
|
}
|
|
|
|
void recSetConstShiftV(int info, int* rsreg, int* rdreg, int* rstemp, int shift64)
|
|
{
|
|
if( info & PROCESS_EE_MMX ) {
|
|
*rdreg = EEREC_D;
|
|
*rsreg = EEREC_S;
|
|
|
|
// make sure to take only low 5 bits of *rsreg
|
|
if( !(g_pCurInstInfo->regs[_Rs_]&EEINST_LASTUSE) && EEINST_ISLIVEMMX(_Rs_) ) {
|
|
*rstemp = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
MOVQRtoR(*rstemp, *rsreg);
|
|
*rsreg = *rstemp;
|
|
}
|
|
else {
|
|
if( *rsreg != *rdreg ) {
|
|
_freeMMXreg(*rsreg);
|
|
mmxregs[*rsreg].inuse = 0;
|
|
}
|
|
}
|
|
|
|
PANDMtoR(*rsreg, (u32)&s_sa[shift64?2:0]);
|
|
|
|
|
|
if( EEREC_D == EEREC_S ) {
|
|
// need to be separate
|
|
int mmreg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
*rdreg = mmreg;
|
|
mmxregs[mmreg] = mmxregs[EEREC_S];
|
|
mmxregs[EEREC_S].inuse = 0;
|
|
}
|
|
}
|
|
else {
|
|
_addNeededMMXreg(MMX_GPR+_Rd_);
|
|
*rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
|
|
SetMMXstate();
|
|
|
|
*rstemp = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
MOV32MtoR(EAX, (u32)&cpuRegs.GPR.r[_Rs_].UL[0]);
|
|
AND32ItoR(EAX, shift64?0x3f:0x1f);
|
|
MOVD32RtoMMX(*rstemp, EAX);
|
|
*rsreg = *rstemp;
|
|
}
|
|
|
|
_flushConstReg(_Rt_);
|
|
}
|
|
|
|
void recMoveSignToRd(int info)
|
|
{
|
|
if( EEINST_ISLIVE1(_Rd_) ) {
|
|
CDQ();
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
|
}
|
|
else {
|
|
EEINST_RESETHASLIVE1(_Rd_);
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
}
|
|
|
|
if( info & PROCESS_EE_MMX ) {
|
|
mmxregs[EEREC_D].inuse = 0;
|
|
}
|
|
}
|
|
|
|
//// SLLV
|
|
void recSLLV_const()
|
|
{
|
|
g_cpuConstRegs[_Rd_].SD[0] = (s32)(g_cpuConstRegs[_Rt_].UL[0] << (g_cpuConstRegs[_Rs_].UL[0] &0x1f));
|
|
}
|
|
|
|
void recSLLV_consts(int info)
|
|
{
|
|
recSLLs_(info, g_cpuConstRegs[_Rs_].UL[0]&0x1f);
|
|
EEINST_SETSIGNEXT(_Rd_);
|
|
}
|
|
|
|
void recSLLV_constt(int info)
|
|
{
|
|
if( (info & PROCESS_EE_MMX) && (info & PROCESS_EE_MODEWRITES) ) MOVD32MMXtoR(ECX, EEREC_S);
|
|
else MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
|
|
MOV32ItoR( EAX, g_cpuConstRegs[_Rt_].UL[0] );
|
|
AND32ItoR( ECX, 0x1f );
|
|
SHL32CLtoR( EAX );
|
|
|
|
recMoveSignToRd(info);
|
|
EEINST_SETSIGNEXT(_Rd_);
|
|
}
|
|
|
|
void recSLLV_(int info)
|
|
{
|
|
int rsreg, rtreg, rdreg, rstemp = -1, t0reg;
|
|
EEINST_SETSIGNEXT(_Rd_);
|
|
|
|
if( recSetShiftV(info, &rsreg, &rtreg, &rdreg, &rstemp, 0, 0) == 0 ) {
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
if ( _Rs_ != 0 )
|
|
{
|
|
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
AND32ItoR( ECX, 0x1f );
|
|
SHL32CLtoR( EAX );
|
|
}
|
|
CDQ();
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
|
return;
|
|
}
|
|
|
|
if( !EEINST_ISLIVE1(_Rd_) ) {
|
|
EEINST_RESETHASLIVE1(_Rd_);
|
|
PSLLDRtoR(rdreg, rsreg);
|
|
if( rstemp != -1 ) _freeMMXreg(rstemp);
|
|
return;
|
|
}
|
|
|
|
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
|
|
// it is a signed shift
|
|
PSLLDRtoR(rdreg, rsreg);
|
|
MOVQRtoR(t0reg, rdreg);
|
|
PSRADItoR(t0reg, 31);
|
|
|
|
// take lower dword of rdreg and lower dword of t0reg
|
|
PUNPCKLDQRtoR(rdreg, t0reg);
|
|
_freeMMXreg(t0reg);
|
|
if( rstemp != -1 ) _freeMMXreg(rstemp);
|
|
}
|
|
|
|
EERECOMPILE_CODE0(SLLV, XMMINFO_READS|XMMINFO_READT|XMMINFO_WRITED);
|
|
|
|
//// SRLV
|
|
void recSRLV_const()
|
|
{
|
|
g_cpuConstRegs[_Rd_].SD[0] = (s32)(g_cpuConstRegs[_Rt_].UL[0] >> (g_cpuConstRegs[_Rs_].UL[0] &0x1f));
|
|
}
|
|
|
|
void recSRLV_consts(int info)
|
|
{
|
|
recSRLs_(info, g_cpuConstRegs[_Rs_].UL[0]&0x1f);
|
|
EEINST_SETSIGNEXT(_Rd_);
|
|
}
|
|
|
|
void recSRLV_constt(int info)
|
|
{
|
|
if( (info & PROCESS_EE_MMX) && (info&PROCESS_EE_MODEWRITES) ) MOVD32MMXtoR(ECX, EEREC_S);
|
|
else MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
|
|
MOV32ItoR( EAX, g_cpuConstRegs[_Rt_].UL[0] );
|
|
AND32ItoR( ECX, 0x1f );
|
|
SHR32CLtoR( EAX );
|
|
|
|
recMoveSignToRd(info);
|
|
EEINST_SETSIGNEXT(_Rd_);
|
|
}
|
|
|
|
void recSRLV_(int info)
|
|
{
|
|
int rsreg, rtreg, rdreg, rstemp = -1, t0reg;
|
|
EEINST_SETSIGNEXT(_Rd_);
|
|
|
|
if( recSetShiftV(info, &rsreg, &rtreg, &rdreg, &rstemp, 0, 0) == 0 ) {
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
if ( _Rs_ != 0 )
|
|
{
|
|
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
AND32ItoR( ECX, 0x1f );
|
|
SHR32CLtoR( EAX );
|
|
}
|
|
CDQ( );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
|
return;
|
|
}
|
|
|
|
if( !EEINST_ISLIVE1(_Rd_) ) {
|
|
EEINST_RESETHASLIVE1(_Rd_);
|
|
PSRLDRtoR(rdreg, rsreg);
|
|
if( rstemp != -1 ) _freeMMXreg(rstemp);
|
|
return;
|
|
}
|
|
|
|
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
|
|
// it is a signed shift
|
|
PSRLDRtoR(rdreg, rsreg);
|
|
MOVQRtoR(t0reg, rdreg);
|
|
PSRADItoR(t0reg, 31);
|
|
|
|
// take lower dword of rdreg and lower dword of t0reg
|
|
PUNPCKLDQRtoR(rdreg, t0reg);
|
|
_freeMMXreg(t0reg);
|
|
if( rstemp != -1 ) _freeMMXreg(rstemp);
|
|
}
|
|
|
|
EERECOMPILE_CODE0(SRLV, XMMINFO_READS|XMMINFO_READT|XMMINFO_WRITED);
|
|
|
|
//// SRAV
|
|
void recSRAV_const()
|
|
{
|
|
g_cpuConstRegs[_Rd_].SD[0] = (s32)(g_cpuConstRegs[_Rt_].SL[0] >> (g_cpuConstRegs[_Rs_].UL[0] &0x1f));
|
|
}
|
|
|
|
void recSRAV_consts(int info)
|
|
{
|
|
recSRAs_(info, g_cpuConstRegs[_Rs_].UL[0]&0x1f);
|
|
EEINST_SETSIGNEXT(_Rd_);
|
|
}
|
|
|
|
void recSRAV_constt(int info)
|
|
{
|
|
if( (info & PROCESS_EE_MMX) && (info&PROCESS_EE_MODEWRITES) ) MOVD32MMXtoR(ECX, EEREC_S);
|
|
else MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
|
|
MOV32ItoR( EAX, g_cpuConstRegs[_Rt_].UL[0] );
|
|
AND32ItoR( ECX, 0x1f );
|
|
SAR32CLtoR( EAX );
|
|
|
|
recMoveSignToRd(info);
|
|
EEINST_SETSIGNEXT(_Rd_);
|
|
}
|
|
|
|
void recSRAV_(int info)
|
|
{
|
|
int rsreg, rtreg, rdreg, rstemp = -1, t0reg;
|
|
EEINST_SETSIGNEXT(_Rd_);
|
|
|
|
if( recSetShiftV(info, &rsreg, &rtreg, &rdreg, &rstemp, 0, 0) == 0 ) {
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
if ( _Rs_ != 0 )
|
|
{
|
|
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
AND32ItoR( ECX, 0x1f );
|
|
SAR32CLtoR( EAX );
|
|
}
|
|
CDQ( );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
|
return;
|
|
}
|
|
|
|
if( !EEINST_ISLIVE1(_Rd_) ) {
|
|
EEINST_RESETHASLIVE1(_Rd_);
|
|
PSRADRtoR(rdreg, rsreg);
|
|
if( rstemp != -1 ) _freeMMXreg(rstemp);
|
|
return;
|
|
}
|
|
|
|
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
|
|
// it is a signed shift
|
|
PSRADRtoR(rdreg, rsreg);
|
|
MOVQRtoR(t0reg, rdreg);
|
|
PSRADItoR(t0reg, 31);
|
|
|
|
// take lower dword of rdreg and lower dword of t0reg
|
|
PUNPCKLDQRtoR(rdreg, t0reg);
|
|
_freeMMXreg(t0reg);
|
|
if( rstemp != -1 ) _freeMMXreg(rstemp);
|
|
}
|
|
|
|
EERECOMPILE_CODE0(SRAV, XMMINFO_READS|XMMINFO_READT|XMMINFO_WRITED);
|
|
|
|
//// DSLLV
|
|
void recDSLLV_const()
|
|
{
|
|
g_cpuConstRegs[_Rd_].UD[0] = (u64)(g_cpuConstRegs[_Rt_].UD[0] << (g_cpuConstRegs[_Rs_].UL[0] &0x3f));
|
|
}
|
|
|
|
void recDSLLV_consts(int info)
|
|
{
|
|
int sa = g_cpuConstRegs[_Rs_].UL[0]&0x3f;
|
|
if( sa < 32 ) recDSLLs_(info, sa);
|
|
else recDSLL32s_(info, sa-32);
|
|
}
|
|
|
|
void recDSLLV_constt(int info)
|
|
{
|
|
int rsreg, rdreg, rstemp = -1;
|
|
recSetConstShiftV(info, &rsreg, &rdreg, &rstemp, 1);
|
|
|
|
MOVQMtoR(rdreg, (u32)&cpuRegs.GPR.r[_Rt_]);
|
|
PSLLQRtoR(rdreg, rsreg);
|
|
if( rstemp != -1 ) _freeMMXreg(rstemp);
|
|
}
|
|
|
|
void recDSLLV_(int info)
|
|
{
|
|
int rsreg, rtreg, rdreg, rstemp = -1;
|
|
recSetShiftV(info, &rsreg, &rtreg, &rdreg, &rstemp, 1, 1);
|
|
|
|
PSLLQRtoR(rdreg, rsreg);
|
|
if( rstemp != -1 ) _freeMMXreg(rstemp);
|
|
}
|
|
|
|
EERECOMPILE_CODE0(DSLLV, XMMINFO_READS|XMMINFO_READT|XMMINFO_WRITED);
|
|
|
|
//// DSRLV
|
|
void recDSRLV_const()
|
|
{
|
|
g_cpuConstRegs[_Rd_].UD[0] = (u64)(g_cpuConstRegs[_Rt_].UD[0] >> (g_cpuConstRegs[_Rs_].UL[0] &0x3f));
|
|
}
|
|
|
|
void recDSRLV_consts(int info)
|
|
{
|
|
int sa = g_cpuConstRegs[_Rs_].UL[0]&0x3f;
|
|
if( sa < 32 ) recDSRLs_(info, sa);
|
|
else recDSRL32s_(info, sa-32);
|
|
}
|
|
|
|
void recDSRLV_constt(int info)
|
|
{
|
|
int rsreg, rdreg, rstemp = -1;
|
|
recSetConstShiftV(info, &rsreg, &rdreg, &rstemp, 1);
|
|
|
|
MOVQMtoR(rdreg, (u32)&cpuRegs.GPR.r[_Rt_]);
|
|
PSRLQRtoR(rdreg, rsreg);
|
|
if( rstemp != -1 ) _freeMMXreg(rstemp);
|
|
}
|
|
|
|
void recDSRLV_(int info)
|
|
{
|
|
int rsreg, rtreg, rdreg, rstemp = -1;
|
|
recSetShiftV(info, &rsreg, &rtreg, &rdreg, &rstemp, 1, 1);
|
|
|
|
PSRLQRtoR(rdreg, rsreg);
|
|
if( rstemp != -1 ) _freeMMXreg(rstemp);
|
|
}
|
|
|
|
EERECOMPILE_CODE0(DSRLV, XMMINFO_READS|XMMINFO_READT|XMMINFO_WRITED);
|
|
|
|
//// DSRAV
|
|
void recDSRAV_const()
|
|
{
|
|
g_cpuConstRegs[_Rd_].SD[0] = (s64)(g_cpuConstRegs[_Rt_].SD[0] >> (g_cpuConstRegs[_Rs_].UL[0] &0x3f));
|
|
}
|
|
|
|
void recDSRAV_consts(int info)
|
|
{
|
|
int sa = g_cpuConstRegs[_Rs_].UL[0]&0x3f;
|
|
if( sa < 32 ) recDSRAs_(info, sa);
|
|
else recDSRA32s_(info, sa-32);
|
|
}
|
|
|
|
void recDSRAV_constt(int info)
|
|
{
|
|
int rsreg, rdreg, rstemp = -1, t0reg, t1reg;
|
|
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
t1reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
|
|
recSetConstShiftV(info, &rsreg, &rdreg, &rstemp, 1);
|
|
|
|
MOVQMtoR(rdreg, (u32)&cpuRegs.GPR.r[_Rt_]);
|
|
PXORRtoR(t0reg, t0reg);
|
|
|
|
// calc high bit
|
|
MOVQRtoR(t1reg, rdreg);
|
|
PCMPGTDRtoR(t0reg, rdreg);
|
|
PUNPCKHDQRtoR(t0reg, t0reg); // shift to lower
|
|
|
|
// shift highest bit, 64 - eax
|
|
MOV32ItoR(EAX, 64);
|
|
MOVD32RtoMMX(t1reg, EAX);
|
|
PSUBDRtoR(t1reg, rsreg);
|
|
|
|
// right logical shift
|
|
PSRLQRtoR(rdreg, rsreg);
|
|
PSLLQRtoR(t0reg, t1reg); // highest bits
|
|
|
|
PORRtoR(rdreg, t0reg);
|
|
|
|
_freeMMXreg(t0reg);
|
|
_freeMMXreg(t1reg);
|
|
if( rstemp != -1 ) _freeMMXreg(rstemp);
|
|
}
|
|
|
|
void recDSRAV_(int info)
|
|
{
|
|
int rsreg, rtreg, rdreg, rstemp = -1, t0reg, t1reg;
|
|
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
t1reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
recSetShiftV(info, &rsreg, &rtreg, &rdreg, &rstemp, 1, 1);
|
|
|
|
PXORRtoR(t0reg, t0reg);
|
|
|
|
// calc high bit
|
|
MOVQRtoR(t1reg, rdreg);
|
|
PCMPGTDRtoR(t0reg, rdreg);
|
|
PUNPCKHDQRtoR(t0reg, t0reg); // shift to lower
|
|
|
|
// shift highest bit, 64 - eax
|
|
MOV32ItoR(EAX, 64);
|
|
MOVD32RtoMMX(t1reg, EAX);
|
|
PSUBDRtoR(t1reg, rsreg);
|
|
|
|
// right logical shift
|
|
PSRLQRtoR(rdreg, rsreg);
|
|
PSLLQRtoR(t0reg, t1reg); // highest bits
|
|
|
|
PORRtoR(rdreg, t0reg);
|
|
|
|
_freeMMXreg(t0reg);
|
|
_freeMMXreg(t1reg);
|
|
if( rstemp != -1 ) _freeMMXreg(rstemp);
|
|
}
|
|
|
|
EERECOMPILE_CODE0(DSRAV, XMMINFO_READS|XMMINFO_READT|XMMINFO_WRITED);
|
|
|
|
#else
|
|
|
|
////////////////////////////////////////////////////
|
|
void recDSRA( void )
|
|
{
|
|
if( !_Rd_ ) return; //?
|
|
|
|
if ( _Sa_ != 0 ) {
|
|
// it is a signed shift
|
|
MOVQMtoR(MM0, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
MOVQRtoR(MM1, MM0);
|
|
PSRADItoR(MM0, _Sa_);
|
|
PSRLQItoR(MM1, _Sa_);
|
|
|
|
PUNPCKHDQRtoR(MM0, MM0); // shift to lower
|
|
// take lower dword of MM1 and lower dword of MM0
|
|
|
|
PUNPCKLDQRtoR(MM1, MM0);
|
|
|
|
MOVQRtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], MM1);
|
|
}
|
|
else {
|
|
MOVQMtoR(MM0, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
MOVQRtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], MM0);
|
|
}
|
|
|
|
SetMMXstate();
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recDSRA32(void)
|
|
{
|
|
if( !_Rd_ ) return; //?
|
|
|
|
MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
|
|
CDQ();
|
|
|
|
if ( _Sa_ != 0 )
|
|
{
|
|
SAR32ItoR( EAX, _Sa_ );
|
|
}
|
|
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX);
|
|
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX);
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recSLL( void )
|
|
{
|
|
if ( ! _Rd_ )
|
|
return;
|
|
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
if ( _Sa_ != 0 )
|
|
{
|
|
SHL32ItoR( EAX, _Sa_ );
|
|
}
|
|
CDQ( );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recSRL( void )
|
|
{
|
|
if ( ! _Rd_ )
|
|
{
|
|
return;
|
|
}
|
|
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
if ( _Sa_ != 0 )
|
|
{
|
|
SHR32ItoR( EAX, _Sa_);
|
|
}
|
|
CDQ( );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
|
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recSRA( void )
|
|
{
|
|
if ( ! _Rd_ )
|
|
{
|
|
return;
|
|
}
|
|
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
if ( _Sa_ != 0 )
|
|
{
|
|
SAR32ItoR( EAX, _Sa_);
|
|
}
|
|
CDQ();
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
|
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recDSLL( void )
|
|
{
|
|
if ( ! _Rd_ )
|
|
{
|
|
return;
|
|
}
|
|
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rt_ ] );
|
|
if ( _Sa_ != 0 )
|
|
{
|
|
PSLLQItoR( MM0, _Sa_ );
|
|
}
|
|
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ], MM0 );
|
|
SetMMXstate();
|
|
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recDSRL( void )
|
|
{
|
|
if ( ! _Rd_ )
|
|
{
|
|
return;
|
|
}
|
|
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rt_ ] );
|
|
if ( _Sa_ != 0 )
|
|
{
|
|
PSRLQItoR( MM0, _Sa_ );
|
|
}
|
|
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ], MM0 );
|
|
SetMMXstate();
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recDSLL32( void )
|
|
{
|
|
if ( ! _Rd_ )
|
|
{
|
|
return;
|
|
}
|
|
|
|
if ( _Sa_ == 0 )
|
|
{
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], 0 );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EAX );
|
|
return;
|
|
}
|
|
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rt_ ] );
|
|
PSLLQItoR( MM0, _Sa_ + 32 );
|
|
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ], MM0 );
|
|
SetMMXstate();
|
|
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recDSRL32( void )
|
|
{
|
|
if ( ! _Rd_ )
|
|
{
|
|
return;
|
|
}
|
|
|
|
|
|
if ( _Sa_ == 0 )
|
|
{
|
|
MOV32MtoR( EAX,(int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
|
|
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], 0 );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
return;
|
|
}
|
|
|
|
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rt_ ] );
|
|
PSRLQItoR( MM0, _Sa_ + 32 );
|
|
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ], MM0 );
|
|
SetMMXstate();
|
|
|
|
}
|
|
|
|
|
|
/*********************************************************
|
|
* Shift arithmetic with variant register shift *
|
|
* Format: OP rd, rt, rs *
|
|
*********************************************************/
|
|
|
|
////////////////////////////////////////////////////
|
|
|
|
|
|
////////////////////////////////////////////////////
|
|
void recSLLV( void )
|
|
{
|
|
|
|
if ( ! _Rd_ ) return;
|
|
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
if ( _Rs_ != 0 )
|
|
{
|
|
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
AND32ItoR( ECX, 0x1f );
|
|
SHL32CLtoR( EAX );
|
|
}
|
|
CDQ();
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
|
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recSRLV( void )
|
|
{
|
|
|
|
if ( ! _Rd_ ) return;
|
|
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
if ( _Rs_ != 0 )
|
|
{
|
|
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
AND32ItoR( ECX, 0x1f );
|
|
SHR32CLtoR( EAX );
|
|
}
|
|
CDQ( );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
|
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recSRAV( void )
|
|
{
|
|
if ( ! _Rd_ ) return;
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
if ( _Rs_ != 0 )
|
|
{
|
|
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
AND32ItoR( ECX, 0x1f );
|
|
SAR32CLtoR( EAX );
|
|
}
|
|
CDQ( );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
|
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
static u64 _sa = 0;
|
|
void recDSLLV( void )
|
|
{
|
|
if ( ! _Rd_ ) return;
|
|
|
|
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rt_ ] );
|
|
if ( _Rs_ != 0 )
|
|
{
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ] );
|
|
AND32ItoR( EAX, 0x3f);
|
|
MOV32RtoM( (int)&_sa, EAX );
|
|
PSLLQMtoR( MM0, (int)&_sa );
|
|
}
|
|
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ], MM0 );
|
|
SetMMXstate();
|
|
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recDSRLV( void )
|
|
{
|
|
if ( ! _Rd_ ) return;
|
|
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rt_ ] );
|
|
if ( _Rs_ != 0 )
|
|
{
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ] );
|
|
AND32ItoR( EAX, 0x3f);
|
|
MOV32RtoM( (int)&_sa, EAX );
|
|
PSRLQMtoR( MM0, (int)&_sa );
|
|
}
|
|
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ], MM0 );
|
|
SetMMXstate();
|
|
|
|
}
|
|
////////////////////////////////////////////////////////////////
|
|
void recDSRAV( void )
|
|
{
|
|
MOVQMtoR(MM0, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
|
|
if ( _Rs_ != 0 ) {
|
|
PXORRtoR(MM1, MM1);
|
|
|
|
// calc high bit
|
|
MOVQRtoR(MM2, MM0);
|
|
PUNPCKHDQRtoR(MM2, MM2); // shift to lower
|
|
PCMPGTDRtoR(MM1, MM2);
|
|
|
|
// it is a signed shift
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ] );
|
|
AND32ItoR( EAX, 0x3f);
|
|
MOVD32RtoMMX(MM2, EAX); // amount to shift
|
|
NOT32R(EAX);
|
|
ADD32ItoR(EAX, 65);
|
|
|
|
// right logical shift
|
|
PSRLQRtoR(MM0, MM2);
|
|
|
|
// shift highest bit, 64 - eax
|
|
MOVD32RtoMMX(MM2, EAX);
|
|
PSLLQRtoR(MM1, MM2); // highest bits
|
|
|
|
PORRtoR(MM0, MM1);
|
|
MOVQRtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], MM0);
|
|
}
|
|
else {
|
|
MOVQRtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], MM0);
|
|
}
|
|
|
|
SetMMXstate();
|
|
}
|
|
#endif
|