mirror of
https://github.com/PCSX2/pcsx2.git
synced 2025-04-02 10:52:54 -04:00
638e0b30f6
git-svn-id: http://pcsx2.googlecode.com/svn/branches/pcsx2_0.9.1@159 96395faa-99c1-11dd-bbfe-3dabce05a288
822 lines
20 KiB
C
822 lines
20 KiB
C
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2003 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdlib.h>
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#include <string.h>
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#include <assert.h>
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#include "Common.h"
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#include "InterTables.h"
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#include "ix86/ix86.h"
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#include "iR5900.h"
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#ifdef __WIN32__
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#pragma warning(disable:4244)
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#pragma warning(disable:4761)
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#endif
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/*********************************************************
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* Shift arithmetic with constant shift *
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* Format: OP rd, rt, sa *
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*********************************************************/
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#ifndef MOVE_RECOMPILE
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REC_FUNC(LUI);
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REC_FUNC(MFLO);
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REC_FUNC(MFHI);
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REC_FUNC(MTLO);
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REC_FUNC(MTHI);
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REC_FUNC( MFHI1 );
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REC_FUNC( MFLO1 );
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REC_FUNC( MTHI1 );
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REC_FUNC( MTLO1 );
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REC_FUNC(MOVZ);
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REC_FUNC(MOVN);
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#elif defined(EE_CONST_PROP)
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/*********************************************************
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* Load higher 16 bits of the first word in GPR with imm *
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* Format: OP rt, immediate *
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*********************************************************/
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//// LUI
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void recLUI(int info)
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{
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int mmreg;
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if(!_Rt_) return;
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_eeOnWriteReg(_Rt_, 1);
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if( (mmreg = _checkXMMreg(XMMTYPE_GPRREG, _Rt_, MODE_WRITE)) >= 0 ) {
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if( xmmregs[mmreg].mode & MODE_WRITE ) {
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SSE_MOVHPS_XMM_to_M64((u32)&cpuRegs.GPR.r[_Rt_].UL[2], mmreg);
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}
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xmmregs[mmreg].inuse = 0;
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}
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_deleteEEreg(_Rt_, 0);
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GPR_SET_CONST(_Rt_);
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g_cpuConstRegs[_Rt_].UD[0] = (s32)(cpuRegs.code << 16);
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}
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////////////////////////////////////////////////////
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void recMFHILO(int hi)
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{
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int reghi, regd, xmmhilo;
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if ( ! _Rd_ )
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return;
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xmmhilo = hi ? XMMGPR_HI : XMMGPR_LO;
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reghi = _checkXMMreg(XMMTYPE_GPRREG, xmmhilo, MODE_READ);
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_eeOnWriteReg(_Rd_, 0);
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regd = _checkXMMreg(XMMTYPE_GPRREG, _Rd_, MODE_READ|MODE_WRITE);
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if( reghi >= 0 ) {
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if( regd >= 0 ) {
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assert( regd != reghi );
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xmmregs[regd].inuse = 0;
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if( cpucaps.hasStreamingSIMD2Extensions ) {
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SSE2_MOVQ_XMM_to_M64((u32)&cpuRegs.GPR.r[_Rd_].UL[0], reghi);
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}
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else {
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SSE_MOVLPS_XMM_to_M64((u32)&cpuRegs.GPR.r[_Rd_].UL[0], reghi);
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}
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if( xmmregs[regd].mode & MODE_WRITE ) {
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SSE_MOVHPS_XMM_to_M64((u32)&cpuRegs.GPR.r[_Rd_].UL[2], regd);
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}
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}
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else {
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regd = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rd_, MODE_WRITE);
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if( regd >= 0 ) {
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SSE2_MOVDQ2Q_XMM_to_MM(regd, reghi);
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}
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else {
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_deleteEEreg(_Rd_, 0);
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SSE2_MOVQ_XMM_to_M64((int)&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ], reghi);
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}
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}
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}
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else {
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reghi = _checkMMXreg(MMX_GPR+xmmhilo, MODE_READ);
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if( reghi >= 0 ) {
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if( regd >= 0 ) {
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if( EEINST_ISLIVE2(_Rd_) ) {
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if( xmmregs[regd].mode & MODE_WRITE ) {
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SSE_MOVHPS_XMM_to_M64((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 2 ], regd);
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}
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xmmregs[regd].inuse = 0;
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MOVQRtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ], reghi);
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}
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else {
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SetMMXstate();
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SSE2_MOVQ2DQ_MM_to_XMM(regd, reghi);
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xmmregs[regd].mode |= MODE_WRITE;
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}
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}
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else {
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regd = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rd_, MODE_WRITE);
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SetMMXstate();
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if( regd >= 0 ) {
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MOVQRtoR(regd, reghi);
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}
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else {
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_deleteEEreg(_Rd_, 0);
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MOVQRtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ], reghi);
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}
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}
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}
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else {
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if( regd >= 0 ) {
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if( EEINST_ISLIVE2(_Rd_) ) SSE_MOVLPS_M64_to_XMM(regd, hi ? (int)&cpuRegs.HI.UD[ 0 ] : (int)&cpuRegs.LO.UD[ 0 ]);
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else SSE2_MOVQ_M64_to_XMM(regd, hi ? (int)&cpuRegs.HI.UD[ 0 ] : (int)&cpuRegs.LO.UD[ 0 ]);
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}
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else {
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regd = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rd_, MODE_WRITE);
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if( regd >= 0 ) {
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SetMMXstate();
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MOVQMtoR(regd, hi ? (int)&cpuRegs.HI.UD[ 0 ] : (int)&cpuRegs.LO.UD[ 0 ]);
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}
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else {
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_deleteEEreg(_Rd_, 0);
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MOV32MtoR( EAX, hi ? (int)&cpuRegs.HI.UL[ 0 ] : (int)&cpuRegs.LO.UL[ 0 ]);
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if( EEINST_ISLIVE1(_Rd_) )
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MOV32MtoR( EDX, hi ? (int)&cpuRegs.HI.UL[ 1 ] : (int)&cpuRegs.LO.UL[ 1 ]);
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
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if( EEINST_ISLIVE1(_Rd_) )
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
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else
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EEINST_RESETHASLIVE1(_Rd_);
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}
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}
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}
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}
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}
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void recMTHILO(int hi)
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{
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int reghi, regs, xmmhilo;
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u32 addrhilo;
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xmmhilo = hi ? XMMGPR_HI : XMMGPR_LO;
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addrhilo = hi ? (int)&cpuRegs.HI.UD[0] : (int)&cpuRegs.LO.UD[0];
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regs = _checkXMMreg(XMMTYPE_GPRREG, _Rs_, MODE_READ);
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reghi = _checkXMMreg(XMMTYPE_GPRREG, xmmhilo, MODE_READ|MODE_WRITE);
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if( reghi >= 0 ) {
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if( regs >= 0 ) {
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assert( reghi != regs );
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if( cpucaps.hasStreamingSIMD2Extensions ) {
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_deleteGPRtoXMMreg(_Rs_, 0);
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SSE2_PUNPCKHQDQ_XMM_to_XMM(reghi, reghi);
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SSE2_PUNPCKLQDQ_XMM_to_XMM(regs, reghi);
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// swap regs
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xmmregs[regs] = xmmregs[reghi];
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xmmregs[reghi].inuse = 0;
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xmmregs[regs].mode |= MODE_WRITE;
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}
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else {
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SSE2EMU_MOVSD_XMM_to_XMM(reghi, regs);
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xmmregs[reghi].mode |= MODE_WRITE;
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}
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}
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else {
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regs = _checkMMXreg(MMX_GPR+_Rs_, MODE_READ);
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if( regs >= 0 ) {
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if( EEINST_ISLIVE2(xmmhilo) ) {
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if( xmmregs[reghi].mode & MODE_WRITE ) {
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SSE_MOVHPS_XMM_to_M64(addrhilo+8, reghi);
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}
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xmmregs[reghi].inuse = 0;
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MOVQRtoM(addrhilo, regs);
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}
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else {
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SetMMXstate();
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SSE2_MOVQ2DQ_MM_to_XMM(reghi, regs);
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xmmregs[reghi].mode |= MODE_WRITE;
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}
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}
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else {
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_flushConstReg(_Rs_);
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SSE_MOVLPS_M64_to_XMM(reghi, (int)&cpuRegs.GPR.r[ _Rs_ ].UD[ 0 ]);
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xmmregs[reghi].mode |= MODE_WRITE;
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}
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}
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}
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else {
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reghi = _allocCheckGPRtoMMX(g_pCurInstInfo, xmmhilo, MODE_WRITE);
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if( reghi >= 0 ) {
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if( regs >= 0 ) {
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//SetMMXstate();
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SSE2_MOVDQ2Q_XMM_to_MM(reghi, regs);
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}
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else {
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regs = _checkMMXreg(MMX_GPR+_Rs_, MODE_WRITE);
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if( regs >= 0 ) {
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SetMMXstate();
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MOVQRtoR(reghi, regs);
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}
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else {
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_flushConstReg(_Rs_);
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MOVQMtoR(reghi, (int)&cpuRegs.GPR.r[ _Rs_ ].UD[ 0 ]);
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}
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}
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}
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else {
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if( regs >= 0 ) {
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SSE2_MOVQ_XMM_to_M64(addrhilo, regs);
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}
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else {
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regs = _checkMMXreg(MMX_GPR+_Rs_, MODE_WRITE);
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if( regs >= 0 ) {
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SetMMXstate();
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MOVQRtoM(addrhilo, regs);
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}
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else {
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if( GPR_IS_CONST1(_Rs_) ) {
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MOV32ItoM(addrhilo, g_cpuConstRegs[_Rs_].UL[0] );
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MOV32ItoM(addrhilo+4, g_cpuConstRegs[_Rs_].UL[1] );
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}
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else {
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_deleteEEreg(_Rs_, 1);
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MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
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MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]);
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MOV32RtoM( addrhilo, EAX );
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MOV32RtoM( addrhilo+4, EDX );
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}
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}
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}
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}
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}
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}
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void recMFHI( void )
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{
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recMFHILO(1);
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}
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void recMFLO( void )
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{
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recMFHILO(0);
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}
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void recMTHI( void )
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{
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recMTHILO(1);
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}
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void recMTLO( void )
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{
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recMTHILO(0);
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}
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////////////////////////////////////////////////////
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void recMFHILO1(int hi)
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{
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int reghi, regd, xmmhilo;
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if ( ! _Rd_ )
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return;
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xmmhilo = hi ? XMMGPR_HI : XMMGPR_LO;
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reghi = _checkXMMreg(XMMTYPE_GPRREG, xmmhilo, MODE_READ);
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_eeOnWriteReg(_Rd_, 0);
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regd = _checkXMMreg(XMMTYPE_GPRREG, _Rd_, MODE_READ|MODE_WRITE);
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if( reghi >= 0 ) {
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if( regd >= 0 ) {
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SSEX_MOVHLPS_XMM_to_XMM(regd, reghi);
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xmmregs[regd].mode |= MODE_WRITE;
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}
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else {
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_deleteEEreg(_Rd_, 0);
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SSE_MOVHPS_XMM_to_M64((int)&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ], reghi);
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}
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}
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else {
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if( regd >= 0 ) {
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if( EEINST_ISLIVE2(_Rd_) ) {
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if( cpucaps.hasStreamingSIMD2Extensions ) {
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SSE2_PUNPCKHQDQ_M128_to_XMM(regd, hi ? (int)&cpuRegs.HI.UD[ 0 ] : (int)&cpuRegs.LO.UD[ 0 ]);
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SSE2_PSHUFD_XMM_to_XMM(regd, regd, 0x4e);
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}
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else {
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SSE_MOVLPS_M64_to_XMM(regd, hi ? (int)&cpuRegs.HI.UD[ 1 ] : (int)&cpuRegs.LO.UD[ 1 ]);
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}
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}
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else {
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SSE2_MOVQ_M64_to_XMM(regd, hi ? (int)&cpuRegs.HI.UD[ 1 ] : (int)&cpuRegs.LO.UD[ 1 ]);
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}
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xmmregs[regd].mode |= MODE_WRITE;
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}
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else {
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regd = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rd_, MODE_WRITE);
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if( regd >= 0 ) {
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SetMMXstate();
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MOVQMtoR(regd, hi ? (int)&cpuRegs.HI.UD[ 1 ] : (int)&cpuRegs.LO.UD[ 1 ]);
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}
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else {
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_deleteEEreg(_Rd_, 0);
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MOV32MtoR( EAX, hi ? (int)&cpuRegs.HI.UL[ 2 ] : (int)&cpuRegs.LO.UL[ 2 ]);
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MOV32MtoR( EDX, hi ? (int)&cpuRegs.HI.UL[ 3 ] : (int)&cpuRegs.LO.UL[ 3 ]);
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
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}
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}
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}
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}
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void recMTHILO1(int hi)
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{
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int reghi, regs, xmmhilo;
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u32 addrhilo;
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xmmhilo = hi ? XMMGPR_HI : XMMGPR_LO;
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addrhilo = hi ? (int)&cpuRegs.HI.UD[0] : (int)&cpuRegs.LO.UD[0];
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regs = _checkXMMreg(XMMTYPE_GPRREG, _Rs_, MODE_READ);
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reghi = _allocCheckGPRtoXMM(g_pCurInstInfo, xmmhilo, MODE_WRITE|MODE_READ);
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if( reghi >= 0 ) {
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if( regs >= 0 ) {
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if( cpucaps.hasStreamingSIMD2Extensions ) SSE2_PUNPCKLQDQ_XMM_to_XMM(reghi, regs);
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else SSE_MOVLHPS_XMM_to_XMM(reghi, regs);
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}
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else {
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_deleteEEreg(_Rs_, 1);
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if( cpucaps.hasStreamingSIMD2Extensions ) SSE2_PUNPCKLQDQ_M128_to_XMM(reghi, (int)&cpuRegs.GPR.r[ _Rs_ ].UD[ 0 ]);
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else SSE_MOVHPS_M64_to_XMM(reghi, (int)&cpuRegs.GPR.r[ _Rs_ ].UD[ 1 ]);
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}
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}
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else {
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if( regs >= 0 ) {
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SSE2_MOVQ_XMM_to_M64(addrhilo+8, regs);
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}
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else {
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regs = _checkMMXreg(MMX_GPR+_Rs_, MODE_WRITE);
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if( regs >= 0 ) {
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SetMMXstate();
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MOVQRtoM(addrhilo+8, regs);
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}
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else {
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if( GPR_IS_CONST1(_Rs_) ) {
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MOV32ItoM(addrhilo+8, g_cpuConstRegs[_Rs_].UL[0] );
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MOV32ItoM(addrhilo+12, g_cpuConstRegs[_Rs_].UL[1] );
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}
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else {
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_deleteEEreg(_Rs_, 1);
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MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
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MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]);
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MOV32RtoM( addrhilo+8, EAX );
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MOV32RtoM( addrhilo+12, EDX );
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}
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}
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}
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}
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}
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void recMFHI1( void )
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{
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recMFHILO1(1);
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}
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void recMFLO1( void )
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{
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recMFHILO1(0);
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}
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void recMTHI1( void )
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{
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recMTHILO1(1);
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}
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void recMTLO1( void )
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{
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recMTHILO1(0);
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}
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//// MOVZ
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void recMOVZtemp_const()
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{
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GPR_DEL_CONST(_Rd_);
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_deleteEEreg(_Rd_, 1);
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_eeOnWriteReg(_Rd_, 0);
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if (g_cpuConstRegs[_Rt_].UD[0] == 0) {
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MOV32ItoM((u32)&cpuRegs.GPR.r[_Rd_].UL[0], g_cpuConstRegs[_Rs_].UL[0]);
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MOV32ItoM((u32)&cpuRegs.GPR.r[_Rd_].UL[1], g_cpuConstRegs[_Rs_].UL[1]);
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}
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}
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__declspec(align(16)) static s_zero[4] = {0,0,0xffffffff, 0xffffffff};
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void recMOVZtemp_consts(int info)
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{
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if( info & PROCESS_EE_MMX ) {
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u32* mem;
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int t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
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PXORRtoR(t0reg, t0reg);
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PCMPEQDRtoR(t0reg, EEREC_T);
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PMOVMSKBMMXtoR(EAX, t0reg);
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CMP8ItoR(EAX, 0xff);
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j8Ptr[ 0 ] = JNE8( 0 );
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|
|
if( g_cpuFlushedConstReg & (1<<_Rs_) ) mem = &cpuRegs.GPR.r[_Rs_].UL[0];
|
|
else {
|
|
mem = recAllocStackMem(8,8);
|
|
|
|
mem[0] = g_cpuConstRegs[_Rs_].UL[0];
|
|
mem[1] = g_cpuConstRegs[_Rs_].UL[1];
|
|
}
|
|
|
|
MOVQMtoR(EEREC_D, (u32)mem);
|
|
x86SetJ8( j8Ptr[ 0 ] );
|
|
|
|
_freeMMXreg(t0reg);
|
|
return;
|
|
}
|
|
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
OR32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
|
|
j8Ptr[ 0 ] = JNZ8( 0 );
|
|
|
|
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], g_cpuConstRegs[_Rs_].UL[0] );
|
|
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], g_cpuConstRegs[_Rs_].UL[1] );
|
|
|
|
x86SetJ8( j8Ptr[ 0 ] );
|
|
}
|
|
|
|
void recMOVZtemp_constt(int info)
|
|
{
|
|
if (g_cpuConstRegs[_Rt_].UD[0] == 0) {
|
|
if( info & PROCESS_EE_MMX ) {
|
|
if( EEREC_D != EEREC_S ) MOVQRtoR(EEREC_D, EEREC_S);
|
|
return;
|
|
}
|
|
|
|
if( _hasFreeXMMreg() ) {
|
|
int t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
MOVQMtoR(t0reg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
|
|
MOVQRtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], t0reg);
|
|
_freeMMXreg(t0reg);
|
|
}
|
|
else {
|
|
MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
|
|
MOV32MtoR(EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]);
|
|
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX);
|
|
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX);
|
|
}
|
|
}
|
|
}
|
|
|
|
void recMOVZtemp_(int info)
|
|
{
|
|
int t0reg = -1;
|
|
|
|
if( info & PROCESS_EE_MMX ) {
|
|
|
|
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
PXORRtoR(t0reg, t0reg);
|
|
PCMPEQDRtoR(t0reg, EEREC_T);
|
|
PMOVMSKBMMXtoR(EAX, t0reg);
|
|
CMP8ItoR(EAX, 0xff);
|
|
j8Ptr[ 0 ] = JNE8( 0 );
|
|
|
|
MOVQRtoR(EEREC_D, EEREC_S);
|
|
x86SetJ8( j8Ptr[ 0 ] );
|
|
|
|
_freeMMXreg(t0reg);
|
|
return;
|
|
}
|
|
|
|
if( _hasFreeXMMreg() )
|
|
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
OR32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
|
|
j8Ptr[ 0 ] = JNZ8( 0 );
|
|
|
|
if( t0reg >= 0 ) {
|
|
MOVQMtoR(t0reg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
|
|
MOVQRtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], t0reg);
|
|
_freeMMXreg(t0reg);
|
|
}
|
|
else {
|
|
MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
|
|
MOV32MtoR(EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]);
|
|
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX);
|
|
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX);
|
|
}
|
|
|
|
x86SetJ8( j8Ptr[ 0 ] );
|
|
SetMMXstate();
|
|
}
|
|
|
|
EERECOMPILE_CODE0(MOVZtemp, XMMINFO_READS|XMMINFO_READD|XMMINFO_READD|XMMINFO_WRITED);
|
|
|
|
void recMOVZ()
|
|
{
|
|
if( _Rs_ == _Rd_ )
|
|
return;
|
|
|
|
if( GPR_IS_CONST1(_Rd_) ) {
|
|
|
|
if( !GPR_IS_CONST2(_Rs_, _Rt_) ) {
|
|
// remove the const, since move is conditional
|
|
_deleteEEreg(_Rd_, 0);
|
|
MOV32ItoM((u32)&cpuRegs.GPR.r[_Rd_].UL[0], g_cpuConstRegs[_Rd_].UL[0]);
|
|
MOV32ItoM((u32)&cpuRegs.GPR.r[_Rd_].UL[1], g_cpuConstRegs[_Rd_].UL[1]);
|
|
}
|
|
}
|
|
|
|
recMOVZtemp();
|
|
}
|
|
|
|
//// MOVN
|
|
void recMOVNtemp_const()
|
|
{
|
|
GPR_DEL_CONST(_Rd_);
|
|
_deleteEEreg(_Rd_, 1);
|
|
_eeOnWriteReg(_Rd_, 0);
|
|
if (g_cpuConstRegs[_Rt_].UD[0] != 0) {
|
|
MOV32ItoM((u32)&cpuRegs.GPR.r[_Rd_].UL[0], g_cpuConstRegs[_Rs_].UL[0]);
|
|
MOV32ItoM((u32)&cpuRegs.GPR.r[_Rd_].UL[1], g_cpuConstRegs[_Rs_].UL[1]);
|
|
}
|
|
}
|
|
|
|
void recMOVNtemp_consts(int info)
|
|
{
|
|
if( info & PROCESS_EE_MMX ) {
|
|
|
|
u32* mem;
|
|
int t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
PXORRtoR(t0reg, t0reg);
|
|
PCMPEQDRtoR(t0reg, EEREC_T);
|
|
|
|
PMOVMSKBMMXtoR(EAX, t0reg);
|
|
CMP8ItoR(EAX, 0xff);
|
|
j8Ptr[ 0 ] = JE8( 0 );
|
|
|
|
if( g_cpuFlushedConstReg & (1<<_Rs_) ) mem = &cpuRegs.GPR.r[_Rs_].UL[0];
|
|
else {
|
|
mem = recAllocStackMem(8,8);
|
|
|
|
mem[0] = g_cpuConstRegs[_Rs_].UL[0];
|
|
mem[1] = g_cpuConstRegs[_Rs_].UL[1];
|
|
}
|
|
|
|
MOVQMtoR(EEREC_D, (u32)mem);
|
|
x86SetJ8( j8Ptr[ 0 ] );
|
|
|
|
_freeMMXreg(t0reg);
|
|
return;
|
|
}
|
|
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
OR32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
|
|
j8Ptr[ 0 ] = JZ8( 0 );
|
|
|
|
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], g_cpuConstRegs[_Rs_].UL[0] );
|
|
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], g_cpuConstRegs[_Rs_].UL[1] );
|
|
|
|
x86SetJ8( j8Ptr[ 0 ] );
|
|
}
|
|
|
|
void recMOVNtemp_constt(int info)
|
|
{
|
|
if (g_cpuConstRegs[_Rt_].UD[0] != 0) {
|
|
if( _hasFreeXMMreg() ) {
|
|
int t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
MOVQMtoR(t0reg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
|
|
MOVQRtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], t0reg);
|
|
_freeMMXreg(t0reg);
|
|
}
|
|
else {
|
|
MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
|
|
MOV32MtoR(EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]);
|
|
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX);
|
|
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX);
|
|
}
|
|
}
|
|
}
|
|
|
|
void recMOVNtemp_(int info)
|
|
{
|
|
int t0reg=-1;
|
|
|
|
if( info & PROCESS_EE_MMX ) {
|
|
|
|
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
PXORRtoR(t0reg, t0reg);
|
|
PCMPEQDRtoR(t0reg, EEREC_T);
|
|
PMOVMSKBMMXtoR(EAX, t0reg);
|
|
CMP8ItoR(EAX, 0xff);
|
|
j8Ptr[ 0 ] = JE8( 0 );
|
|
|
|
MOVQRtoR(EEREC_D, EEREC_S);
|
|
x86SetJ8( j8Ptr[ 0 ] );
|
|
|
|
_freeMMXreg(t0reg);
|
|
return;
|
|
}
|
|
|
|
if( _hasFreeXMMreg() )
|
|
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
OR32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
|
|
j8Ptr[ 0 ] = JZ8( 0 );
|
|
|
|
if( t0reg >= 0 ) {
|
|
MOVQMtoR(t0reg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
|
|
MOVQRtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], t0reg);
|
|
_freeMMXreg(t0reg);
|
|
}
|
|
else {
|
|
MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
|
|
MOV32MtoR(EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]);
|
|
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX);
|
|
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX);
|
|
}
|
|
|
|
x86SetJ8( j8Ptr[ 0 ] );
|
|
|
|
SetMMXstate();
|
|
}
|
|
|
|
EERECOMPILE_CODE0(MOVNtemp, XMMINFO_READS|XMMINFO_READD|XMMINFO_READD|XMMINFO_WRITED);
|
|
|
|
void recMOVN()
|
|
{
|
|
if( _Rs_ == _Rd_ )
|
|
return;
|
|
|
|
if( GPR_IS_CONST1(_Rd_) ) {
|
|
|
|
if( !GPR_IS_CONST2(_Rs_, _Rt_) ) {
|
|
// remove the const, since move is conditional
|
|
_deleteEEreg(_Rd_, 0);
|
|
MOV32ItoM((u32)&cpuRegs.GPR.r[_Rd_].UL[0], g_cpuConstRegs[_Rd_].UL[0]);
|
|
MOV32ItoM((u32)&cpuRegs.GPR.r[_Rd_].UL[1], g_cpuConstRegs[_Rd_].UL[1]);
|
|
}
|
|
}
|
|
|
|
recMOVNtemp();
|
|
}
|
|
|
|
#else
|
|
|
|
////////////////////////////////////////////////////
|
|
void recLUI( void )
|
|
{
|
|
if(!_Rt_) return;
|
|
if ( _Imm_ < 0 )
|
|
{
|
|
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], (u32)_Imm_ << 16 ); //U
|
|
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0xffffffff ); //V
|
|
}
|
|
else
|
|
{
|
|
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], (u32)_Imm_ << 16 ); //U
|
|
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 ); //V
|
|
}
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recMFHI( void )
|
|
{
|
|
|
|
if ( ! _Rd_ )
|
|
{
|
|
return;
|
|
}
|
|
|
|
MOVQMtoR( MM0, (int)&cpuRegs.HI.UD[ 0 ] );
|
|
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ], MM0 );
|
|
SetMMXstate();
|
|
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recMFLO( void )
|
|
{
|
|
|
|
if ( ! _Rd_ )
|
|
{
|
|
return;
|
|
}
|
|
|
|
MOVQMtoR( MM0, (int)&cpuRegs.LO.UD[ 0 ] );
|
|
MOVQRtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ], MM0 );
|
|
SetMMXstate();
|
|
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recMTHI( void )
|
|
{
|
|
|
|
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rs_ ].UD[ 0 ] );
|
|
MOVQRtoM( (int)&cpuRegs.HI.UD[ 0 ], MM0 );
|
|
SetMMXstate();
|
|
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recMTLO( void )
|
|
{
|
|
|
|
MOVQMtoR( MM0, (int)&cpuRegs.GPR.r[ _Rs_ ].UD[ 0 ] );
|
|
MOVQRtoM( (int)&cpuRegs.LO.UD[ 0 ], MM0 );
|
|
SetMMXstate();
|
|
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recMOVZ( void )
|
|
{
|
|
if ( ! _Rd_ )
|
|
{
|
|
return;
|
|
}
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
OR32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
|
|
j8Ptr[ 0 ] = JNZ8( 0 );
|
|
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
|
|
|
x86SetJ8( j8Ptr[ 0 ] );
|
|
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recMOVN( void )
|
|
{
|
|
if ( ! _Rd_ )
|
|
{
|
|
return;
|
|
}
|
|
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
OR32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
|
|
j8Ptr[ 0 ] = JZ8( 0 );
|
|
|
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], ECX );
|
|
|
|
x86SetJ8( j8Ptr[ 0 ] );
|
|
|
|
}
|
|
|
|
REC_FUNC( MFHI1 );
|
|
REC_FUNC( MFLO1 );
|
|
REC_FUNC( MTHI1 );
|
|
REC_FUNC( MTLO1 );
|
|
|
|
#endif
|