mirror of
https://github.com/PCSX2/pcsx2.git
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638e0b30f6
git-svn-id: http://pcsx2.googlecode.com/svn/branches/pcsx2_0.9.1@159 96395faa-99c1-11dd-bbfe-3dabce05a288
131 lines
3.6 KiB
C
131 lines
3.6 KiB
C
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2003 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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// recompiler reworked to add dynamic linking zerofrog(@gmail.com) Jan06
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#include <stdlib.h>
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#include <string.h>
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#include <assert.h>
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#include "Common.h"
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#include "InterTables.h"
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#include "ix86/ix86.h"
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#include "iR5900.h"
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#ifdef __WIN32__
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#pragma warning(disable:4244)
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#pragma warning(disable:4761)
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#endif
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/*********************************************************
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* Jump to target *
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* Format: OP target *
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*********************************************************/
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#ifndef JUMP_RECOMPILE
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REC_SYS(J);
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REC_SYS(JAL);
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REC_SYS(JR);
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REC_SYS(JALR);
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#else
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////////////////////////////////////////////////////
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void recJ( void )
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{
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// SET_FPUSTATE;
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u32 newpc = (_Target_ << 2) + ( pc & 0xf0000000 );
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recompileNextInstruction(1);
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SetBranchImm(newpc);
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}
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////////////////////////////////////////////////////
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void recJAL( void )
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{
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u32 newpc = (_Target_ << 2) + ( pc & 0xf0000000 );
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_deleteEEreg(31, 0);
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GPR_SET_CONST(31);
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g_cpuConstRegs[31].UL[0] = pc + 4;
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g_cpuConstRegs[31].UL[1] = 0;
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recompileNextInstruction(1);
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SetBranchImm(newpc);
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}
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/*********************************************************
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* Register jump *
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* Format: OP rs, rd *
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*********************************************************/
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////////////////////////////////////////////////////
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void recJR( void )
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{
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SetBranchReg( _Rs_);
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}
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////////////////////////////////////////////////////
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void recJALR( void )
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{
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_allocX86reg(ESI, X86TYPE_PCWRITEBACK, 0, MODE_WRITE);
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_eeMoveGPRtoR(ESI, _Rs_);
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// uncomment when there are NO instructions that need to call interpreter
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// int mmreg;
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// if( GPR_IS_CONST1(_Rs_) )
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// MOV32ItoM( (u32)&cpuRegs.pc, g_cpuConstRegs[_Rs_].UL[0] );
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// else {
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// int mmreg;
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//
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// if( (mmreg = _checkXMMreg(XMMTYPE_GPRREG, _Rs_, MODE_READ)) >= 0 ) {
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// SSE_MOVSS_XMM_to_M32((u32)&cpuRegs.pc, mmreg);
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// }
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// else if( (mmreg = _checkMMXreg(MMX_GPR+_Rs_, MODE_READ)) >= 0 ) {
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// MOVDMMXtoM((u32)&cpuRegs.pc, mmreg);
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// SetMMXstate();
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// }
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// else {
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// MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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// MOV32RtoM((u32)&cpuRegs.pc, EAX);
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// }
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// }
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if ( _Rd_ )
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{
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_deleteEEreg(_Rd_, 0);
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GPR_SET_CONST(_Rd_);
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g_cpuConstRegs[_Rd_].UL[0] = pc + 4;
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g_cpuConstRegs[_Rd_].UL[1] = 0;
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}
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_clearNeededMMXregs();
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_clearNeededXMMregs();
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recompileNextInstruction(1);
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if( x86regs[ESI].inuse ) {
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assert( x86regs[ESI].type == X86TYPE_PCWRITEBACK );
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MOV32RtoM((int)&cpuRegs.pc, ESI);
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x86regs[ESI].inuse = 0;
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}
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else {
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MOV32MtoR(EAX, (u32)&g_recWriteback);
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MOV32RtoM((int)&cpuRegs.pc, EAX);
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}
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SetBranchReg(0xffffffff);
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}
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#endif
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