mirror of
https://github.com/PCSX2/pcsx2.git
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638e0b30f6
git-svn-id: http://pcsx2.googlecode.com/svn/branches/pcsx2_0.9.1@159 96395faa-99c1-11dd-bbfe-3dabce05a288
1087 lines
No EOL
24 KiB
C
1087 lines
No EOL
24 KiB
C
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2003 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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// recompiler reworked to add dynamic linking zerofrog(@gmail.com) Jan06
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#include <stdlib.h>
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#include <string.h>
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#include <assert.h>
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#include "Common.h"
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#include "InterTables.h"
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#include "ix86/ix86.h"
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#include "iR5900.h"
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#ifdef __WIN32__
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#pragma warning(disable:4244)
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#pragma warning(disable:4761)
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#endif
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/*********************************************************
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* Register branch logic *
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* Format: OP rs, rt, offset *
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*********************************************************/
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#ifndef BRANCH_RECOMPILE
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REC_SYS(BEQ);
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REC_SYS(BEQL);
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REC_SYS(BNE);
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REC_SYS(BNEL);
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REC_SYS(BLTZ);
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REC_SYS(BGTZ);
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REC_SYS(BLEZ);
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REC_SYS(BGEZ);
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REC_SYS(BGTZL);
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REC_SYS(BLTZL);
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REC_SYS(BLTZAL);
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REC_SYS(BLTZALL);
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REC_SYS(BLEZL);
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REC_SYS(BGEZL);
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REC_SYS(BGEZAL);
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REC_SYS(BGEZALL);
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#else
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#if defined(EE_CONST_PROP)
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void recSetBranchEQ(int info, int bne, int process)
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{
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if( info & PROCESS_EE_MMX ) {
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int t0reg;
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SetMMXstate();
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if( process & PROCESS_CONSTS ) {
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if( (g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE) || !EEINST_ISLIVEMMX(_Rt_) ) {
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_deleteMMXreg(_Rt_, 1);
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mmxregs[EEREC_T].inuse = 0;
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t0reg = EEREC_T;
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}
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else {
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t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
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MOVQRtoR(t0reg, EEREC_T);
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}
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_flushConstReg(_Rs_);
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PCMPEQDMtoR(t0reg, (u32)&cpuRegs.GPR.r[_Rs_].UL[0]);
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if( t0reg != EEREC_T ) _freeMMXreg(t0reg);
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}
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else if( process & PROCESS_CONSTT ) {
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if( (g_pCurInstInfo->regs[_Rs_] & EEINST_LASTUSE) || !EEINST_ISLIVEMMX(_Rs_) ) {
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_deleteMMXreg(_Rs_, 1);
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mmxregs[EEREC_S].inuse = 0;
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t0reg = EEREC_S;
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}
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else {
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t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
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MOVQRtoR(t0reg, EEREC_S);
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}
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_flushConstReg(_Rt_);
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PCMPEQDMtoR(t0reg, (u32)&cpuRegs.GPR.r[_Rt_].UL[0]);
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if( t0reg != EEREC_S ) _freeMMXreg(t0reg);
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}
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else {
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if( (g_pCurInstInfo->regs[_Rs_] & EEINST_LASTUSE) || !EEINST_ISLIVEMMX(_Rs_) ) {
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_deleteMMXreg(_Rs_, 1);
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mmxregs[EEREC_S].inuse = 0;
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t0reg = EEREC_S;
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PCMPEQDRtoR(t0reg, EEREC_T);
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}
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else if( (g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE) || !EEINST_ISLIVEMMX(_Rt_) ) {
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_deleteMMXreg(_Rt_, 1);
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mmxregs[EEREC_T].inuse = 0;
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t0reg = EEREC_T;
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PCMPEQDRtoR(t0reg, EEREC_S);
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}
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else {
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t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
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MOVQRtoR(t0reg, EEREC_S);
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PCMPEQDRtoR(t0reg, EEREC_T);
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}
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if( t0reg != EEREC_S && t0reg != EEREC_T ) _freeMMXreg(t0reg);
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}
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PMOVMSKBMMXtoR(EAX, t0reg);
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_eeFlushAllUnused();
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CMP8ItoR( EAX, 0xff );
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if( bne ) j32Ptr[ 1 ] = JE32( 0 );
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else j32Ptr[ 0 ] = j32Ptr[ 1 ] = JNE32( 0 );
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}
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else if( info & PROCESS_EE_XMM ) {
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int t0reg;
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if( process & PROCESS_CONSTS ) {
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if( (g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE) || !EEINST_ISLIVEXMM(_Rt_) ) {
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_deleteGPRtoXMMreg(_Rt_, 1);
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xmmregs[EEREC_T].inuse = 0;
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t0reg = EEREC_T;
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}
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else {
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t0reg = _allocTempXMMreg(XMMT_INT, -1);
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SSE2_MOVQ_XMM_to_XMM(t0reg, EEREC_T);
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}
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_flushConstReg(_Rs_);
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SSE2_PCMPEQD_M128_to_XMM(t0reg, (u32)&cpuRegs.GPR.r[_Rs_].UL[0]);
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if( t0reg != EEREC_T ) _freeXMMreg(t0reg);
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}
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else if( process & PROCESS_CONSTT ) {
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if( (g_pCurInstInfo->regs[_Rs_] & EEINST_LASTUSE) || !EEINST_ISLIVEXMM(_Rs_) ) {
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_deleteGPRtoXMMreg(_Rs_, 1);
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xmmregs[EEREC_S].inuse = 0;
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t0reg = EEREC_S;
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}
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else {
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t0reg = _allocTempXMMreg(XMMT_INT, -1);
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SSE2_MOVQ_XMM_to_XMM(t0reg, EEREC_S);
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}
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_flushConstReg(_Rt_);
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SSE2_PCMPEQD_M128_to_XMM(t0reg, (u32)&cpuRegs.GPR.r[_Rt_].UL[0]);
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if( t0reg != EEREC_S ) _freeXMMreg(t0reg);
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}
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else {
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if( (g_pCurInstInfo->regs[_Rs_] & EEINST_LASTUSE) || !EEINST_ISLIVEXMM(_Rs_) ) {
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_deleteGPRtoXMMreg(_Rs_, 1);
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xmmregs[EEREC_S].inuse = 0;
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t0reg = EEREC_S;
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SSE2_PCMPEQD_XMM_to_XMM(t0reg, EEREC_T);
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}
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else if( (g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE) || !EEINST_ISLIVEXMM(_Rt_) ) {
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_deleteGPRtoXMMreg(_Rt_, 1);
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xmmregs[EEREC_T].inuse = 0;
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t0reg = EEREC_T;
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SSE2_PCMPEQD_XMM_to_XMM(t0reg, EEREC_S);
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}
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else {
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t0reg = _allocTempXMMreg(XMMT_INT, -1);
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SSE2_MOVQ_XMM_to_XMM(t0reg, EEREC_S);
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SSE2_PCMPEQD_XMM_to_XMM(t0reg, EEREC_T);
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}
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if( t0reg != EEREC_S && t0reg != EEREC_T ) _freeXMMreg(t0reg);
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}
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SSE_MOVMSKPS_XMM_to_R32(EAX, t0reg);
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_eeFlushAllUnused();
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AND8ItoR(EAX, 3);
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CMP8ItoR( EAX, 0x3 );
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if( bne ) j32Ptr[ 1 ] = JE32( 0 );
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else j32Ptr[ 0 ] = j32Ptr[ 1 ] = JNE32( 0 );
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}
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else {
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_eeFlushAllUnused();
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if( bne ) {
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if( process & PROCESS_CONSTS ) {
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CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], g_cpuConstRegs[_Rs_].UL[0] );
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j8Ptr[ 0 ] = JNE8( 0 );
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CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], g_cpuConstRegs[_Rs_].UL[1] );
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j32Ptr[ 1 ] = JE32( 0 );
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}
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else if( process & PROCESS_CONSTT ) {
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CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], g_cpuConstRegs[_Rt_].UL[0] );
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j8Ptr[ 0 ] = JNE8( 0 );
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CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], g_cpuConstRegs[_Rt_].UL[1] );
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j32Ptr[ 1 ] = JE32( 0 );
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}
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else {
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MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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CMP32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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j8Ptr[ 0 ] = JNE8( 0 );
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MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
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CMP32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
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j32Ptr[ 1 ] = JE32( 0 );
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}
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x86SetJ8( j8Ptr[0] );
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}
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else {
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// beq
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if( process & PROCESS_CONSTS ) {
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CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], g_cpuConstRegs[_Rs_].UL[0] );
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j32Ptr[ 0 ] = JNE32( 0 );
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CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], g_cpuConstRegs[_Rs_].UL[1] );
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j32Ptr[ 1 ] = JNE32( 0 );
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}
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else if( process & PROCESS_CONSTT ) {
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CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], g_cpuConstRegs[_Rt_].UL[0] );
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j32Ptr[ 0 ] = JNE32( 0 );
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CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], g_cpuConstRegs[_Rt_].UL[1] );
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j32Ptr[ 1 ] = JNE32( 0 );
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}
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else {
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MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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CMP32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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j32Ptr[ 0 ] = JNE32( 0 );
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MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
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CMP32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
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j32Ptr[ 1 ] = JNE32( 0 );
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}
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}
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}
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_clearNeededMMXregs();
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_clearNeededXMMregs();
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}
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void recSetBranchL(int ltz)
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{
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int regs = _checkMMXreg(MMX_GPR+_Rs_, MODE_READ);
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if( regs >= 0 ) {
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int t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
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SetMMXstate();
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PXORRtoR(t0reg, t0reg);
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PCMPGTDRtoR(t0reg, regs);
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PMOVMSKBMMXtoR(EAX, t0reg);
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_freeMMXreg(t0reg);
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_eeFlushAllUnused();
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TEST8ItoR( EAX, 0x80 );
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if( ltz ) j32Ptr[ 0 ] = JZ32( 0 );
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else j32Ptr[ 0 ] = JNZ32( 0 );
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return;
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}
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regs = _checkXMMreg(XMMTYPE_GPRREG, _Rs_, MODE_READ);
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if( regs >= 0 ) {
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int t0reg = _allocTempXMMreg(XMMT_INT, -1);
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SSE_XORPS_XMM_to_XMM(t0reg, t0reg);
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SSE2_PCMPGTD_XMM_to_XMM(t0reg, regs);
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SSE_MOVMSKPS_XMM_to_R32(EAX, t0reg);
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_freeXMMreg(t0reg);
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_eeFlushAllUnused();
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TEST8ItoR( EAX, 2 );
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if( ltz ) j32Ptr[ 0 ] = JZ32( 0 );
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else j32Ptr[ 0 ] = JNZ32( 0 );
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return;
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}
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CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], 0 );
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if( ltz ) j32Ptr[ 0 ] = JGE32( 0 );
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else j32Ptr[ 0 ] = JL32( 0 );
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_clearNeededMMXregs();
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_clearNeededXMMregs();
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}
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//// BEQ
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void recBEQ_const()
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{
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u32 branchTo;
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if( g_cpuConstRegs[_Rs_].SD[0] == g_cpuConstRegs[_Rt_].SD[0] )
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branchTo = ((s32)_Imm_ * 4) + pc;
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else
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branchTo = pc+4;
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recompileNextInstruction(1);
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SetBranchImm( branchTo );
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}
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void recBEQ_process(int info, int process)
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{
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u32 branchTo = ((s32)_Imm_ * 4) + pc;
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if ( _Rs_ == _Rt_ )
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{
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recompileNextInstruction(1);
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SetBranchImm( branchTo );
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}
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else
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{
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recSetBranchEQ(info, 0, process);
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SaveBranchState();
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recompileNextInstruction(1);
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SetBranchImm(branchTo);
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x86SetJ32( j32Ptr[ 0 ] );
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x86SetJ32( j32Ptr[ 1 ] );
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// recopy the next inst
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pc -= 4;
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LoadBranchState();
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recompileNextInstruction(1);
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SetBranchImm(pc);
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}
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}
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void recBEQ_(int info) { recBEQ_process(info, 0); }
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void recBEQ_consts(int info) { recBEQ_process(info, PROCESS_CONSTS); }
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void recBEQ_constt(int info) { recBEQ_process(info, PROCESS_CONSTT); }
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EERECOMPILE_CODE0(BEQ, XMMINFO_READS|XMMINFO_READT);
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//// BNE
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void recBNE_const()
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{
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u32 branchTo;
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if( g_cpuConstRegs[_Rs_].SD[0] != g_cpuConstRegs[_Rt_].SD[0] )
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branchTo = ((s32)_Imm_ * 4) + pc;
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else
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branchTo = pc+4;
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recompileNextInstruction(1);
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SetBranchImm( branchTo );
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}
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void recBNE_process(int info, int process)
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{
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u32 branchTo = ((s32)_Imm_ * 4) + pc;
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if ( _Rs_ == _Rt_ )
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{
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recompileNextInstruction(1);
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SetBranchImm(pc);
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return;
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}
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recSetBranchEQ(info, 1, process);
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SaveBranchState();
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recompileNextInstruction(1);
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SetBranchImm(branchTo);
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x86SetJ32( j32Ptr[ 1 ] );
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// recopy the next inst
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pc -= 4;
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LoadBranchState();
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recompileNextInstruction(1);
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SetBranchImm(pc);
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}
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void recBNE_(int info) { recBNE_process(info, 0); }
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void recBNE_consts(int info) { recBNE_process(info, PROCESS_CONSTS); }
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void recBNE_constt(int info) { recBNE_process(info, PROCESS_CONSTT); }
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EERECOMPILE_CODE0(BNE, XMMINFO_READS|XMMINFO_READT);
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//// BEQL
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void recBEQL_const()
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{
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if( g_cpuConstRegs[_Rs_].SD[0] == g_cpuConstRegs[_Rt_].SD[0] ) {
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u32 branchTo = ((s32)_Imm_ * 4) + pc;
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recompileNextInstruction(1);
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SetBranchImm( branchTo );
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}
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else {
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SetBranchImm( pc+4 );
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}
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}
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void recBEQL_process(int info, int process)
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{
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u32 branchTo = ((s32)_Imm_ * 4) + pc;
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recSetBranchEQ(info, 0, process);
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SaveBranchState();
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recompileNextInstruction(1);
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SetBranchImm(branchTo);
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x86SetJ32( j32Ptr[ 0 ] );
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x86SetJ32( j32Ptr[ 1 ] );
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LoadBranchState();
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SetBranchImm(pc);
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}
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void recBEQL_(int info) { recBEQL_process(info, 0); }
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void recBEQL_consts(int info) { recBEQL_process(info, PROCESS_CONSTS); }
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void recBEQL_constt(int info) { recBEQL_process(info, PROCESS_CONSTT); }
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EERECOMPILE_CODE0(BEQL, XMMINFO_READS|XMMINFO_READT);
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//// BNEL
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void recBNEL_const()
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{
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if( g_cpuConstRegs[_Rs_].SD[0] != g_cpuConstRegs[_Rt_].SD[0] ) {
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u32 branchTo = ((s32)_Imm_ * 4) + pc;
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recompileNextInstruction(1);
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SetBranchImm(branchTo);
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}
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else {
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SetBranchImm( pc+4 );
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}
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}
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void recBNEL_process(int info, int process)
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{
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u32 branchTo = ((s32)_Imm_ * 4) + pc;
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recSetBranchEQ(info, 0, process);
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|
|
SaveBranchState();
|
|
SetBranchImm(pc+4);
|
|
|
|
x86SetJ32( j32Ptr[ 0 ] );
|
|
x86SetJ32( j32Ptr[ 1 ] );
|
|
|
|
// recopy the next inst
|
|
LoadBranchState();
|
|
recompileNextInstruction(1);
|
|
SetBranchImm(branchTo);
|
|
}
|
|
|
|
void recBNEL_(int info) { recBNEL_process(info, 0); }
|
|
void recBNEL_consts(int info) { recBNEL_process(info, PROCESS_CONSTS); }
|
|
void recBNEL_constt(int info) { recBNEL_process(info, PROCESS_CONSTT); }
|
|
|
|
EERECOMPILE_CODE0(BNEL, XMMINFO_READS|XMMINFO_READT);
|
|
|
|
/*********************************************************
|
|
* Register branch logic *
|
|
* Format: OP rs, offset *
|
|
*********************************************************/
|
|
|
|
////////////////////////////////////////////////////
|
|
//void recBLTZAL( void )
|
|
//{
|
|
// SysPrintf("BLTZAL\n");
|
|
// _eeFlushAllUnused();
|
|
// MOV32ItoM( (int)&cpuRegs.code, cpuRegs.code );
|
|
// MOV32ItoM( (int)&cpuRegs.pc, pc );
|
|
// iFlushCall(FLUSH_EVERYTHING);
|
|
// CALLFunc( (int)BLTZAL );
|
|
// branch = 2;
|
|
//}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recBLTZAL(int info)
|
|
{
|
|
u32 branchTo = ((s32)_Imm_ * 4) + pc;
|
|
|
|
SysPrintf("BLTZAL\n");
|
|
_eeOnWriteReg(31, 0);
|
|
_eeFlushAllUnused();
|
|
|
|
_deleteEEreg(31, 0);
|
|
MOV32ItoM((u32)&cpuRegs.GPR.r[31].UL[0], pc+4);
|
|
MOV32ItoM((u32)&cpuRegs.GPR.r[31].UL[1], 0);
|
|
|
|
if( GPR_IS_CONST1(_Rs_) ) {
|
|
if( !(g_cpuConstRegs[_Rs_].SD[0] < 0) )
|
|
branchTo = pc+4;
|
|
|
|
recompileNextInstruction(1);
|
|
SetBranchImm( branchTo );
|
|
return;
|
|
}
|
|
|
|
recSetBranchL(1);
|
|
|
|
SaveBranchState();
|
|
|
|
recompileNextInstruction(1);
|
|
|
|
SetBranchImm(branchTo);
|
|
|
|
x86SetJ32( j32Ptr[ 0 ] );
|
|
|
|
// recopy the next inst
|
|
pc -= 4;
|
|
LoadBranchState();
|
|
recompileNextInstruction(1);
|
|
|
|
SetBranchImm(pc);
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recBGEZAL( void )
|
|
{
|
|
SysPrintf("BGEZAL\n");
|
|
_eeFlushAllUnused();
|
|
MOV32ItoM( (int)&cpuRegs.code, cpuRegs.code );
|
|
MOV32ItoM( (int)&cpuRegs.pc, pc );
|
|
iFlushCall(FLUSH_EVERYTHING);
|
|
CALLFunc( (int)BGEZAL );
|
|
branch = 2;
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recBLTZALL( void )
|
|
{
|
|
SysPrintf("BLTZALL\n");
|
|
_eeFlushAllUnused();
|
|
MOV32ItoM( (int)&cpuRegs.code, cpuRegs.code );
|
|
MOV32ItoM( (int)&cpuRegs.pc, pc );
|
|
iFlushCall(FLUSH_EVERYTHING);
|
|
CALLFunc( (int)BLTZALL );
|
|
branch = 2;
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recBGEZALL( void )
|
|
{
|
|
SysPrintf("BGEZALL\n");
|
|
_eeFlushAllUnused();
|
|
MOV32ItoM( (int)&cpuRegs.code, cpuRegs.code );
|
|
MOV32ItoM( (int)&cpuRegs.pc, pc );
|
|
iFlushCall(FLUSH_EVERYTHING);
|
|
CALLFunc( (int)BGEZALL );
|
|
branch = 2;
|
|
}
|
|
|
|
#else
|
|
|
|
|
|
////////////////////////////////////////////////////
|
|
void recBEQ( void )
|
|
{
|
|
u32 branchTo = ((s32)_Imm_ * 4) + pc;
|
|
|
|
if ( _Rs_ == _Rt_ )
|
|
{
|
|
_clearNeededMMXregs();
|
|
_clearNeededXMMregs();
|
|
recompileNextInstruction(1);
|
|
SetBranchImm( branchTo );
|
|
}
|
|
else
|
|
{
|
|
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
CMP32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
j32Ptr[ 0 ] = JNE32( 0 );
|
|
|
|
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
|
|
CMP32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
|
|
j32Ptr[ 1 ] = JNE32( 0 );
|
|
|
|
_clearNeededMMXregs();
|
|
_clearNeededXMMregs();
|
|
|
|
SaveBranchState();
|
|
recompileNextInstruction(1);
|
|
|
|
SetBranchImm(branchTo);
|
|
|
|
x86SetJ32( j32Ptr[ 0 ] );
|
|
x86SetJ32( j32Ptr[ 1 ] );
|
|
|
|
// recopy the next inst
|
|
pc -= 4;
|
|
LoadBranchState();
|
|
recompileNextInstruction(1);
|
|
|
|
SetBranchImm(pc);
|
|
}
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recBNE( void )
|
|
{
|
|
u32 branchTo = ((s32)_Imm_ * 4) + pc;
|
|
|
|
if ( _Rs_ == _Rt_ )
|
|
{
|
|
_clearNeededMMXregs();
|
|
_clearNeededXMMregs();
|
|
recompileNextInstruction(1);
|
|
SetBranchImm(pc);
|
|
return;
|
|
}
|
|
|
|
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
CMP32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
j32Ptr[ 0 ] = JNE32( 0 );
|
|
|
|
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
|
|
CMP32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
|
|
j32Ptr[ 1 ] = JE32( 0 );
|
|
|
|
x86SetJ32( j32Ptr[ 0 ] );
|
|
|
|
_clearNeededMMXregs();
|
|
_clearNeededXMMregs();
|
|
|
|
SaveBranchState();
|
|
recompileNextInstruction(1);
|
|
|
|
SetBranchImm(branchTo);
|
|
|
|
x86SetJ32( j32Ptr[ 1 ] );
|
|
|
|
// recopy the next inst
|
|
pc -= 4;
|
|
LoadBranchState();
|
|
recompileNextInstruction(1);
|
|
|
|
SetBranchImm(pc);
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recBEQL( void )
|
|
{
|
|
u32 branchTo = ((s32)_Imm_ * 4) + pc;
|
|
|
|
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
CMP32RtoR( ECX, EDX );
|
|
j32Ptr[ 0 ] = JNE32( 0 );
|
|
|
|
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
|
|
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
|
|
CMP32RtoR( ECX, EDX );
|
|
j32Ptr[ 1 ] = JNE32( 0 );
|
|
|
|
_clearNeededMMXregs();
|
|
_clearNeededXMMregs();
|
|
|
|
SaveBranchState();
|
|
recompileNextInstruction(1);
|
|
SetBranchImm(branchTo);
|
|
|
|
x86SetJ32( j32Ptr[ 0 ] );
|
|
x86SetJ32( j32Ptr[ 1 ] );
|
|
|
|
LoadBranchState();
|
|
SetBranchImm(pc);
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recBNEL( void )
|
|
{
|
|
u32 branchTo = ((s32)_Imm_ * 4) + pc;
|
|
|
|
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
CMP32RtoR( ECX, EDX );
|
|
j32Ptr[ 0 ] = JNE32( 0 );
|
|
|
|
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
|
|
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
|
|
CMP32RtoR( ECX, EDX );
|
|
j32Ptr[ 1 ] = JNE32( 0 );
|
|
|
|
_clearNeededMMXregs();
|
|
_clearNeededXMMregs();
|
|
|
|
SaveBranchState();
|
|
SetBranchImm(pc+4);
|
|
|
|
x86SetJ32( j32Ptr[ 0 ] );
|
|
x86SetJ32( j32Ptr[ 1 ] );
|
|
|
|
// recopy the next inst
|
|
LoadBranchState();
|
|
recompileNextInstruction(1);
|
|
SetBranchImm(branchTo);
|
|
}
|
|
|
|
/*********************************************************
|
|
* Register branch logic *
|
|
* Format: OP rs, offset *
|
|
*********************************************************/
|
|
|
|
////////////////////////////////////////////////////
|
|
void recBLTZAL( void )
|
|
{
|
|
MOV32ItoM( (int)&cpuRegs.code, cpuRegs.code );
|
|
MOV32ItoM( (int)&cpuRegs.pc, pc );
|
|
iFlushCall(FLUSH_EVERYTHING);
|
|
CALLFunc( (int)BLTZAL );
|
|
branch = 2;
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recBGEZAL( void )
|
|
{
|
|
MOV32ItoM( (int)&cpuRegs.code, cpuRegs.code );
|
|
MOV32ItoM( (int)&cpuRegs.pc, pc );
|
|
iFlushCall(FLUSH_EVERYTHING);
|
|
CALLFunc( (int)BGEZAL );
|
|
branch = 2;
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recBLTZALL( void )
|
|
{
|
|
SysPrintf("BLTZALL\n");
|
|
MOV32ItoM( (int)&cpuRegs.code, cpuRegs.code );
|
|
MOV32ItoM( (int)&cpuRegs.pc, pc );
|
|
iFlushCall(FLUSH_EVERYTHING);
|
|
CALLFunc( (int)BLTZALL );
|
|
branch = 2;
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recBGEZALL( void )
|
|
{
|
|
SysPrintf("BGEZALL\n");
|
|
MOV32ItoM( (int)&cpuRegs.code, cpuRegs.code );
|
|
MOV32ItoM( (int)&cpuRegs.pc, pc );
|
|
iFlushCall(FLUSH_EVERYTHING);
|
|
CALLFunc( (int)BGEZALL );
|
|
branch = 2;
|
|
}
|
|
|
|
#endif
|
|
|
|
//// BLEZ
|
|
void recBLEZ( void )
|
|
{
|
|
u32 branchTo = ((s32)_Imm_ * 4) + pc;
|
|
|
|
_eeFlushAllUnused();
|
|
|
|
if( GPR_IS_CONST1(_Rs_) ) {
|
|
if( !(g_cpuConstRegs[_Rs_].SD[0] <= 0) )
|
|
branchTo = pc+4;
|
|
|
|
recompileNextInstruction(1);
|
|
SetBranchImm( branchTo );
|
|
return;
|
|
}
|
|
|
|
_deleteEEreg(_Rs_, 1);
|
|
|
|
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], 0 );
|
|
j8Ptr[ 0 ] = JL8( 0 );
|
|
j32Ptr[ 1 ] = JG32( 0 );
|
|
|
|
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], 0 );
|
|
j32Ptr[ 2 ] = JNZ32( 0 );
|
|
|
|
x86SetJ8( j8Ptr[ 0 ] );
|
|
|
|
_clearNeededMMXregs();
|
|
_clearNeededXMMregs();
|
|
|
|
SaveBranchState();
|
|
recompileNextInstruction(1);
|
|
|
|
SetBranchImm(branchTo);
|
|
|
|
x86SetJ32( j32Ptr[ 1 ] );
|
|
x86SetJ32( j32Ptr[ 2 ] );
|
|
|
|
// recopy the next inst
|
|
pc -= 4;
|
|
LoadBranchState();
|
|
recompileNextInstruction(1);
|
|
|
|
SetBranchImm(pc);
|
|
}
|
|
|
|
//// BGTZ
|
|
void recBGTZ( void )
|
|
{
|
|
u32 branchTo = ((s32)_Imm_ * 4) + pc;
|
|
|
|
_eeFlushAllUnused();
|
|
|
|
if( GPR_IS_CONST1(_Rs_) ) {
|
|
if( !(g_cpuConstRegs[_Rs_].SD[0] > 0) )
|
|
branchTo = pc+4;
|
|
|
|
recompileNextInstruction(1);
|
|
SetBranchImm( branchTo );
|
|
return;
|
|
}
|
|
|
|
_deleteEEreg(_Rs_, 1);
|
|
|
|
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], 0 );
|
|
j8Ptr[ 0 ] = JG8( 0 );
|
|
j32Ptr[ 1 ] = JL32( 0 );
|
|
|
|
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], 0 );
|
|
j32Ptr[ 2 ] = JZ32( 0 );
|
|
|
|
x86SetJ8( j8Ptr[ 0 ] );
|
|
|
|
_clearNeededMMXregs();
|
|
_clearNeededXMMregs();
|
|
|
|
SaveBranchState();
|
|
recompileNextInstruction(1);
|
|
|
|
SetBranchImm(branchTo);
|
|
|
|
x86SetJ32( j32Ptr[ 1 ] );
|
|
x86SetJ32( j32Ptr[ 2 ] );
|
|
|
|
// recopy the next inst
|
|
pc -= 4;
|
|
LoadBranchState();
|
|
recompileNextInstruction(1);
|
|
|
|
SetBranchImm(pc);
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recBLTZ()
|
|
{
|
|
u32 branchTo = ((s32)_Imm_ * 4) + pc;
|
|
|
|
_eeFlushAllUnused();
|
|
|
|
if( GPR_IS_CONST1(_Rs_) ) {
|
|
if( !(g_cpuConstRegs[_Rs_].SD[0] < 0) )
|
|
branchTo = pc+4;
|
|
|
|
recompileNextInstruction(1);
|
|
SetBranchImm( branchTo );
|
|
return;
|
|
}
|
|
|
|
recSetBranchL(1);
|
|
|
|
SaveBranchState();
|
|
recompileNextInstruction(1);
|
|
|
|
SetBranchImm(branchTo);
|
|
|
|
x86SetJ32( j32Ptr[ 0 ] );
|
|
|
|
// recopy the next inst
|
|
pc -= 4;
|
|
LoadBranchState();
|
|
recompileNextInstruction(1);
|
|
|
|
SetBranchImm(pc);
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recBGEZ( void )
|
|
{
|
|
u32 branchTo = ((s32)_Imm_ * 4) + pc;
|
|
|
|
_eeFlushAllUnused();
|
|
|
|
if( GPR_IS_CONST1(_Rs_) ) {
|
|
if( !(g_cpuConstRegs[_Rs_].SD[0] >= 0) )
|
|
branchTo = pc+4;
|
|
|
|
recompileNextInstruction(1);
|
|
SetBranchImm( branchTo );
|
|
return;
|
|
}
|
|
|
|
recSetBranchL(0);
|
|
|
|
SaveBranchState();
|
|
recompileNextInstruction(1);
|
|
|
|
SetBranchImm(branchTo);
|
|
|
|
x86SetJ32( j32Ptr[ 0 ] );
|
|
|
|
// recopy the next inst
|
|
pc -= 4;
|
|
LoadBranchState();
|
|
recompileNextInstruction(1);
|
|
|
|
SetBranchImm(pc);
|
|
}
|
|
|
|
/*********************************************************
|
|
* Register branch logic Likely *
|
|
* Format: OP rs, offset *
|
|
*********************************************************/
|
|
|
|
////////////////////////////////////////////////////
|
|
void recBLEZL( void )
|
|
{
|
|
u32 branchTo = ((s32)_Imm_ * 4) + pc;
|
|
|
|
_eeFlushAllUnused();
|
|
|
|
if( GPR_IS_CONST1(_Rs_) ) {
|
|
if( !(g_cpuConstRegs[_Rs_].SD[0] <= 0) )
|
|
SetBranchImm( pc + 4);
|
|
else {
|
|
_clearNeededMMXregs();
|
|
_clearNeededXMMregs();
|
|
recompileNextInstruction(1);
|
|
SetBranchImm( branchTo );
|
|
}
|
|
return;
|
|
}
|
|
|
|
_deleteEEreg(_Rs_, 1);
|
|
|
|
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], 0 );
|
|
j32Ptr[ 0 ] = JL32( 0 );
|
|
j32Ptr[ 1 ] = JG32( 0 );
|
|
|
|
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], 0 );
|
|
j32Ptr[ 2 ] = JNZ32( 0 );
|
|
|
|
x86SetJ32( j32Ptr[ 0 ] );
|
|
|
|
_clearNeededMMXregs();
|
|
_clearNeededXMMregs();
|
|
|
|
SaveBranchState();
|
|
recompileNextInstruction(1);
|
|
SetBranchImm(branchTo);
|
|
|
|
x86SetJ32( j32Ptr[ 1 ] );
|
|
x86SetJ32( j32Ptr[ 2 ] );
|
|
|
|
LoadBranchState();
|
|
SetBranchImm(pc);
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recBGTZL( void )
|
|
{
|
|
u32 branchTo = ((s32)_Imm_ * 4) + pc;
|
|
|
|
_eeFlushAllUnused();
|
|
|
|
if( GPR_IS_CONST1(_Rs_) ) {
|
|
if( !(g_cpuConstRegs[_Rs_].SD[0] > 0) )
|
|
SetBranchImm( pc + 4);
|
|
else {
|
|
_clearNeededMMXregs();
|
|
_clearNeededXMMregs();
|
|
recompileNextInstruction(1);
|
|
SetBranchImm( branchTo );
|
|
}
|
|
return;
|
|
}
|
|
|
|
_deleteEEreg(_Rs_, 1);
|
|
|
|
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], 0 );
|
|
j32Ptr[ 0 ] = JG32( 0 );
|
|
j32Ptr[ 1 ] = JL32( 0 );
|
|
|
|
CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], 0 );
|
|
j32Ptr[ 2 ] = JZ32( 0 );
|
|
|
|
x86SetJ32( j32Ptr[ 0 ] );
|
|
|
|
_clearNeededMMXregs();
|
|
_clearNeededXMMregs();
|
|
|
|
SaveBranchState();
|
|
recompileNextInstruction(1);
|
|
SetBranchImm(branchTo);
|
|
|
|
x86SetJ32( j32Ptr[ 1 ] );
|
|
x86SetJ32( j32Ptr[ 2 ] );
|
|
|
|
LoadBranchState();
|
|
SetBranchImm(pc);
|
|
}
|
|
|
|
////////////////////////////////////////////////////
|
|
void recBLTZL( void )
|
|
{
|
|
u32 branchTo = ((s32)_Imm_ * 4) + pc;
|
|
|
|
_eeFlushAllUnused();
|
|
|
|
if( GPR_IS_CONST1(_Rs_) ) {
|
|
if( !(g_cpuConstRegs[_Rs_].SD[0] < 0) )
|
|
SetBranchImm( pc + 4);
|
|
else {
|
|
recompileNextInstruction(1);
|
|
SetBranchImm( branchTo );
|
|
}
|
|
return;
|
|
}
|
|
|
|
recSetBranchL(1);
|
|
|
|
SaveBranchState();
|
|
recompileNextInstruction(1);
|
|
SetBranchImm(branchTo);
|
|
|
|
x86SetJ32( j32Ptr[ 0 ] );
|
|
|
|
LoadBranchState();
|
|
SetBranchImm(pc);
|
|
}
|
|
|
|
|
|
////////////////////////////////////////////////////
|
|
void recBGEZL( void )
|
|
{
|
|
u32 branchTo = ((s32)_Imm_ * 4) + pc;
|
|
|
|
_eeFlushAllUnused();
|
|
|
|
if( GPR_IS_CONST1(_Rs_) ) {
|
|
if( !(g_cpuConstRegs[_Rs_].SD[0] >= 0) )
|
|
SetBranchImm( pc + 4);
|
|
else {
|
|
recompileNextInstruction(1);
|
|
SetBranchImm( branchTo );
|
|
}
|
|
return;
|
|
}
|
|
|
|
recSetBranchL(0);
|
|
|
|
SaveBranchState();
|
|
recompileNextInstruction(1);
|
|
SetBranchImm(branchTo);
|
|
|
|
x86SetJ32( j32Ptr[ 0 ] );
|
|
|
|
LoadBranchState();
|
|
SetBranchImm(pc);
|
|
}
|
|
|
|
#endif |