mirror of
https://github.com/PCSX2/pcsx2.git
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638e0b30f6
git-svn-id: http://pcsx2.googlecode.com/svn/branches/pcsx2_0.9.1@159 96395faa-99c1-11dd-bbfe-3dabce05a288
616 lines
15 KiB
C
616 lines
15 KiB
C
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2004 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <string.h>
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#include <malloc.h>
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#include <xmmintrin.h>
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#include <emmintrin.h>
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#include "Common.h"
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#include "PsxCommon.h"
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#include "Sif.h"
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#include "Sifcmd.h"
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#define sif0dma ((DMACh*)&PS2MEM_HW[0xc000])
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#define sif1dma ((DMACh*)&PS2MEM_HW[0xc400])
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#define sif2dma ((DMACh*)&PS2MEM_HW[0xc800])
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#define FIFO_SIF0_W 128
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#define FIFO_SIF1_W 128
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typedef struct {
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u32 fifoData[FIFO_SIF0_W];
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int fifoReadPos;
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int fifoWritePos;
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int fifoSize;
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int chain;
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int end;
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int tagMode;
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int counter;
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struct sifData sifData;
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} _sif0;
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typedef struct {
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u32 fifoData[FIFO_SIF1_W];
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int fifoReadPos;
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int fifoWritePos;
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int fifoSize;
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int chain;
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int end;
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int tagMode;
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int counter;
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} _sif1;
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_sif0 sif0;
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_sif1 sif1;
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int sifInit() {
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memset(&sif0, 0, sizeof(sif0));
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memset(&sif1, 0, sizeof(sif1));
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return 0;
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}
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void SIF0write(u32 *from, int words)
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{
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if(words > (FIFO_SIF0_W-sif0.fifoWritePos)) {
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int wP0 = (FIFO_SIF0_W-sif0.fifoWritePos);
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int wP1 = words - wP0;
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memcpy_amd(&sif0.fifoData[sif0.fifoWritePos], from, wP0 << 2);
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memcpy_amd(&sif0.fifoData[0], &from[wP0], wP1 << 2);
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sif0.fifoWritePos = wP1;
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}
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else
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{
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memcpy_amd(&sif0.fifoData[sif0.fifoWritePos], from, words << 2);
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sif0.fifoWritePos += words;
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}
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sif0.fifoSize += words;
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#ifdef SIF_LOG
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SIF_LOG(" SIF0 + %d = %d (pos=%d)\n", words, sif0.fifoSize, sif0.fifoWritePos);
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#endif
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/* if (sif0.fifoSize == FIFO_SIF0_W) {
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Cpu->ExecuteBlock();
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}*/
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}
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void SIF0read(u32 *to, int words)
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{
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if(words > (FIFO_SIF0_W-sif0.fifoReadPos))
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{
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int wP0 = (FIFO_SIF0_W-sif0.fifoReadPos);
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int wP1 = words - wP0;
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memcpy_amd(to, &sif0.fifoData[sif0.fifoReadPos], wP0 << 2);
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memcpy_amd(&to[wP0], &sif0.fifoData[0], wP1 << 2);
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sif0.fifoReadPos = wP1;
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}
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else
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{
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memcpy_amd(to, &sif0.fifoData[sif0.fifoReadPos], words << 2);
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sif0.fifoReadPos += words;
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}
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sif0.fifoSize -= words;
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#ifdef SIF_LOG
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SIF_LOG(" SIF0 - %d = %d (pos=%d)\n", words, sif0.fifoSize, sif0.fifoReadPos);
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#endif
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}
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void SIF1write(u32 *from, int words)
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{
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if(words > (FIFO_SIF1_W-sif1.fifoWritePos))
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{
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int wP0 = (FIFO_SIF1_W-sif1.fifoWritePos);
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int wP1 = words - wP0;
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memcpy_amd(&sif1.fifoData[sif1.fifoWritePos], from, wP0 << 2);
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memcpy_amd(&sif1.fifoData[0], &from[wP0], wP1 << 2);
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sif1.fifoWritePos = wP1;
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}
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else
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{
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memcpy_amd(&sif1.fifoData[sif1.fifoWritePos], from, words << 2);
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sif1.fifoWritePos += words;
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}
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sif1.fifoSize += words;
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#ifdef SIF_LOG
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SIF_LOG(" SIF1 + %d = %d (pos=%d)\n", words, sif1.fifoSize, sif1.fifoWritePos);
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#endif
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/* if (sif1.fifoSize == FIFO_SIF1_W) {
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psxCpu->ExecuteBlock();
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}*/
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}
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void SIF1read(u32 *to, int words)
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{
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if(words > (FIFO_SIF1_W-sif1.fifoReadPos))
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{
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int wP0 = (FIFO_SIF1_W-sif1.fifoReadPos);
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int wP1 = words - wP0;
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memcpy_amd(to, &sif1.fifoData[sif1.fifoReadPos], wP0 << 2);
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memcpy_amd(&to[wP0], &sif1.fifoData[0], wP1 << 2);
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sif1.fifoReadPos = wP1;
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}
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else
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{
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memcpy_amd(to, &sif1.fifoData[sif1.fifoReadPos], words << 2);
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sif1.fifoReadPos += words;
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}
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sif1.fifoSize -= words;
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#ifdef SIF_LOG
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SIF_LOG(" SIF1 - %d = %d (pos=%d)\n", words, sif1.fifoSize, sif1.fifoReadPos);
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#endif
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}
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void SIF0Dma()
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{
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u32 *ptag;
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int notDone;
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//int cycles = 0, psxCycles = 0;
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#ifdef SIF_LOG
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SIF_LOG("SIF0 DMA start...\n");
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#endif
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do
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{
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notDone = 0;
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if(HW_DMA9_CHCR & 0x01000000) // If EE SIF0 is enabled
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{
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int size = sif0.counter; //HW_DMA9_BCR >> 16;
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if(size == 0) // If there's no more to transfer
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{
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// Note.. add normal mode here
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if (sif0.sifData.data & 0xC0000000) // If NORMAL mode or end of CHAIN, or interrupt then stop DMA
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{
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#ifdef SIF_LOG
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SIF_LOG(" IOP SIF Stopped\n");
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#endif
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// Stop & signal interrupts on IOP
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HW_DMA9_CHCR &= ~0x01000000; //reset TR flag
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psxDmaInterrupt2(2);
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//hwIntcIrq(INTC_SBUS);
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sif0.sifData.data = 0;
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}
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else if(FIFO_SIF1_W-sif0.fifoSize >= 2) // Chain mode
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{
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// Process DMA tag at HW_DMA9_TADR
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sif0.sifData = *(struct sifData *)PSXM(HW_DMA9_TADR);
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sif0.sifData.words = (sif0.sifData.words + 3) & 0xfffffffc; // Round up to nearest 4.
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SIF0write((u32*)PSXM(HW_DMA9_TADR+8), 4);
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//psxCycles += 2;
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HW_DMA9_MADR = sif0.sifData.data & 0xFFFFFF;
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HW_DMA9_TADR += 16; ///HW_DMA9_MADR + 16 + sif0.sifData.words << 2;
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//HW_DMA9_BCR = (sif0.sifData.words << 16) | 1;
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sif0.counter = sif0.sifData.words & 0xFFFFFF;
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notDone = 1;
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#ifdef SIF_LOG
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SIF_LOG(" SIF0 Tag: madr=%lx, tadr=%lx, counter=%lx (%08X_%08X)\n", HW_DMA9_MADR, HW_DMA9_TADR, sif0.counter, sif0.sifData.words, sif0.sifData.data);
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#endif
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if(sif0.sifData.data & 0x40000000)
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{
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#ifdef SIF_LOG
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SIF_LOG(" END\n");
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#endif
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}
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else
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{
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#ifdef SIF_LOG
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SIF_LOG(" CNT %08X, %08X\n", sif0.sifData.data, sif0.sifData.words);
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#endif
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}
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}
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}
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else // There's some data ready to transfer into the fifo..
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{
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int wTransfer = sif0.counter; // HW_DMA9_BCR >> 16;
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if (wTransfer > (FIFO_SIF0_W-sif0.fifoSize))
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wTransfer = (FIFO_SIF0_W-sif0.fifoSize);
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#ifdef SIF_LOG
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SIF_LOG("+++++++++++ %lX of %lX\n", wTransfer, sif0.counter /*(HW_DMA9_BCR >> 16)*/ );
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#endif
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SIF0write((u32*)PSXM(HW_DMA9_MADR), wTransfer);
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HW_DMA9_MADR += wTransfer << 2;
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//HW_DMA9_BCR = (HW_DMA9_BCR & 0xFFFF) | (((HW_DMA9_BCR >> 16) - wTransfer)<<16);
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//psxCycles += (wTransfer / 4) * BIAS;
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sif0.counter -= wTransfer;
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notDone = 1;
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}
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}
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if(sif0dma->chcr & 0x100) // If EE SIF enabled and there's something to transfer
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{
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int size = sif0dma->qwc;
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if ((psHu32(DMAC_CTRL) & 0x30) == 0x10) { // STS == fromSIF0
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SysPrintf("SIF0 stall control\n");
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}
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if(size > 0) // If we're reading something continue to do so
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{
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if(sif0.fifoSize > 0)
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{
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int readSize = size;
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if(readSize > (sif0.fifoSize/4))
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readSize = (sif0.fifoSize/4);
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//SIF_LOG(" EE SIF doing transfer %04Xqw to %08X\n", readSize, sif0dma->madr);
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#ifdef SIF_LOG
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SIF_LOG("----------- %lX of %lX\n", readSize << 2, size << 2 );
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#endif
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_dmaGetAddr(sif0dma, ptag, sif0dma->madr, 5);
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SIF0read((u32*)ptag, readSize*4);
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Cpu->Clear(sif0dma->madr, readSize*4);
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//cycles += readSize * BIAS;
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sif0dma->qwc -= readSize;
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sif0dma->madr += readSize << 4;
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notDone = 1;
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}
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}
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else
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{
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if(sif0.chain && sif0dma->chcr & 0x80000000) // Stop on tag IRQ
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{
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// Tag interrupt
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#ifdef SIF_LOG
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SIF_LOG(" EE SIF interrupt\n");
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#endif
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sif0dma->chcr &= ~0x100;
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hwDmacIrq(5);
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notDone = 0;
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}
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else if(sif0.end) // Stop on tag END
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{
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// End tag.
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#ifdef SIF_LOG
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SIF_LOG(" EE SIF end\n");
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#endif
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sif0dma->chcr &= ~0x100;
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hwDmacIrq(5);
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notDone = 0;
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}
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else if(sif0.fifoSize >= 4) // Read a tag
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{
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__declspec(align(16)) static u32 tag[4];
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SIF0read((u32*)&tag[0], 4); // Tag
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sif0dma->qwc = (u16)tag[0];
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sif0dma->madr = tag[1];
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sif0dma->chcr = (sif0dma->chcr & 0xffff) | (tag[0] & 0xffff0000);
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#ifdef SIF_LOG
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SIF_LOG(" EE SIF dest chain tag madr:%08X qwc:%04X id:%X irq:%d(%08X_%08X)\n", sif0dma->madr, sif0dma->qwc, (tag[0]>>28)&3, (tag[0]>>31)&1, tag[1], tag[0]);
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#endif
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if ((psHu32(DMAC_CTRL) & 0x30) != 0)psHu32(DMAC_STADR) = sif0dma->madr;
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notDone = 1;
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sif0.chain = 1;
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if(tag[0] & 0x40000000)
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sif0.end = 1;
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}
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}
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}
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}while(notDone);
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FreezeMMXRegs(0);
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}
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void SIF1Dma()
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{
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int id;
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u32 *ptag;
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int notDone;
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//int cycles = 0, psxCycles = 0;
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do
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{
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notDone = 0;
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if(sif1dma->chcr & 0x100) // If EE SIF1 is enabled
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{
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if ((psHu32(DMAC_CTRL) & 0xC0) == 0xC0) { // STS == fromSIF1
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SysPrintf("SIF1 stall control\n");
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}
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if(sif1dma->qwc == 0) // If there's no more to transfer
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{
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if ((sif1dma->chcr & 0xc) == 0 || sif1.end) // If NORMAL mode or end of CHAIN then stop DMA
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{
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// Stop & signal interrupts on EE
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sif1dma->chcr &= ~0x100;
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hwDmacIrq(6);
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sif1.chain = 0;
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sif1.end = 0;
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}
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else // Chain mode
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{
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// Process DMA tag at sif1dma->tadr
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notDone = 1;
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_dmaGetAddr(sif1dma, ptag, sif1dma->tadr, 6);
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sif1dma->chcr = ( sif1dma->chcr & 0xFFFF ) | ( (*ptag) & 0xFFFF0000 ); // Copy the tag
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sif1dma->qwc = (u16)ptag[0];
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if (sif1dma->chcr & 0x40) {
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SysPrintf("SIF1 TTE\n");
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SIF1write(ptag+2, 2);
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}
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sif1.chain = 1;
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id = (ptag[0] >> 28) & 0x7;
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switch(id)
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{
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case 0: // refe
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#ifdef SIF_LOG
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SIF_LOG(" REFE %08X\n", ptag[1]);
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#endif
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sif1.end = 1;
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sif1dma->madr = ptag[1];
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sif1dma->tadr += 16;
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break;
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case 1: // cnt
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#ifdef SIF_LOG
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SIF_LOG(" CNT\n");
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#endif
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sif1dma->madr = sif1dma->tadr + 16;
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sif1dma->tadr = sif1dma->madr + (sif1dma->qwc << 4);
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break;
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case 2: // next
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#ifdef SIF_LOG
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SIF_LOG(" NEXT %08X\n", ptag[1]);
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#endif
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sif1dma->madr = sif1dma->tadr + 16;
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sif1dma->tadr = ptag[1];
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break;
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case 3: // ref
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case 4: // refs
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#ifdef SIF_LOG
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SIF_LOG(" REF %08X\n", ptag[1]);
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#endif
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sif1dma->madr = ptag[1];
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sif1dma->tadr += 16;
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break;
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case 7: // end
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#ifdef SIF_LOG
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SIF_LOG(" END\n");
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#endif
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sif1.end = 1;
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sif1dma->madr = sif1dma->tadr + 16;
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sif1dma->tadr = sif1dma->madr + (sif1dma->qwc << 4);
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break;
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default:
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SysPrintf("Bad addr1 source chain\n");
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}
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}
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}
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else // There's some data ready to transfer into the fifo..
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{
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int qwTransfer = sif1dma->qwc;
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u32 *data;
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notDone = 1;
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_dmaGetAddr(sif1dma, data, sif1dma->madr, 6);
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if(qwTransfer > (FIFO_SIF1_W-sif1.fifoSize)/4) // Copy part of sif1dma into FIFO
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qwTransfer = (FIFO_SIF1_W-sif1.fifoSize)/4;
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SIF1write(data, qwTransfer << 2);
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sif1dma->madr += qwTransfer << 4;
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//cycles += qwTransfer * BIAS;
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sif1dma->qwc -= qwTransfer;
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}
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}
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if(HW_DMA10_CHCR & 0x01000000 ) // If IOP SIF enabled and there's something to transfer
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{
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int size = sif1.counter;
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if(size > 0) // If we're reading something continue to do so
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{
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if(sif1.fifoSize > 0)
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{
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int readSize = size;
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if(readSize > sif1.fifoSize)
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readSize = sif1.fifoSize;
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#ifdef SIF_LOG
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SIF_LOG(" IOP SIF doing transfer %04X to %08X\n", readSize, HW_DMA10_MADR);
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#endif
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SIF1read((u32*)PSXM(HW_DMA10_MADR), readSize);
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psxCpu->Clear(HW_DMA10_MADR, readSize);
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//psxCycles += readSize / 4;
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sif1.counter = size-readSize;
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HW_DMA10_MADR += readSize << 2;
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notDone = 1;
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}
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}
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if(size <= 0 || sif1.fifoSize == 0)
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{
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if(sif1.tagMode & 0x80) // Stop on tag IRQ
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{
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// Tag interrupt
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#ifdef SIF_LOG
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SIF_LOG(" IOP SIF interrupt\n");
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#endif
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HW_DMA10_CHCR &= ~0x01000000; //reset TR flag
|
|
psxDmaInterrupt2(3);
|
|
//hwIntcIrq(INTC_SBUS);
|
|
sif1.tagMode = 0;
|
|
notDone = 0;
|
|
}
|
|
else if(sif1.tagMode & 0x40) // Stop on tag END
|
|
{
|
|
// End tag.
|
|
#ifdef SIF_LOG
|
|
SIF_LOG(" IOP SIF end\n");
|
|
#endif
|
|
HW_DMA10_CHCR &= ~0x01000000; //reset TR flag
|
|
psxDmaInterrupt2(3);
|
|
//hwIntcIrq(INTC_SBUS);
|
|
sif1.tagMode = 0;
|
|
notDone = 0;
|
|
}
|
|
else if(sif1.fifoSize >= 4) // Read a tag
|
|
{
|
|
struct sifData d;
|
|
|
|
SIF1read((u32*)&d, 4);
|
|
|
|
#ifdef SIF_LOG
|
|
SIF_LOG(" IOP SIF dest chain tag madr:%08X wc:%04X id:%X irq:%d\n", d.data & 0xffffff, d.words, (d.data>>28)&7, (d.data>>31)&1);
|
|
#endif
|
|
HW_DMA10_MADR = d.data & 0xffffff;
|
|
sif1.counter = d.words;
|
|
sif1.tagMode = (d.data >> 24) & 0xFF;
|
|
notDone = 1;
|
|
}
|
|
}
|
|
}
|
|
}while(notDone);
|
|
|
|
FreezeMMXRegs(0);
|
|
}
|
|
|
|
int sif0Interrupt() {
|
|
/*if (psxHu32(0x1070) & 8) {
|
|
PSX_INT(9, 0x800);
|
|
return 0;
|
|
}*/
|
|
|
|
psxDmaInterrupt2(2);
|
|
//hwIntcIrq(INTC_SBUS);
|
|
return 1;
|
|
}
|
|
|
|
int sif1Interrupt() {
|
|
/*if (psxHu32(0x1070) & 8) {
|
|
PSX_INT(10, 0x800);
|
|
return 0;
|
|
}*/
|
|
|
|
HW_DMA10_CHCR &= ~0x01000000; //reset TR flag
|
|
psxDmaInterrupt2(3);
|
|
//hwIntcIrq(INTC_SBUS);
|
|
return 1;
|
|
}
|
|
|
|
int EEsif0Interrupt() {
|
|
/*if (psHu32(DMAC_STAT) & (1<<5)) {
|
|
INT(5, 0x800);
|
|
return 0;
|
|
}*/
|
|
sif0dma->chcr &= ~0x100;
|
|
hwDmacIrq(5);
|
|
|
|
return 1;
|
|
}
|
|
|
|
int EEsif1Interrupt() {
|
|
/*if (psHu32(DMAC_STAT) & (1<<6)) {
|
|
INT(6, 0x800);
|
|
return 0;
|
|
}*/
|
|
hwDmacIrq(6);
|
|
|
|
return 1;
|
|
}
|
|
|
|
void dmaSIF0() {
|
|
|
|
#ifdef SIF_LOG
|
|
SIF_LOG("EE: dmaSIF0 chcr = %lx, madr = %lx, qwc = %lx, tadr = %lx\n",
|
|
sif0dma->chcr, sif0dma->madr, sif0dma->qwc, sif0dma->tadr);
|
|
#endif
|
|
|
|
if (sif0.fifoReadPos != sif0.fifoWritePos) {
|
|
SysPrintf("warning, sif0.fifoReadPos != sif0.fifoWritePos\n");
|
|
}
|
|
psHu32(0x1000F240) |= 0x2000;
|
|
if(sif0dma->chcr & 0x100 && HW_DMA9_CHCR & 0x01000000) {
|
|
hwIntcIrq(INTC_SBUS);
|
|
SIF0Dma();
|
|
psHu32(0x1000F240) &= ~0x20;
|
|
psHu32(0x1000F240) &= ~0x2000;
|
|
}
|
|
}
|
|
|
|
void dmaSIF1() {
|
|
|
|
#ifdef SIF_LOG
|
|
SIF_LOG("EE: dmaSIF1 chcr = %lx, madr = %lx, qwc = %lx, tadr = %lx\n",
|
|
sif1dma->chcr, sif1dma->madr, sif1dma->qwc, sif1dma->tadr);
|
|
#endif
|
|
|
|
if (sif1.fifoReadPos != sif1.fifoWritePos) {
|
|
SysPrintf("warning, sif1.fifoReadPos != sif1.fifoWritePos\n");
|
|
}
|
|
psHu32(0x1000F240) |= 0x4000;
|
|
if(sif1dma->chcr & 0x100 && HW_DMA10_CHCR & 0x01000000) {
|
|
SIF1Dma();
|
|
psHu32(0x1000F240) &= ~0x40;
|
|
psHu32(0x1000F240) &= ~0x100;
|
|
psHu32(0x1000F240) &= ~0x4000;
|
|
}
|
|
}
|
|
|
|
void dmaSIF2() {
|
|
|
|
#ifdef SIF_LOG
|
|
SIF_LOG("dmaSIF2 chcr = %lx, madr = %lx, qwc = %lx\n",
|
|
sif2dma->chcr, sif2dma->madr, sif2dma->qwc);
|
|
#endif
|
|
|
|
sif2dma->chcr&= ~0x100;
|
|
hwDmacIrq(7);
|
|
SysPrintf("*PCSX2*: dmaSIF2\n");
|
|
}
|
|
|
|
|
|
int sifFreeze(gzFile f, int Mode) {
|
|
gzfreeze(&sif0, sizeof(sif0));
|
|
gzfreeze(&sif1, sizeof(sif1));
|
|
return 0;
|
|
}
|