mirror of
https://github.com/PCSX2/pcsx2.git
synced 2025-04-02 10:52:54 -04:00
ba4d5b0b95
Fix a stack fault with address sanitizer (on linux) v2: protect the code with GNUC (as it is already done in microVU_Execute.inl)
613 lines
18 KiB
C++
613 lines
18 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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//------------------------------------------------------------------
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// Micro VU - Reg Loading/Saving/Shuffling/Unpacking/Merging...
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//------------------------------------------------------------------
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void mVUunpack_xyzw(const xmm& dstreg, const xmm& srcreg, int xyzw)
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{
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switch ( xyzw ) {
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case 0: xPSHUF.D(dstreg, srcreg, 0x00); break; // XXXX
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case 1: xPSHUF.D(dstreg, srcreg, 0x55); break; // YYYY
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case 2: xPSHUF.D(dstreg, srcreg, 0xaa); break; // ZZZZ
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case 3: xPSHUF.D(dstreg, srcreg, 0xff); break; // WWWW
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}
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}
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void mVUloadReg(const xmm& reg, xAddressVoid ptr, int xyzw)
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{
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switch( xyzw ) {
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case 8: xMOVSSZX(reg, ptr32[ptr]); break; // X
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case 4: xMOVSSZX(reg, ptr32[ptr+4]); break; // Y
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case 2: xMOVSSZX(reg, ptr32[ptr+8]); break; // Z
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case 1: xMOVSSZX(reg, ptr32[ptr+12]); break; // W
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default: xMOVAPS (reg, ptr128[ptr]); break;
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}
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}
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void mVUloadIreg(const xmm& reg, int xyzw, VURegs* vuRegs)
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{
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xMOVSSZX(reg, ptr32[&vuRegs->VI[REG_I].UL]);
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if (!_XYZWss(xyzw)) xSHUF.PS(reg, reg, 0);
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}
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// Modifies the Source Reg!
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void mVUsaveReg(const xmm& reg, xAddressVoid ptr, int xyzw, bool modXYZW)
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{
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/*xMOVAPS(xmmT2, ptr128[ptr]);
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if (modXYZW && (xyzw == 8 || xyzw == 4 || xyzw == 2 || xyzw == 1)) {
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mVUunpack_xyzw(reg, reg, 0);
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}
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mVUmergeRegs(xmmT2, reg, xyzw);
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xMOVAPS(ptr128[ptr], xmmT2);
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return;*/
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switch ( xyzw ) {
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case 5: if (x86caps.hasStreamingSIMD4Extensions) {
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xEXTRACTPS(ptr32[ptr+4], reg, 1);
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xEXTRACTPS(ptr32[ptr+12], reg, 3);
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}
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else {
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xPSHUF.D(reg, reg, 0xe1); //WZXY
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xMOVSS(ptr32[ptr+4], reg);
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xPSHUF.D(reg, reg, 0xff); //WWWW
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xMOVSS(ptr32[ptr+12], reg);
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}
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break; // YW
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case 6: xPSHUF.D(reg, reg, 0xc9);
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xMOVL.PS(ptr64[ptr+4], reg);
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break; // YZ
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case 7: if (x86caps.hasStreamingSIMD4Extensions) {
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xMOVH.PS(ptr64[ptr+8], reg);
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xEXTRACTPS(ptr32[ptr+4], reg, 1);
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}
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else {
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xPSHUF.D(reg, reg, 0x93); //ZYXW
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xMOVH.PS(ptr64[ptr+4], reg);
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xMOVSS(ptr32[ptr+12], reg);
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}
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break; // YZW
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case 9: if (x86caps.hasStreamingSIMD4Extensions) {
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xMOVSS(ptr32[ptr], reg);
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xEXTRACTPS(ptr32[ptr+12], reg, 3);
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}
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else {
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xMOVSS(ptr32[ptr], reg);
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xPSHUF.D(reg, reg, 0xff); //WWWW
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xMOVSS(ptr32[ptr+12], reg);
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}
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break; // XW
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case 10: if (x86caps.hasStreamingSIMD4Extensions) {
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xMOVSS(ptr32[ptr], reg);
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xEXTRACTPS(ptr32[ptr+8], reg, 2);
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}
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else {
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xMOVSS(ptr32[ptr], reg);
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xMOVHL.PS(reg, reg);
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xMOVSS(ptr32[ptr+8], reg);
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}
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break; //XZ
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case 11: xMOVSS(ptr32[ptr], reg);
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xMOVH.PS(ptr64[ptr+8], reg);
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break; //XZW
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case 13: if (x86caps.hasStreamingSIMD4Extensions) {
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xMOVL.PS(ptr64[ptr], reg);
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xEXTRACTPS(ptr32[ptr+12], reg, 3);
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}
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else {
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xPSHUF.D(reg, reg, 0x4b); //YXZW
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xMOVH.PS(ptr64[ptr], reg);
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xMOVSS(ptr32[ptr+12], reg);
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}
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break; // XYW
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case 14: if (x86caps.hasStreamingSIMD4Extensions) {
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xMOVL.PS(ptr64[ptr], reg);
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xEXTRACTPS(ptr32[ptr+8], reg, 2);
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}
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else {
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xMOVL.PS(ptr64[ptr], reg);
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xMOVHL.PS(reg, reg);
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xMOVSS(ptr32[ptr+8], reg);
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}
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break; // XYZ
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case 4: if (!modXYZW) mVUunpack_xyzw(reg, reg, 1);
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xMOVSS(ptr32[ptr+4], reg);
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break; // Y
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case 2: if (!modXYZW) mVUunpack_xyzw(reg, reg, 2);
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xMOVSS(ptr32[ptr+8], reg);
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break; // Z
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case 1: if (!modXYZW) mVUunpack_xyzw(reg, reg, 3);
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xMOVSS(ptr32[ptr+12], reg);
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break; // W
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case 8: xMOVSS(ptr32[ptr], reg); break; // X
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case 12: xMOVL.PS(ptr64[ptr], reg); break; // XY
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case 3: xMOVH.PS(ptr64[ptr+8], reg); break; // ZW
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default: xMOVAPS(ptr128[ptr], reg); break; // XYZW
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}
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}
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// Modifies the Source Reg! (ToDo: Optimize modXYZW = 1 cases)
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void mVUmergeRegs(const xmm& dest, const xmm& src, int xyzw, bool modXYZW)
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{
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xyzw &= 0xf;
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if ( (dest != src) && (xyzw != 0) ) {
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if (x86caps.hasStreamingSIMD4Extensions && (xyzw != 0x8) && (xyzw != 0xf)) {
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if (modXYZW) {
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if (xyzw == 1) { xINSERTPS(dest, src, _MM_MK_INSERTPS_NDX(0, 3, 0)); return; }
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else if (xyzw == 2) { xINSERTPS(dest, src, _MM_MK_INSERTPS_NDX(0, 2, 0)); return; }
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else if (xyzw == 4) { xINSERTPS(dest, src, _MM_MK_INSERTPS_NDX(0, 1, 0)); return; }
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}
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xyzw = ((xyzw & 1) << 3) | ((xyzw & 2) << 1) | ((xyzw & 4) >> 1) | ((xyzw & 8) >> 3);
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xBLEND.PS(dest, src, xyzw);
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}
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else {
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switch (xyzw) {
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case 1: if (modXYZW) mVUunpack_xyzw(src, src, 0);
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xMOVHL.PS(src, dest); // src = Sw Sz Dw Dz
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xSHUF.PS(dest, src, 0xc4); // 11 00 01 00
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break;
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case 2: if (modXYZW) mVUunpack_xyzw(src, src, 0);
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xMOVHL.PS(src, dest);
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xSHUF.PS(dest, src, 0x64);
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break;
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case 3: xSHUF.PS(dest, src, 0xe4);
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break;
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case 4: if (modXYZW) mVUunpack_xyzw(src, src, 0);
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xMOVSS(src, dest);
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xMOVSD(dest, src);
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break;
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case 5: xSHUF.PS(dest, src, 0xd8);
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xPSHUF.D(dest, dest, 0xd8);
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break;
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case 6: xSHUF.PS(dest, src, 0x9c);
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xPSHUF.D(dest, dest, 0x78);
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break;
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case 7: xMOVSS(src, dest);
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xMOVAPS(dest, src);
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break;
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case 8: xMOVSS(dest, src);
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break;
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case 9: xSHUF.PS(dest, src, 0xc9);
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xPSHUF.D(dest, dest, 0xd2);
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break;
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case 10: xSHUF.PS(dest, src, 0x8d);
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xPSHUF.D(dest, dest, 0x72);
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break;
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case 11: xMOVSS(dest, src);
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xSHUF.PS(dest, src, 0xe4);
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break;
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case 12: xMOVSD(dest, src);
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break;
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case 13: xMOVHL.PS(dest, src);
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xSHUF.PS(src, dest, 0x64);
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xMOVAPS(dest, src);
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break;
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case 14: xMOVHL.PS(dest, src);
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xSHUF.PS(src, dest, 0xc4);
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xMOVAPS(dest, src);
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break;
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default: xMOVAPS(dest, src);
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break;
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}
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}
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}
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}
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//------------------------------------------------------------------
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// Micro VU - Misc Functions
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//------------------------------------------------------------------
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// Backup Volatile Regs (EAX, ECX, EDX, MM0~7, XMM0~7, are all volatile according to 32bit Win/Linux ABI)
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__fi void mVUbackupRegs(microVU& mVU, bool toMemory = false) {
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if (toMemory) {
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for(int i = 0; i < 8; i++) {
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xMOVAPS(ptr128[&mVU.xmmBackup[i][0]], xmm(i));
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}
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}
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else {
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mVU.regAlloc->flushAll(); // Flush Regalloc
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xMOVAPS(ptr128[&mVU.xmmBackup[xmmPQ.Id][0]], xmmPQ);
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}
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}
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// Restore Volatile Regs
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__fi void mVUrestoreRegs(microVU& mVU, bool fromMemory = false) {
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if (fromMemory) {
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for(int i = 0; i < 8; i++) {
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xMOVAPS(xmm(i), ptr128[&mVU.xmmBackup[i][0]]);
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}
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}
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else xMOVAPS(xmmPQ, ptr128[&mVU.xmmBackup[xmmPQ.Id][0]]);
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}
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_mVUt void __fc mVUprintRegs() {
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microVU& mVU = mVUx;
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for(int i = 0; i < 8; i++) {
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Console.WriteLn("xmm%d = [0x%08x,0x%08x,0x%08x,0x%08x]", i,
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mVU.xmmBackup[i][0], mVU.xmmBackup[i][1],
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mVU.xmmBackup[i][2], mVU.xmmBackup[i][3]);
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}
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for(int i = 0; i < 8; i++) {
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Console.WriteLn("xmm%d = [%f,%f,%f,%f]", i,
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(float&)mVU.xmmBackup[i][0], (float&)mVU.xmmBackup[i][1],
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(float&)mVU.xmmBackup[i][2], (float&)mVU.xmmBackup[i][3]);
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}
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}
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// Gets called by mVUaddrFix at execution-time
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static void __fc mVUwarningRegAccess(u32 prog, u32 pc) {
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Console.Error("microVU0 Warning: Accessing VU1 Regs! [%04x] [%x]", pc, prog);
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}
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static inline u32 branchAddrN(const mV)
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{
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pxAssumeDev(islowerOP, "MicroVU: Expected Lower OP code for valid branch addr.");
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return ((((iPC + 4) + (_Imm11_ * 2)) & mVU.progMemMask) * 4);
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}
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static inline u32 branchAddr(const mV)
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{
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pxAssumeDev(islowerOP, "MicroVU: Expected Lower OP code for valid branch addr.");
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return ((((iPC + 2) + (_Imm11_ * 2)) & mVU.progMemMask) * 4);
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}
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static void __fc mVUwaitMTVU() {
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if (IsDevBuild) DevCon.WriteLn("microVU0: Waiting on VU1 thread to access VU1 regs!");
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if (THREAD_VU1) vu1Thread.WaitVU();
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}
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// Transforms the Address in gprReg to valid VU0/VU1 Address
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__fi void mVUaddrFix(mV, const x32& gprReg)
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{
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if (isVU1) {
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xAND(gprReg, 0x3ff); // wrap around
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xSHL(gprReg, 4);
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}
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else {
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xTEST(gprReg, 0x400);
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xForwardJNZ8 jmpA; // if addr & 0x4000, reads VU1's VF regs and VI regs
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xAND(gprReg, 0xff); // if !(addr & 0x4000), wrap around
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xForwardJump32 jmpB;
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jmpA.SetTarget();
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if (THREAD_VU1 || (IsDevBuild && !isCOP2)) {
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mVUbackupRegs(mVU, true);
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xPUSH(gprT1);
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xPUSH(gprT2);
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xPUSH(gprT3);
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// Align the stackframe (GCC only, since GCC assumes stackframe is always aligned)
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#ifdef __GNUC__
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xSUB(esp, 4);
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#endif
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if (IsDevBuild && !isCOP2) { // Lets see which games do this!
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xMOV (gprT2, mVU.prog.cur->idx); // Note: Kernel does it via COP2 to initialize VU1!
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xMOV (gprT3, xPC); // So we don't spam console, we'll only check micro-mode...
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xCALL(mVUwarningRegAccess);
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}
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xCALL(mVUwaitMTVU);
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#ifdef __GNUC__
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xADD(esp, 4);
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#endif
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xPOP (gprT3);
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xPOP (gprT2);
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xPOP (gprT1);
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mVUrestoreRegs(mVU, true);
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}
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xAND(gprReg, 0x3f); // ToDo: theres a potential problem if VU0 overrides VU1's VF0/VI0 regs!
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xADD(gprReg, (u128*)VU1.VF - (u128*)VU0.Mem);
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jmpB.SetTarget();
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xSHL(gprReg, 4); // multiply by 16 (shift left by 4)
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}
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}
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//------------------------------------------------------------------
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// Micro VU - Custom SSE Instructions
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//------------------------------------------------------------------
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struct SSEMasks { u32 MIN_MAX_1[4], MIN_MAX_2[4], ADD_SS[4]; };
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static const __aligned16 SSEMasks sseMasks =
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{
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{0xffffffff, 0x80000000, 0xffffffff, 0x80000000},
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{0x00000000, 0x40000000, 0x00000000, 0x40000000},
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{0x80000000, 0xffffffff, 0xffffffff, 0xffffffff}
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};
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// Warning: Modifies t1 and t2
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void MIN_MAX_PS(microVU& mVU, const xmm& to, const xmm& from, const xmm& t1in, const xmm& t2in, bool min)
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{
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const xmm& t1 = t1in.IsEmpty() ? mVU.regAlloc->allocReg() : t1in;
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const xmm& t2 = t2in.IsEmpty() ? mVU.regAlloc->allocReg() : t2in;
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if (0) { // use double comparison
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// ZW
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xPSHUF.D(t1, to, 0xfa);
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xPAND (t1, ptr128[sseMasks.MIN_MAX_1]);
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xPOR (t1, ptr128[sseMasks.MIN_MAX_2]);
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xPSHUF.D(t2, from, 0xfa);
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xPAND (t2, ptr128[sseMasks.MIN_MAX_1]);
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xPOR (t2, ptr128[sseMasks.MIN_MAX_2]);
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if (min) xMIN.PD(t1, t2);
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else xMAX.PD(t1, t2);
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// XY
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xPSHUF.D(t2, from, 0x50);
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xPAND (t2, ptr128[sseMasks.MIN_MAX_1]);
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xPOR (t2, ptr128[sseMasks.MIN_MAX_2]);
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xPSHUF.D(to, to, 0x50);
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xPAND (to, ptr128[sseMasks.MIN_MAX_1]);
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xPOR (to, ptr128[sseMasks.MIN_MAX_2]);
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if (min) xMIN.PD(to, t2);
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else xMAX.PD(to, t2);
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xSHUF.PS(to, t1, 0x88);
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}
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else { // use integer comparison
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const xmm& c1 = min ? t2 : t1;
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const xmm& c2 = min ? t1 : t2;
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xMOVAPS (t1, to);
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xPSRA.D (t1, 31);
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xPSRL.D (t1, 1);
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xPXOR (t1, to);
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xMOVAPS (t2, from);
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xPSRA.D (t2, 31);
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xPSRL.D (t2, 1);
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xPXOR (t2, from);
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xPCMP.GTD(c1, c2);
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xPAND (to, c1);
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xPANDN (c1, from);
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xPOR (to, c1);
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}
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if (t1 != t1in) mVU.regAlloc->clearNeeded(t1);
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if (t2 != t2in) mVU.regAlloc->clearNeeded(t2);
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}
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// Warning: Modifies to's upper 3 vectors, and t1
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void MIN_MAX_SS(mV, const xmm& to, const xmm& from, const xmm& t1in, bool min)
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{
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const xmm& t1 = t1in.IsEmpty() ? mVU.regAlloc->allocReg() : t1in;
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xSHUF.PS(to, from, 0);
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xPAND (to, ptr128[sseMasks.MIN_MAX_1]);
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xPOR (to, ptr128[sseMasks.MIN_MAX_2]);
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xPSHUF.D(t1, to, 0xee);
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if (min) xMIN.PD(to, t1);
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else xMAX.PD(to, t1);
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if (t1 != t1in) mVU.regAlloc->clearNeeded(t1);
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}
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// Not Used! - TriAce games only need a portion of this code to boot (see function below)
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// What this code attempts to do is do a floating point ADD with only 1 guard bit,
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// whereas FPU calculations that follow the IEEE standard have 3 guard bits (guard|round|sticky)
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// Warning: Modifies all vectors in 'to' and 'from', and Modifies t1in
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void ADD_SS_Single_Guard_Bit(microVU& mVU, const xmm& to, const xmm& from, const xmm& t1in)
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{
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const xmm& t1 = t1in.IsEmpty() ? mVU.regAlloc->allocReg() : t1in;
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xMOVD(eax, to);
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xMOVD(ecx, from);
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xSHR (eax, 23);
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xSHR (ecx, 23);
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xAND (eax, 0xff);
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xAND (ecx, 0xff);
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xSUB (ecx, eax); // Exponent Difference
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xForwardJL8 case_neg;
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xForwardJE8 case_end1;
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xCMP (ecx, 24);
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xForwardJLE8 case_pos_small;
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// case_pos_big:
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xPAND(to, ptr128[sseMasks.ADD_SS]);
|
|
xForwardJump8 case_end2;
|
|
|
|
case_pos_small.SetTarget();
|
|
xDEC (ecx);
|
|
xMOV (eax, 0xffffffff);
|
|
xSHL (eax, cl);
|
|
xMOVDZX(t1, eax);
|
|
xPAND (to, t1);
|
|
xForwardJump8 case_end3;
|
|
|
|
case_neg.SetTarget();
|
|
xCMP (ecx, -24);
|
|
xForwardJGE8 case_neg_small;
|
|
|
|
// case_neg_big:
|
|
xPAND(from, ptr128[sseMasks.ADD_SS]);
|
|
xForwardJump8 case_end4;
|
|
|
|
case_neg_small.SetTarget();
|
|
xNOT (ecx); // -ecx - 1
|
|
xMOV (eax, 0xffffffff);
|
|
xSHL (eax, cl);
|
|
xMOVDZX(t1, eax);
|
|
xPAND (from, t1);
|
|
|
|
case_end1.SetTarget();
|
|
case_end2.SetTarget();
|
|
case_end3.SetTarget();
|
|
case_end4.SetTarget();
|
|
|
|
xADD.SS(to, from);
|
|
if (t1 != t1in) mVU.regAlloc->clearNeeded(t1);
|
|
}
|
|
|
|
// Turns out only this is needed to get TriAce games booting with mVU
|
|
// Modifies from's lower vector
|
|
void ADD_SS_TriAceHack(microVU& mVU, const xmm& to, const xmm& from)
|
|
{
|
|
xMOVD(eax, to);
|
|
xMOVD(ecx, from);
|
|
xSHR (eax, 23);
|
|
xSHR (ecx, 23);
|
|
xAND (eax, 0xff);
|
|
xAND (ecx, 0xff);
|
|
xSUB (ecx, eax); // Exponent Difference
|
|
|
|
xCMP (ecx, -25);
|
|
xForwardJLE8 case_neg_big;
|
|
xCMP (ecx, 25);
|
|
xForwardJL8 case_end1;
|
|
|
|
// case_pos_big:
|
|
xPAND(to, ptr128[sseMasks.ADD_SS]);
|
|
xForwardJump8 case_end2;
|
|
|
|
case_neg_big.SetTarget();
|
|
xPAND(from, ptr128[sseMasks.ADD_SS]);
|
|
|
|
case_end1.SetTarget();
|
|
case_end2.SetTarget();
|
|
|
|
xADD.SS(to, from);
|
|
}
|
|
|
|
#define clampOp(opX, isPS) { \
|
|
mVUclamp3(mVU, to, t1, (isPS)?0xf:0x8); \
|
|
mVUclamp3(mVU, from, t1, (isPS)?0xf:0x8); \
|
|
opX(to, from); \
|
|
mVUclamp4(to, t1, (isPS)?0xf:0x8); \
|
|
}
|
|
|
|
void SSE_MAXPS(mV, const xmm& to, const xmm& from, const xmm& t1 = xEmptyReg, const xmm& t2 = xEmptyReg)
|
|
{
|
|
if (CHECK_VU_MINMAXHACK) { xMAX.PS(to, from); }
|
|
else { MIN_MAX_PS(mVU, to, from, t1, t2, false); }
|
|
}
|
|
void SSE_MINPS(mV, const xmm& to, const xmm& from, const xmm& t1 = xEmptyReg, const xmm& t2 = xEmptyReg)
|
|
{
|
|
if (CHECK_VU_MINMAXHACK) { xMIN.PS(to, from); }
|
|
else { MIN_MAX_PS(mVU, to, from, t1, t2, true); }
|
|
}
|
|
void SSE_MAXSS(mV, const xmm& to, const xmm& from, const xmm& t1 = xEmptyReg, const xmm& t2 = xEmptyReg)
|
|
{
|
|
if (CHECK_VU_MINMAXHACK) { xMAX.SS(to, from); }
|
|
else { MIN_MAX_SS(mVU, to, from, t1, false); }
|
|
}
|
|
void SSE_MINSS(mV, const xmm& to, const xmm& from, const xmm& t1 = xEmptyReg, const xmm& t2 = xEmptyReg)
|
|
{
|
|
if (CHECK_VU_MINMAXHACK) { xMIN.SS(to, from); }
|
|
else { MIN_MAX_SS(mVU, to, from, t1, true); }
|
|
}
|
|
void SSE_ADD2SS(mV, const xmm& to, const xmm& from, const xmm& t1 = xEmptyReg, const xmm& t2 = xEmptyReg)
|
|
{
|
|
if (!CHECK_VUADDSUBHACK) { clampOp(xADD.SS, false); }
|
|
else { ADD_SS_TriAceHack(mVU, to, from); }
|
|
}
|
|
|
|
// Does same as SSE_ADDPS since tri-ace games only need SS implementation of VUADDSUBHACK...
|
|
void SSE_ADD2PS(mV, const xmm& to, const xmm& from, const xmm& t1 = xEmptyReg, const xmm& t2 = xEmptyReg)
|
|
{
|
|
clampOp(xADD.PS, true);
|
|
}
|
|
void SSE_ADDPS(mV, const xmm& to, const xmm& from, const xmm& t1 = xEmptyReg, const xmm& t2 = xEmptyReg)
|
|
{
|
|
clampOp(xADD.PS, true);
|
|
}
|
|
void SSE_ADDSS(mV, const xmm& to, const xmm& from, const xmm& t1 = xEmptyReg, const xmm& t2 = xEmptyReg)
|
|
{
|
|
clampOp(xADD.SS, false);
|
|
}
|
|
void SSE_SUBPS(mV, const xmm& to, const xmm& from, const xmm& t1 = xEmptyReg, const xmm& t2 = xEmptyReg)
|
|
{
|
|
clampOp(xSUB.PS, true);
|
|
}
|
|
void SSE_SUBSS(mV, const xmm& to, const xmm& from, const xmm& t1 = xEmptyReg, const xmm& t2 = xEmptyReg)
|
|
{
|
|
clampOp(xSUB.SS, false);
|
|
}
|
|
void SSE_MULPS(mV, const xmm& to, const xmm& from, const xmm& t1 = xEmptyReg, const xmm& t2 = xEmptyReg)
|
|
{
|
|
clampOp(xMUL.PS, true);
|
|
}
|
|
void SSE_MULSS(mV, const xmm& to, const xmm& from, const xmm& t1 = xEmptyReg, const xmm& t2 = xEmptyReg)
|
|
{
|
|
clampOp(xMUL.SS, false);
|
|
}
|
|
void SSE_DIVPS(mV, const xmm& to, const xmm& from, const xmm& t1 = xEmptyReg, const xmm& t2 = xEmptyReg)
|
|
{
|
|
clampOp(xDIV.PS, true);
|
|
}
|
|
void SSE_DIVSS(mV, const xmm& to, const xmm& from, const xmm& t1 = xEmptyReg, const xmm& t2 = xEmptyReg)
|
|
{
|
|
clampOp(xDIV.SS, false);
|
|
}
|
|
|
|
//------------------------------------------------------------------
|
|
// Micro VU - Custom Quick Search
|
|
//------------------------------------------------------------------
|
|
|
|
__pagealigned u8 mVUsearchXMM[__pagesize];
|
|
|
|
// Generates a custom optimized block-search function
|
|
// Note: Structs must be 16-byte aligned! (GCC doesn't guarantee this)
|
|
void mVUcustomSearch() {
|
|
HostSys::MemProtectStatic(mVUsearchXMM, PageAccess_ReadWrite());
|
|
memset_8<0xcc,__pagesize>(mVUsearchXMM);
|
|
xSetPtr(mVUsearchXMM);
|
|
|
|
xMOVAPS (xmm0, ptr32[ecx]);
|
|
xPCMP.EQD(xmm0, ptr32[edx]);
|
|
xMOVAPS (xmm1, ptr32[ecx + 0x10]);
|
|
xPCMP.EQD(xmm1, ptr32[edx + 0x10]);
|
|
xPAND (xmm0, xmm1);
|
|
|
|
xMOVMSKPS(eax, xmm0);
|
|
xCMP (eax, 0xf);
|
|
xForwardJL8 exitPoint;
|
|
|
|
xMOVAPS (xmm0, ptr32[ecx + 0x20]);
|
|
xPCMP.EQD(xmm0, ptr32[edx + 0x20]);
|
|
xMOVAPS (xmm1, ptr32[ecx + 0x30]);
|
|
xPCMP.EQD(xmm1, ptr32[edx + 0x30]);
|
|
xPAND (xmm0, xmm1);
|
|
|
|
xMOVAPS (xmm2, ptr32[ecx + 0x40]);
|
|
xPCMP.EQD(xmm2, ptr32[edx + 0x40]);
|
|
xMOVAPS (xmm3, ptr32[ecx + 0x50]);
|
|
xPCMP.EQD(xmm3, ptr32[edx + 0x50]);
|
|
xPAND (xmm2, xmm3);
|
|
|
|
xMOVAPS (xmm4, ptr32[ecx + 0x60]);
|
|
xPCMP.EQD(xmm4, ptr32[edx + 0x60]);
|
|
xMOVAPS (xmm5, ptr32[ecx + 0x70]);
|
|
xPCMP.EQD(xmm5, ptr32[edx + 0x70]);
|
|
xPAND (xmm4, xmm5);
|
|
|
|
xMOVAPS (xmm6, ptr32[ecx + 0x80]);
|
|
xPCMP.EQD(xmm6, ptr32[edx + 0x80]);
|
|
xMOVAPS (xmm7, ptr32[ecx + 0x90]);
|
|
xPCMP.EQD(xmm7, ptr32[edx + 0x90]);
|
|
xPAND (xmm6, xmm7);
|
|
|
|
xPAND (xmm0, xmm2);
|
|
xPAND (xmm4, xmm6);
|
|
xPAND (xmm0, xmm4);
|
|
xMOVMSKPS(eax, xmm0);
|
|
|
|
exitPoint.SetTarget();
|
|
xRET();
|
|
HostSys::MemProtectStatic(mVUsearchXMM, PageAccess_ExecOnly());
|
|
}
|