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  • 0dd6de9044 Change back some DMA logic so when non-investigated cases come through they will throw runtime_error. Marco Satti 2017-03-13 15:25:30 +08:00
  • 76091d9252 Changed around some debug stuff - last commit (SBUS fixes) actually fixed the OSDSYS load problem: "[Debug] EE SIO Message: # Loader 'rom0:OSDSYS':pc=00200008", which I didn't notice! I'm still spending a bit of time to double check the DMA logic. Marco Satti 2017-03-12 21:16:44 +08:00
  • e138a0ac59 Moved some of the SBUS register update logic to the IOP side, so it now obeys the start / finish order. Updated the DMAC logic of EE and IOP to check for appropriate read/write FIFO sizes (used for debugging). Marco Satti 2017-03-11 00:42:09 +08:00
  • 770f3f6909 Fix up the DMAC accuracy option for quicker debugging. Currently investigating the "failed to load OSDSYS". Marco Satti 2017-03-10 14:56:05 +08:00
  • 0f92f3e2f9 Fixed up the load memory instructions - now gets to: "[Debug] EE SIO Message: # Loader: can't load rom0:OSDSYS" :) Marco Satti 2017-03-10 00:59:12 +08:00
  • 6e7031d570 Update the readme a bit... been a while. Marco Satti 2017-03-08 14:50:13 +08:00
  • 21121a30a3 Update to VS2017. Marco Satti 2017-03-08 13:23:19 +08:00
  • c25c79290c Added in a system skip cycles option to consume all ticks for a run - for systems such as the DMAC's, where nothing will change if no DMA transfer is in process (wasting energy on nothing). Multi threaded mode needs to be tested with it. Reworked the IOP timers overflow check - not sure why, but there was a huge perf increase (no obvious changes, probably a lot of cache misses). Marco Satti 2017-03-07 23:35:04 +08:00
  • 5fc137163a Fixed up the interrupt/exception PC stuff for the ??? time... Still not happy with it but it works. IOP and EE now sitting in idle loops (interrupts enabled), which is good. Onto the VPU's! Marco Satti 2017-03-07 13:33:44 +08:00
  • 0d5159440b Fixed up the EE DMAC interrupt not getting handled properly. Need to investigate the IOP infinite loop next (no interrupts enabled). Marco Satti 2017-03-05 20:21:17 +08:00
  • 436dec2b0d Implemented the IOP source chain mode DMA transfer! EE and IOP are now communicating with each other! Marco Satti 2017-03-05 15:22:18 +08:00
  • 717632d7d7 Got IOP DMAC channel SIF1 to recieve data properly in (dest) chain mode - now working on implementing source chain mode to work (for SIF0). Marco Satti 2017-03-04 23:14:31 +08:00
  • 506a741a0d Cleanup of the IOP and EE DMAC's based upon new info from wisi and SP193, getting ready for IOP's chain mode. Marco Satti 2017-03-03 13:51:34 +08:00
  • 3e2c08eed4 Git sync commit. Marco Satti 2017-02-23 17:06:34 +08:00
  • 999d7402e3 Fix dword ordering of the u128 type, which fixes the FIFO queue word ordering. Currently investigating the IOP SIF1 chain mode (not documented except for PCSX2). Marco Satti 2017-02-22 22:51:57 +08:00
  • 513bb452bd Change the COP0 operating context functions to be 1 function. Marco Satti 2017-02-21 16:39:24 +08:00
  • 91bcd88dd1 Merge branch 'gs-pcrtc-test' Marco Satti 2017-02-20 18:53:11 +08:00
  • 92884aaae8 Still not finished with the CRTC, but I wil look at it later - sorted out the pixel clock stuff, how to interrupt the EE/IOP intc, and the timer gate functionality for now. Marco Satti 2017-02-20 18:47:23 +08:00
  • 0ef78b3084 Initial test of the PCRTC - based of guesses (calculating a pixel clock, using that for hblank and vblank). Marco Satti 2017-02-15 20:04:15 +08:00
  • eaeea2066e Merge branch 'threading-test' - although MT mode is not quite ready (race condition issues), the ST mode was updated in the process (stable). Marco Satti 2017-02-04 15:15:22 +08:00
  • a26e84c42f Changed the time slice VM options (MT and ST) to a single option, as both are useless when only 1 mode can be selected. Marco Satti 2017-02-04 11:58:05 +08:00
  • fe7fe047f7 Got logging working again, fixed up single threaded mode, added in a VM option for time slice's per VM run() instead of fixed values. Marco Satti 2017-02-04 00:36:22 +08:00
  • 4e638f247b Major refactor & clean, implemented threading (still not sure on best practice but it seems fairly simple code wise), added system biasing / persistant clock speed state, stuffed up logging however, need to fix that. Marco Satti 2017-02-03 21:32:00 +08:00
  • 2340a10aa7 Working POC of threading. Still need to make the bus writes (in PhysicalMMU_t) atomic, but for now it works without it (DMA transfers I imagine will need this). Will also refactor the VM manager shortly. Marco Satti 2017-01-30 20:33:39 +08:00
  • cca0ab5b01 Initial threading test try - not currently working. Marco Satti 2017-01-28 16:17:20 +08:00
  • 65f1287dc5 Refactored a lot of code, moved the EE and IOP core's MMU and Exception handlers into the base core class logic. Currently brainstorming over multi-threading, as this is a good time to put it in. Marco Satti 2017-01-27 22:47:02 +08:00
  • 12cd7f1e4f Fixes for interrupt handling... Marco Satti 2017-01-22 20:21:22 +08:00
  • 3af76911eb Initial commit of working IOP timers.. still a lot left unimplemented, but basics (sysclock count, interrupting) working. Marco Satti 2017-01-21 17:32:05 +08:00
  • 70cba8c009 Implemented IOP timers resources, logic to follow. Marco Satti 2017-01-19 19:21:52 +08:00
  • 5e48cefa6f Implemented most of the SBUS registers. Marco Satti 2017-01-19 17:21:11 +08:00
  • a7cae2e5ef WIP on implementing SBUS register functionality. DMA and FIFO stuff done. Marco Satti 2017-01-18 21:27:52 +08:00
  • c11b989f67 Moved more interrupt logic to registers. Marco Satti 2017-01-17 00:00:56 +08:00
  • 55aee83090 Begin implementing SBUS register functionality. Moved some parts of code from logic components into registers, such as determining if an interrupt should be raised. There is a blurry line here.. when should I put things into registers (event based) and when should I put things into logic components (polling based)? I have currently defined this line as "its ok to put things in registers that do not interface with other registers outside its 'area'", exceptions being made for fully un-reversed engineered parts such as the SBUS registers/logic. Marco Satti 2017-01-16 21:04:38 +08:00
  • ead73a2e67 Moved setFieldValue to an inline function. Marco Satti 2017-01-16 10:33:16 +08:00
  • e96661bfba Cleanup. Marco Satti 2017-01-15 21:58:26 +08:00
  • 90b6b7de1d Fixed up a few exception handling errors - in particular, the EE and IOP Core's now increment the PC before executing the instruction. Marco Satti 2017-01-15 16:17:26 +08:00
  • 12792cc78a Changed interrupts to a full polling method - currently level interrupt triggered, but can be edge if needed. Still investigating a bug to do with the IOP.COP0.Status where it doesnt always re-enable interrupts. Marco Satti 2017-01-13 22:52:27 +08:00
  • a473c16894 Small optimisation to both DMAC logic. Marco Satti 2017-01-13 14:35:25 +08:00
  • c1a6f7b264 Added in separate MIPS branch delay object type, split register debugging into reads and writes. Marco Satti 2017-01-13 00:17:18 +08:00
  • a86f11028e Few small fixes to interrupt handling. Still not working properly, currently debugging. Marco Satti 2017-01-11 19:07:53 +08:00
  • cf9f784eda FeelsReallyGoodMan - EE and IOP are beginning to communicate through the SBUS (DMA transfers)! IOP now interrupting on SIF1 completing. Will need to change the way interrupt exceptions are generated as currently the IOP INTC is sending one every tick (and getting handled meaning no progression in the IOP Core). Reworked some COP0 BitfieldRegister32's that were basically equivilant to a Register32 (simplified). Added in an initalise virtual function to the registers. General reorganisation. Marco Satti 2017-01-09 19:00:07 +08:00
  • 78b8b170f3 Fixup of the exception handling for the EE and IOP cores. Now checks for masking conditions before commiting the exception (especially needed for interrupts). Marco Satti 2017-01-06 12:07:58 +08:00
  • 4f8ec56862 WIP on the IOP Dmac Marco Satti 2017-01-04 14:09:55 +08:00
  • 0e4728be86 Added in register context as a parameter when reading/writing. 2 reasons: easier debugging, and to support registers which have different functionality depending on which component accessed it (ie: EE or IOP). This will be useful, for example, with the SBUS registers. Marco Satti 2017-01-03 18:13:34 +08:00
  • 706fcedd78 Cleaned up the memory and register types - no longer have a signed/unsigned combo, instead the caller must cast the result to the appropriate type (only useful on reads in most cases). Rationale for this change is to stop duplicating custom functionality through eg: readWordU/S. Marco Satti 2017-01-01 19:00:42 +08:00
  • 23e7301aa4 Initial IOP INTC (INTR?) commit - still to decypher bitfields within the registers. Marco Satti 2016-12-29 22:23:21 +08:00
  • 62654cdfe1 Cleanup. Marco Satti 2016-12-26 00:02:51 +08:00
  • aaf895f7c2 Add in debug syscall tables for the EE and IOP. Marco Satti 2016-12-24 16:31:19 +08:00
  • f04e6d795c Remove getPCValue() from PCRegister32_t - not needed, use normal register read functions. Marco Satti 2016-12-23 21:54:33 +08:00
  • 5863b6b252 WIP on IOP DMAC registers. Changed FIFO queue to use u32 as base type, since the IOP needs to read from it. Marco Satti 2016-12-23 00:48:23 +08:00
  • 9e0af0acb9 Begin adding in IOP DMAC resources/system logic. Marco Satti 2016-12-22 18:43:23 +08:00
  • fd36c6dd63 Small fix to the u128 type which caused incorrect values to be later read. Removed the source chain first cycle stuff - didnt realise the PS2 OS sets TADR before turning the dma channel on. Marco Satti 2016-12-22 00:40:44 +08:00
  • 0fd155193b Moved channel related functions into the channel type instead of the DMAC system. Also got rid of the slice channel count stuff - implementation was wrong and correct way doesn't make sense in an emulator (if I read it correctly this time). Probably need to write the IOP DMAC system now, wont be able to progress any further until I do so. Marco Satti 2016-12-21 14:26:59 +08:00
  • b645357eaa EE DMAC now works somewhat - EE is writing data to the SIF1 channel (there is no IOP DMAC to recieve it yet). Still a bit more work to do. IOPCore stuck in infinite loop, presumably waiting for an interrupt, while EECore is watching an address, presumably for the IOP to write to it. Marco Satti 2016-12-20 23:24:49 +08:00
  • 2194330ce5 Added in abstraction for read/writing 128-bit primatives to memory, registers, etc. DMAC now crashes due to no data being available in the associated fifo queue... Need to add a way to return early and try again next cycle if this occurs. Marco Satti 2016-12-18 22:31:42 +08:00
  • 0aab1549bb Brainstorming a bit for the EE DMAC fixes.. Marco Satti 2016-12-17 23:03:48 +08:00
  • 3974afb750 Put in more SIF registers (SBUS), now crashes in the EE DMAC SIF0 channel system - missing TADR register. Will have to invesigate more with PCSX2 as the manual clearly says there isn't one, but PCSX2 supports chain (tag) mode implying there is one. Marco Satti 2016-12-14 17:59:44 +08:00
  • 54cc1fd292 IOP now has all registers implemented properly, in step with before. Changed the MappedRegister wrapper classes to allow aligned register access, where appropriate. Marco Satti 2016-12-14 16:52:08 +08:00
  • b26b1a9211 Renamed registers to be more consistent, changed the register mapping wrappers to allow accesses other than the nominated size (returns LSB's). Marco Satti 2016-12-13 23:18:15 +08:00
  • 71b7bbbf68 Change ZeroRegister types to ConstantRegister - allows the user to set specific constant values instead of just 0 (defaults to 0 if no parameter specified). WIP on adding IOP DMAC stuff. Marco Satti 2016-12-13 18:33:46 +08:00
  • 613fa4aa1c Starting to properly implement the IOP now. Will probably take a while to go through PCSX2's source code. Marco Satti 2016-12-13 00:48:07 +08:00
  • 6a65d07cfc Small speedups for debugging (inlining). Small cleanup/reorganisation of the component timing. Marco Satti 2016-12-10 00:19:44 +08:00
  • cf39c4a94b Started adding in a bunch of IOP registers/memory (CDVD & ROM1, EROM, ROM2). Marco Satti 2016-12-06 17:57:42 +08:00
  • dd40cc16fb Small bug fixes in the EECore FPU and MMU. Marco Satti 2016-11-30 00:20:52 +08:00
  • 8ef9059f98 Bug fix for the wrong PA's being returned for VA's in the EE Core - spent a whole day tracking this one down! When debugging, it was acutally overwriting the instructions already there causing a large amount of confusion on my part... Marco Satti 2016-11-29 20:29:41 +08:00
  • 777d267389 Begin implementing the VU instructions. Changes to the way FPU values are calculated - when calling the format function it will fill in a list of flags needed by the EE Core FPU and VU units. Marco Satti 2016-11-28 21:02:55 +08:00
  • 7ef5cd173a Added in the VU0/1 registers (and other. misc ones) Marco Satti 2016-11-26 16:38:39 +08:00
  • 04a3174ff2 Cleanup, get rid of mostly useless get functions, move instruction exception raising code to helper functions. Marco Satti 2016-11-19 03:03:39 +08:00
  • 96fbe08138 VU structure work. EE Core now delegates COP2 instructions to the VU0 unit. Marco Satti 2016-11-18 20:29:05 +08:00
  • 41010d6ebc COP2 instruction table and definitions added, still need to implement the actual code. Added additional field extraction functions to a new EECoreInstruction_t that is based on the MIPS one. Marco Satti 2016-11-17 18:01:15 +08:00
  • 124f31794f WIP on the VIF, VU and COP2 (VU0 connection) of the EE Core. Marco Satti 2016-11-16 20:13:04 +08:00
  • 13c970b8eb Begin work on the VIF system. Added in the VU zero register. Marco Satti 2016-11-12 20:09:46 +08:00
  • 51086c5657 Implemented more MappedRegister_t types, set up the VU0/1 physical memory map framework. Marco Satti 2016-11-11 16:18:44 +08:00
  • f743c0a8d7 A lot of organisation again. I had to remove the direct mapping ability of MappedMemory_t (now just Memory_t) as VU0 requires its memory be mapped in two places - it was getting messy with image mappings everywhere. There is now a wrapper class to map Memory_t. There are new mapMemory() functions to create the wrappers automatically. Marco Satti 2016-11-10 15:28:10 +08:00
  • 056f2634d4 Removed an unused include. Marco Satti 2016-10-30 21:28:33 +08:00
  • 7d69528016 Structual changes needed for writing the upcoming VU code. Removed the class / idea of 'bitfield memory 32' and instead changed things to use BitfieldRegister32_t. In order to map a register (into PhysicalMMU_t), a new compatibility layer MappedRegister32_t has been created instead. Any MappedMemory_t class and child classes remain intact, they can still be mapped directly. Marco Satti 2016-10-30 21:26:00 +08:00
  • 7796445880 Cleanup. Marco Satti 2016-10-28 23:36:19 +08:00
  • 1e8688fd60 Added in a few more memory mappings, fixed the EE Core and IOP MMU's to recognise when a read or write is occuring (helps with throwing exceptions and checking for the isolate cache condition). Marco Satti 2016-10-28 15:16:21 +08:00
  • 73d33b244b Fixed up the IOP's COP0 registers, added a check for the IsC bit when writing to IOP's main memory. Discards the write if set. Marco Satti 2016-10-25 23:54:29 +08:00
  • a321ce4bf5 Tracked down a bug preventing IOP progress due to it writing to the BIOS area (???) - made ROMappedMemory_t which discards writes and the BIOS is now subclassed of that instead. Marco Satti 2016-10-23 22:33:50 +08:00
  • 415861a532 Move the IOP core into its proper hierarchy (IOPCore). Marco Satti 2016-10-22 17:35:37 +08:00
  • 9e0d685a74 Put in some of the IOP undocumented memory accesses.. the PC now enters the main memory for execution! Marco Satti 2016-10-21 22:21:21 +08:00
  • 85470b6e27 Moved the VM MMU to a separate type under PS2Resources - the IOP has its own address space apparently so we can reuse it. Marco Satti 2016-10-21 20:41:36 +08:00
  • f0ad6f2145 Started working on the IOP - got the main loop going with basic MIPS instructions done. Added in a method for sending clock events to components and updating the individual timings for each clock source. Currently, components such as the DMAC, INTC will be renamed to EECoreDMAC etc once the IOP components are put in. Marco Satti 2016-10-18 09:58:37 +08:00
  • 3e01b4b1fb Implemented DMAC stall control. Marco Satti 2016-10-10 22:20:55 +08:00
  • a94391b829 Finished interleaved DMAC mode, organised EE register resources structure into sub systems. Marco Satti 2016-10-09 18:47:15 +08:00
  • 91c8bcdc78 Small cleanup to the DMAC code. Taking a break for a bit perhaps, will start on IOP or VIF/VU when I resume (after the rest of the DMAC). Marco Satti 2016-10-06 22:57:58 +08:00
  • cf22906291 DMA tag instructions done. Marco Satti 2016-10-05 13:02:11 +08:00
  • d665c8d206 Chain mode mostly done, just need to implement tag ID actions. Marco Satti 2016-10-04 23:36:03 +08:00
  • 49febe88d7 More on DMAC. Marco Satti 2016-10-04 00:18:09 +08:00
  • 0b21031341 Organisation, more work on DMAC source chain mode (currently reading though PCSX2 source code) Marco Satti 2016-10-03 17:10:36 +08:00
  • c87ecbe9b4 Try this for calculating physical mem addresses - can't test for now though. Marco Satti 2016-09-30 21:06:31 +08:00
  • 30f1f2792c Reorganised the EE Core MMU.. I think there is something wrong with stage 4 lookup, currently debugging it. Marco Satti 2016-09-30 17:57:20 +08:00
  • 10c9c188ca Fix up the mask generator function for when length = 32. x86 only allows shifting for 0-31, so need a special condition for 32. Marco Satti 2016-09-30 09:10:56 +08:00
  • bc18d72e5e Removed boost dependencies, and updated documentation. Marco Satti 2016-09-29 22:54:25 +08:00
  • f8a1b96099 Ok - moved to a C array for the bitfield map. Should not be an issue any more... It works (good), and the only sanity checking done is on the index supplied. Marco Satti 2016-09-29 22:24:22 +08:00
  • 1b056fce38 Renamed StorageObject -> MappedMemory. Moved bitfield map into its own type class which is extended by the registers and mapped memory... Something seems to have broken performance though... Marco Satti 2016-09-28 23:20:02 +08:00
  • 1ba1c69dea Done a bit more on the DMAC. Normal mode almost done. Marco Satti 2016-09-28 13:34:42 +08:00
  • 8b38815735 Added in bitfield DMAC channel registers. Marco Satti 2016-09-25 19:48:32 +08:00
  • 4d78f68122 As you have to generate symlinks to the boost headers, mark in the gitmodules file that we can safely ignore modifications in the boost submodule folder. Marco Satti 2016-09-24 17:02:34 +08:00