mirror of
https://github.com/AlexAltea/orbital.git
synced 2024-06-16 03:07:58 -04:00
hardware/liverpool: Separate SAM/SMU into dedicated engines
This commit is contained in:
Alexandro Sanchez Bach
parent
bc67ad6b8b
commit
1541e6eaad
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@ -45,8 +45,11 @@ ORBITAL_SOURCES_APPEND(${ORBITAL_DIR_SOURCES}/orbital/hardware)
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ORBITAL_SOURCES_APPEND(${ORBITAL_DIR_SOURCES}/orbital/hardware/aeolia)
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ORBITAL_SOURCES_APPEND(${ORBITAL_DIR_SOURCES}/orbital/hardware/aeolia/uart)
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ORBITAL_SOURCES_APPEND(${ORBITAL_DIR_SOURCES}/orbital/hardware/liverpool)
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ORBITAL_SOURCES_APPEND(${ORBITAL_DIR_SOURCES}/orbital/hardware/liverpool/gca)
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ORBITAL_SOURCES_APPEND(${ORBITAL_DIR_SOURCES}/orbital/hardware/liverpool/gmc)
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ORBITAL_SOURCES_APPEND(${ORBITAL_DIR_SOURCES}/orbital/hardware/liverpool/oss)
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ORBITAL_SOURCES_APPEND(${ORBITAL_DIR_SOURCES}/orbital/hardware/liverpool/smu)
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ORBITAL_SOURCES_APPEND(${ORBITAL_DIR_SOURCES}/orbital/hardware/liverpool/sam)
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ORBITAL_SOURCES_APPEND(${ORBITAL_DIR_SOURCES}/orbital/software)
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ORBITAL_SOURCES_APPEND(${ORBITAL_DIR_SOURCES}/orbital/software/sbl)
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ORBITAL_SOURCES_APPEND(${ORBITAL_DIR_SOURCES}/orbital/ui)
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@ -22,9 +22,8 @@
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#include "gmc/gmc_7_1_sh_mask.h"
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#include "oss/oss_2_0_d.h"
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#include "oss/oss_2_0_sh_mask.h"
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#include "smu/smu_7_1_2_d.h"
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#include "smu/smu_7_1_2_sh_mask.h"
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#include "sam/sam.h"
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constexpr auto GC_MMIO_PCI = OffsetRange(0x0000, 0x100);
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// Logging
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#define DEBUG_GC 0
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@ -40,7 +39,9 @@ do { \
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LiverpoolGCDevice::LiverpoolGCDevice(PCIeBus* bus, const LiverpoolGCDeviceConfig& config)
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: PCIeDevice(bus, config),
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// Engines
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gmc(bus->space_mem()), ih(*this, gmc)
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gmc(bus->space_mem()), ih(*this, gmc),
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smu(gmc, ih),
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sam(gmc, ih, smu)
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{
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// Define BARs
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space_bar0 = new MemorySpace(this, 0x4000000, {
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@ -83,8 +84,6 @@ void LiverpoolGCDevice::reset() {
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header.header_type |= PCI_HEADER_TYPE_MULTI_FUNCTION;
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mmio.fill(0);
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sam_ix.fill(0);
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sam_sab_ix.fill(0);
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}
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U64 LiverpoolGCDevice::bar0_read(U64 addr, U64 size) {
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@ -128,7 +127,8 @@ U64 LiverpoolGCDevice::mmio_read(U64 addr, U64 size) {
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value = gmc.mmio_read(index);
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return value;
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}
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else if (GMC_MMIO_MC.contains(index)) {
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else if (GMC_MMIO_VM.contains(index)
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|| GMC_MMIO_MC.contains(index)) {
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value = gmc.mmio_read(index);
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return value;
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}
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@ -136,6 +136,14 @@ U64 LiverpoolGCDevice::mmio_read(U64 addr, U64 size) {
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value = ih.mmio_read(index);
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return value;
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}
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else if (SMU_MMIO.contains(index)) {
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value = smu.mmio_read(index);
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return value;
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}
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else if (SAM_MMIO.contains(index)) {
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value = sam.mmio_read(index);
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return value;
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}
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switch (index) {
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// ACP
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@ -149,25 +157,6 @@ U64 LiverpoolGCDevice::mmio_read(U64 addr, U64 size) {
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value = 0xFFFFFFFF;
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break;
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// SMU
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case mmSMC_IND_INDEX:
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value = mmio[index];
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break;
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case mmSMC_IND_DATA:
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switch (mmio[mmSMC_IND_INDEX]) {
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case 0xC2100004:
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value = 0x2 | 0x1;
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break;
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case 0xC0500090:
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value = 0x1;
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break;
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case 0xC0500098:
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value = 0x1;
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break;
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default:
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value = 0x0;
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}
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break;
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// GCA
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case mmGRBM_GFX_INDEX:
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@ -182,25 +171,6 @@ U64 LiverpoolGCDevice::mmio_read(U64 addr, U64 size) {
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value = 0;
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break;
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case mmSAM_IX_DATA:
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index_ix = mmio[mmSAM_IX_INDEX];
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DPRINTF("mmSAM_IX_DATA_read { index: %X }", index_ix);
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value = sam_ix[index_ix];
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break;
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case mmSAM_SAB_IX_DATA:
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index_ix = mmio[mmSAM_SAB_IX_INDEX];
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DPRINTF("mmSAM_SAB_IX_DATA_read { index: %X }", index_ix);
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value = sam_sab_ix[index_ix];
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break;
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// Simple registers
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case mmSAM_GPR_SCRATCH_0:
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case mmSAM_GPR_SCRATCH_1:
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case mmSAM_GPR_SCRATCH_2:
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case mmSAM_GPR_SCRATCH_3:
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value = mmio[index];
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break;
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default:
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DPRINTF("index=0x%llX, size=0x%llX", index, size);
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assert_always("Unimplemented");
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@ -222,39 +192,26 @@ void LiverpoolGCDevice::mmio_write(U64 addr, U64 value, U64 size) {
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else if (GMC_MMIO_VM.contains(index)) {
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gmc.mmio_write(index, value);
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}
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else if (GMC_MMIO_MC.contains(index)) {
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else if (GMC_MMIO_VM.contains(index)
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|| GMC_MMIO_MC.contains(index)) {
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gmc.mmio_write(index, value);
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return;
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}
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else if (OSS_MMIO_IH.contains(index)) {
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ih.mmio_write(index, value);
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return;
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}
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else if (SMU_MMIO.contains(index)) {
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smu.mmio_write(index, value);
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return;
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}
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else if (SAM_MMIO.contains(index)) {
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sam.mmio_write(index, value);
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return;
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}
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// Indirect registers
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switch (index) {
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case mmSAM_IX_DATA:
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switch (mmio[mmSAM_IX_INDEX]) {
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case ixSAM_IH_CPU_AM32_INT:
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update_sam(value);
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break;
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case ixSAM_IH_AM32_CPU_INT_ACK:
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sam_ix[ixSAM_IH_CPU_AM32_INT_STATUS] = 0;
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break;
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default:
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index_ix = mmio[mmSAM_IX_INDEX];
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DPRINTF("mmSAM_IX_DATA_write { index: %X, value: %llX }", index_ix, value);
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sam_ix[index_ix] = value;
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}
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return;
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case mmSAM_SAB_IX_DATA:
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switch (mmio[mmSAM_SAB_IX_INDEX]) {
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default:
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index_ix = mmio[mmSAM_SAB_IX_INDEX];
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DPRINTF("mmSAM_SAB_IX_DATA_write { index: %X, value: %llX }", index_ix, value);
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sam_sab_ix[index_ix] = value;
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}
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return;
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case mmMM_DATA:
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mmio_write(mmio[mmMM_INDEX], value, size);
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return;
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@ -268,10 +225,6 @@ void LiverpoolGCDevice::mmio_write(U64 addr, U64 value, U64 size) {
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mmio[mmACP_SOFT_RESET] = (value << 16);
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break;
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// SMU
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case mmSMC_IND_INDEX:
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break;
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// GCA
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case mmGRBM_GFX_INDEX:
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case mmRLC_PG_ALWAYS_ON_CU_MASK:
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@ -358,23 +311,3 @@ void LiverpoolGCDevice::mmio_write(U64 addr, U64 value, U64 size) {
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assert_always("Unimplemented");
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}
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}
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void LiverpoolGCDevice::update_sam(U32 value) {
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U64 query_addr;
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U64 reply_addr;
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assert(value == 1);
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query_addr = sam_ix[ixSAM_IH_CPU_AM32_INT_CTX_HIGH];
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query_addr = sam_ix[ixSAM_IH_CPU_AM32_INT_CTX_LOW] | (query_addr << 32);
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query_addr &= 0xFFFFFFFFFFFFULL;
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reply_addr = sam_ix[ixSAM_IH_AM32_CPU_INT_CTX_HIGH];
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reply_addr = sam_ix[ixSAM_IH_AM32_CPU_INT_CTX_LOW] | (reply_addr << 32);
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reply_addr &= 0xFFFFFFFFFFFFULL;
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const U16 flags = query_addr >> 48;
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DPRINTF("flags=0x%llX, query=0x%llX, reply=0x%llX\n", flags, query_addr, reply_addr);
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sam_ix[ixSAM_IH_CPU_AM32_INT_STATUS] = 0;// 1;
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sam_ix[ixSAM_IH_AM32_CPU_INT_STATUS] |= 1;
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}
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@ -15,6 +15,7 @@
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// Engines
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#include "gmc/gmc.h"
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#include "oss/ih.h"
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#include "smu/smu.h"
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#include <array>
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#include <memory>
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@ -66,16 +67,9 @@ private:
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U64 mmio_read(U64 addr, U64 size);
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void mmio_write(U64 addr, U64 value, U64 size);
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// GMC
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// Engines
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GmcDevice gmc;
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// OSS
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IhDevice ih;
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// SAMU
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std::unique_ptr<SAMUDevice> sam;
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std::array<U32, 0x80> sam_ix;
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std::array<U32, 0x40> sam_sab_ix;
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void update_sam(U32 value);
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SmuDevice smu;
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SamDevice sam;
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};
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206
src/orbital/hardware/liverpool/sam/sam.cpp
Normal file
206
src/orbital/hardware/liverpool/sam/sam.cpp
Normal file
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@ -0,0 +1,206 @@
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/**
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* AMD Secure Asset Management Unit (SAMU) device.
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*
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* Copyright 2017-2021. Orbital project.
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* Released under MIT license. Read LICENSE for more details.
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*
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* Authors:
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* - Alexandro Sanchez Bach <alexandro@phi.nz>
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*/
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#include "sam.h"
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#include <orbital/hardware/liverpool/gmc/gmc.h>
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#include <orbital/hardware/liverpool/oss/ih.h>
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#include <orbital/hardware/liverpool/smu/smu.h>
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// SBL
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constexpr U32 SBL_INT_UNKA202 = 0xA202;
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constexpr U32 SBL_INT_UNKA303 = 0xA303;
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constexpr U32 SBL_INT_SMU_READ = 0xA404;
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constexpr U32 SBL_INT_SMU_WRITE = 0xA505;
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// Logging
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#define DEBUG_SAM 1
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#define DPRINTF(...) \
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do { \
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if (DEBUG_SAM) { \
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fprintf(stderr, "lvp-sam (%s:%d): ", __FUNCTION__, __LINE__); \
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fprintf(stderr, __VA_ARGS__); \
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fprintf(stderr, "\n"); \
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} \
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} while (0)
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SamDevice::SamDevice(GmcDevice& gmc, IhDevice& ih, SmuDevice& smu)
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: Device(nullptr), gmc(gmc), ih(ih), smu(smu) {
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reset();
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}
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void SamDevice::reset() {
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gpr.fill(0);
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ih_cpu_am32_int_ctx = 0;
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ih_am32_cpu_int_ctx = 0;
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ix_data.fill(0);
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sab_ix_data.fill(0);
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}
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U32 SamDevice::mmio_read(U32 index) {
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U32 value = 0;
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switch (index) {
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case mmSAM_IX_INDEX:
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value = sam_ix_index;
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break;
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case mmSAM_IX_DATA:
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switch (sam_ix_index) {
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case ixSAM_IH_CPU_AM32_INT_CTX_HIGH:
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value = ih_cpu_am32_int_ctx_high;
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break;
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case ixSAM_IH_CPU_AM32_INT_CTX_LOW:
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value = ih_cpu_am32_int_ctx_low;
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break;
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case ixSAM_IH_AM32_CPU_INT_CTX_HIGH:
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value = ih_am32_cpu_int_ctx_high;
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break;
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case ixSAM_IH_AM32_CPU_INT_CTX_LOW:
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value = ih_am32_cpu_int_ctx_low;
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break;
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default:
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DPRINTF("mmSAM_IX_DATA_read { index: %X }", sam_ix_index);
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value = ix_data[sam_ix_index];
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}
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break;
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case mmSAM_SAB_IX_INDEX:
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value = sam_sab_ix_index;
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break;
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case mmSAM_SAB_IX_DATA:
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DPRINTF("mmSAM_SAB_IX_DATA_read { index: %X }", sam_sab_ix_index);
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value = sab_ix_data[sam_sab_ix_index];
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break;
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case mmSAM_GPR_SCRATCH_0:
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value = gpr[0];
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break;
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case mmSAM_GPR_SCRATCH_1:
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value = gpr[1];
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break;
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case mmSAM_GPR_SCRATCH_2:
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value = gpr[2];
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break;
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case mmSAM_GPR_SCRATCH_3:
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value = gpr[3];
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break;
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default:
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assert_always("Unimplemented");
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}
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return value;
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}
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void SamDevice::mmio_write(U32 index, U32 value) {
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switch (index) {
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case mmSAM_IX_INDEX:
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sam_ix_index = value;
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break;
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case mmSAM_IX_DATA:
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switch (sam_ix_index) {
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case ixSAM_IH_CPU_AM32_INT:
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handle_request(value);
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break;
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case ixSAM_IH_CPU_AM32_INT_CTX_HIGH:
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ih_cpu_am32_int_ctx_high = value;
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break;
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case ixSAM_IH_CPU_AM32_INT_CTX_LOW:
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ih_cpu_am32_int_ctx_low = value;
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break;
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case ixSAM_IH_AM32_CPU_INT_CTX_HIGH:
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ih_am32_cpu_int_ctx_high = value;
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break;
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case ixSAM_IH_AM32_CPU_INT_CTX_LOW:
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ih_am32_cpu_int_ctx_low = value;
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break;
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case ixSAM_IH_AM32_CPU_INT_ACK:
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//sam_ix[ixSAM_IH_AM32_CPU_INT_STATUS] = 0;
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ix_data[ixSAM_IH_CPU_AM32_INT_STATUS] = 0;
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break;
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default:
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DPRINTF("mmSAM_IX_DATA_write { index: %X, value: %llX }", sam_ix_index, value);
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ix_data[sam_ix_index] = value;
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}
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break;
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case mmSAM_SAB_IX_INDEX:
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sam_sab_ix_index = value;
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break;
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case mmSAM_SAB_IX_DATA:
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switch (sam_sab_ix_index) {
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default:
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DPRINTF("mmSAM_SAB_IX_DATA_write { index: %X, value: %llX }", sam_sab_ix_index, value);
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ix_data[sam_sab_ix_index] = value;
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}
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break;
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case mmSAM_GPR_SCRATCH_0:
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gpr[0] = value;
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break;
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case mmSAM_GPR_SCRATCH_1:
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gpr[1] = value;
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break;
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case mmSAM_GPR_SCRATCH_2:
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gpr[2] = value;
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break;
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case mmSAM_GPR_SCRATCH_3:
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gpr[3] = value;
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break;
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default:
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assert_always("Unimplemented");
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}
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}
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void SamDevice::handle_request(U32 value) {
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const auto query_addr = ih_cpu_am32_int_ctx & UINT64_C(0xFFFFFFFFFFFF);
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const auto reply_addr = ih_am32_cpu_int_ctx & UINT64_C(0xFFFFFFFFFFFF);
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assert(value == 1);
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const U16 flags = ih_cpu_am32_int_flags;
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DPRINTF("flags=0x%llX, query=0x%llX, reply=0x%llX\n", flags, query_addr, reply_addr);
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if (flags == 0) {
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const auto id = gpr[0];
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switch (id) {
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case SBL_INT_UNKA202:
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assert_always("Unimplemented");
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break;
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case SBL_INT_UNKA303:
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assert_always("Unimplemented");
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break;
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case SBL_INT_SMU_READ:
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gpr[2] = smu.smc_read(gpr[1]);
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gpr[3] = 0;
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break;
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case SBL_INT_SMU_WRITE:
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smu.smc_write(gpr[1], gpr[2]);
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gpr[3] = 0;
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break;
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}
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ix_data[ixSAM_IH_CPU_AM32_INT_STATUS] = 0;// 1;
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ix_data[ixSAM_IH_AM32_CPU_INT_STATUS] |= 1;
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return;
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}
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else {
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#if 0
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||||
uint32_t command = ldl_le_phys(s->gart.as[15 /*gart->as[SAMU_VMID] */], query_addr);
|
||||
if (command == 0) {
|
||||
liverpool_gc_samu_init(&s->samu, query_addr);
|
||||
}
|
||||
else {
|
||||
liverpool_gc_samu_packet(&s->samu, query_addr, reply_addr);
|
||||
}
|
||||
|
||||
if (command == SAMU_CMD_SERVICE_RAND || command == 0) {
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
ix_data[ixSAM_IH_CPU_AM32_INT_STATUS] = 0;//1
|
||||
ix_data[ixSAM_IH_AM32_CPU_INT_STATUS] |= 1;
|
||||
ih.push_iv(0, IV_SRCID_SAM, 0 /* TODO */);
|
||||
}
|
||||
}
|
||||
|
|
@ -12,6 +12,16 @@
|
|||
|
||||
#pragma once
|
||||
|
||||
#include <orbital/core.h>
|
||||
#include <orbital/offset_range.h>
|
||||
|
||||
// Forward declarations
|
||||
class GmcDevice;
|
||||
class IhDevice;
|
||||
class SmuDevice;
|
||||
|
||||
constexpr auto SAM_MMIO = OffsetRange(0x8800, 0x20);
|
||||
|
||||
// SAMU
|
||||
#define mmSAM_IX_INDEX 0x00008800
|
||||
#define mmSAM_IX_DATA 0x00008801
|
||||
|
|
@ -31,6 +41,7 @@
|
|||
#define ixSAM_IH_AM32_CPU_INT_CTX_HIGH 0x00000035
|
||||
#define ixSAM_IH_AM32_CPU_INT_CTX_LOW 0x00000036
|
||||
#define ixSAM_IH_AM32_CPU_INT_ACK 0x00000037
|
||||
#define ixSAM_UNK3E 0x0000003E
|
||||
#define ixSAM_IH_CPU_AM32_INT_STATUS 0x0000004A
|
||||
#define ixSAM_IH_AM32_CPU_INT_STATUS 0x0000004B
|
||||
#define ixSAM_RST_HOST_SOFT_RST_RDY 0x00000051
|
||||
|
|
@ -126,6 +137,41 @@ struct samu_command_service_rand_t {
|
|||
LE<U08> data[0x10];
|
||||
};
|
||||
|
||||
class SAMUDevice : public Device {
|
||||
class SamDevice : public Device {
|
||||
public:
|
||||
SamDevice(GmcDevice& gmc, IhDevice& ih, SmuDevice& smu);
|
||||
|
||||
void reset();
|
||||
|
||||
U32 mmio_read(U32 index);
|
||||
void mmio_write(U32 index, U32 value);
|
||||
|
||||
private:
|
||||
GmcDevice& gmc;
|
||||
IhDevice& ih;
|
||||
SmuDevice& smu;
|
||||
|
||||
std::array<U32, 4> gpr;
|
||||
std::array<U32, 0x80> ix_data;
|
||||
std::array<U32, 0x40> sab_ix_data;
|
||||
U32 sam_ix_index;
|
||||
U32 sam_sab_ix_index;
|
||||
|
||||
union {
|
||||
LE<U64> ih_cpu_am32_int_ctx;
|
||||
Bitfield<U64, 48, 16> ih_cpu_am32_int_flags;
|
||||
struct {
|
||||
LE<U32> ih_cpu_am32_int_ctx_low;
|
||||
LE<U32> ih_cpu_am32_int_ctx_high;
|
||||
};
|
||||
};
|
||||
union {
|
||||
LE<U64> ih_am32_cpu_int_ctx;
|
||||
struct {
|
||||
LE<U32> ih_am32_cpu_int_ctx_low;
|
||||
LE<U32> ih_am32_cpu_int_ctx_high;
|
||||
};
|
||||
};
|
||||
|
||||
void handle_request(U32 value);
|
||||
};
|
||||
|
|
|
|||
94
src/orbital/hardware/liverpool/smu/smu.cpp
Normal file
94
src/orbital/hardware/liverpool/smu/smu.cpp
Normal file
|
|
@ -0,0 +1,94 @@
|
|||
/**
|
||||
* AMD System Management Unit (SMU) device.
|
||||
*
|
||||
* Copyright 2017-2021. Orbital project.
|
||||
* Released under MIT license. Read LICENSE for more details.
|
||||
*
|
||||
* Authors:
|
||||
* - Alexandro Sanchez Bach <alexandro@phi.nz>
|
||||
*/
|
||||
|
||||
#include "smu.h"
|
||||
#include <orbital/hardware/liverpool/gmc/gmc.h>
|
||||
#include <orbital/hardware/liverpool/oss/ih.h>
|
||||
|
||||
#include "smu_7_1_2_d.h"
|
||||
#include "smu_7_1_2_sh_mask.h"
|
||||
|
||||
SmuDevice::SmuDevice(GmcDevice& gmc, IhDevice& ih)
|
||||
: Device(nullptr), gmc(gmc), ih(ih) {
|
||||
reset();
|
||||
}
|
||||
|
||||
void SmuDevice::reset() {
|
||||
}
|
||||
|
||||
U32 SmuDevice::mmio_read(U32 index) {
|
||||
U32 value = 0;
|
||||
|
||||
switch (index) {
|
||||
case mmSMC_IND_INDEX:
|
||||
value = smc_ix;
|
||||
break;
|
||||
case mmSMC_IND_DATA:
|
||||
value = smc_read(smc_ix);
|
||||
break;
|
||||
default:
|
||||
assert_always("Unimplemented");
|
||||
}
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
void SmuDevice::mmio_write(U32 index, U32 value) {
|
||||
switch (index) {
|
||||
case mmSMC_IND_INDEX:
|
||||
smc_ix = value;
|
||||
break;
|
||||
case mmSMC_IND_DATA:
|
||||
smc_write(smc_ix, value);
|
||||
break;
|
||||
default:
|
||||
assert_always("Unimplemented");
|
||||
}
|
||||
}
|
||||
|
||||
U32 SmuDevice::smc_read(U32 index) {
|
||||
U32 value = 0;
|
||||
|
||||
switch (index) {
|
||||
case 0xC2100004:
|
||||
value = 0x2 | 0x1;
|
||||
break;
|
||||
case 0xC0500090:
|
||||
value = 0x1;
|
||||
break;
|
||||
case 0xC0500098:
|
||||
value = 0x1;
|
||||
break;
|
||||
case ixCG_DCLK_STATUS:
|
||||
value = 0x1;
|
||||
break;
|
||||
case ixCG_VCLK_STATUS:
|
||||
value = 0x1;
|
||||
break;
|
||||
case ixCG_ECLK_STATUS:
|
||||
value = 0x1;
|
||||
break;
|
||||
case 0xC05000E0:
|
||||
value = 0x1;
|
||||
break;
|
||||
case 0xC05000E8:
|
||||
value = 0x1;
|
||||
break;
|
||||
default:
|
||||
//assert_always("Unimplemented");
|
||||
break;
|
||||
}
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
void SmuDevice::smc_write(U32 index, U32 value) {
|
||||
//assert_always("Unimplemented");
|
||||
}
|
||||
39
src/orbital/hardware/liverpool/smu/smu.h
Normal file
39
src/orbital/hardware/liverpool/smu/smu.h
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
/**
|
||||
* AMD System Management Unit (SMU) device.
|
||||
*
|
||||
* Copyright 2017-2021. Orbital project.
|
||||
* Released under MIT license. Read LICENSE for more details.
|
||||
*
|
||||
* Authors:
|
||||
* - Alexandro Sanchez Bach <alexandro@phi.nz>
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <orbital/core.h>
|
||||
#include <orbital/offset_range.h>
|
||||
|
||||
// Forward declarations
|
||||
class GmcDevice;
|
||||
class IhDevice;
|
||||
|
||||
constexpr auto SMU_MMIO = OffsetRange(0x80, 0x40);
|
||||
|
||||
class SmuDevice : public Device {
|
||||
public:
|
||||
SmuDevice(GmcDevice& gmc, IhDevice& ih);
|
||||
|
||||
void reset();
|
||||
|
||||
U32 mmio_read(U32 index);
|
||||
void mmio_write(U32 index, U32 value);
|
||||
|
||||
U32 smc_read(U32 index);
|
||||
void smc_write(U32 index, U32 value);
|
||||
|
||||
private:
|
||||
GmcDevice& gmc;
|
||||
IhDevice& ih;
|
||||
|
||||
U32 smc_ix;
|
||||
};
|
||||
Loading…
Reference in a new issue