mirror of
https://github.com/gligli/nulldc-360.git
synced 2025-04-02 11:11:56 -04:00
159 lines
No EOL
5.8 KiB
C
159 lines
No EOL
5.8 KiB
C
#pragma once
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typedef u8 uint8_t;
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typedef u16 uint16_t;
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typedef u32 uint32_t;
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typedef u64 uint64_t;
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typedef u32 uint32;
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typedef s8 int8_t;
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typedef s16 int16_t;
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typedef s32 int32_t;
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typedef s64 int64_t;
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#define le64_to_cpu(x) (x)
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#define le32_to_cpu(x) (x)
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#define le16_to_cpu(x) (x)
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#define cpu_to_le64(x) (x)
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#define cpu_to_le32(x) (x)
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#define cpu_to_le16(x) (x)
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#define cpu_to_be16(x) ( (((u8)(x))<<8) | ((u8)((x)>>8)) )
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#define be16_to_cpu(x) ( (((u8)(x))<<8) | ((u8)((x)>>8)) )
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#define be32_to_cpu(val) ((u32) ( \
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(((u32) (val) & (u32) 0x000000ffU) << 24) | \
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(((u32) (val) & (u32) 0x0000ff00U) << 8) | \
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(((u32) (val) & (u32) 0x00ff0000U) >> 8) | \
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(((u32) (val) & (u32) 0xff000000U) >> 24)))
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#define cpu_to_be32(val) ((u32) ( \
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(((u32) (val) & (u32) 0x000000ffU) << 24) | \
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(((u32) (val) & (u32) 0x0000ff00U) << 8) | \
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(((u32) (val) & (u32) 0x00ff0000U) >> 8) | \
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(((u32) (val) & (u32) 0xff000000U) >> 24)))
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void cpu_physical_memory_write(u32 addr,const void* buff,u32 sz);
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void cpu_physical_memory_read(u32 addr,void* buff,u32 sz);
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#define target_phys_addr_t u32
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#define QEMUFile void*
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struct PCIDevice;
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struct VLANClientState;
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struct QEMUTimer;
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struct NICInfo
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{
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uint8_t macaddr[6];
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};
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struct PCIBus;
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void rtl8139_resete(void* p);
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void qemu_send_packet(VLANClientState*,const uint8_t*, int,u32 fromaddr);
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typedef u32 net_receive(void *opaque, const uint8_t *buf, int size);
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typedef int net_can_receive(void *opaque);
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VLANClientState * qemu_new_vlan_client(void* ,net_receive* rc,net_can_receive* cr,void* opaq);
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void pci_set_irq(PCIDevice* dev,u32 duno,u32 status);
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typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
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uint32_t address, uint32_t data, int len);
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typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
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uint32_t address, int len);
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typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
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uint32_t addr, uint32_t size, int type);
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#define PCI_ADDRESS_SPACE_MEM 0x00
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#define PCI_ADDRESS_SPACE_IO 0x01
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#define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
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typedef struct PCIIORegion {
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uint32_t addr; /* current PCI mapping address. -1 means not mapped */
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uint32_t size;
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uint8_t type;
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PCIMapIORegionFunc *map_func;
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} PCIIORegion;
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#define PCI_ROM_SLOT 6
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#define PCI_NUM_REGIONS 7
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#define PCI_DEVICES_MAX 64
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#define PCI_VENDOR_ID 0x00 /* 16 bits */
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#define PCI_DEVICE_ID 0x02 /* 16 bits */
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#define PCI_COMMAND 0x04 /* 16 bits */
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#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
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#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
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#define PCI_CLASS_DEVICE 0x0a /* Device class */
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#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
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#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
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#define PCI_MIN_GNT 0x3e /* 8 bits */
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#define PCI_MAX_LAT 0x3f /* 8 bits */
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struct PCIDevice {
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/* PCI config space */
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uint8_t config[256];
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/* the following fields are read only */
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PCIBus *bus;
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int devfn;
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char name[64];
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PCIIORegion io_regions[PCI_NUM_REGIONS];
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/* do not access the following fields */
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PCIConfigReadFunc *config_read;
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PCIConfigWriteFunc *config_write;
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/* ??? This is a PC-specific hack, and should be removed. */
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int irq_index;
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/* IRQ objects for the INTA-INTD pins. */
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// qemu_irq *irq;
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/* Current IRQ levels. Used internally by the generic PCI code. */
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int irq_state[4];
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};
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void pci_register_io_region(PCIDevice *pci_dev, int region_num,
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uint32_t size, int type,
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PCIMapIORegionFunc *map_func);
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PCIDevice *pci_register_device(PCIBus *bus, const char *name,
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int instance_size, int devfn,
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PCIConfigReadFunc *config_read,
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PCIConfigWriteFunc *config_write);
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void pci_register_io_region(PCIDevice *pci_dev, int region_num,
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uint32_t size, int type,
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PCIMapIORegionFunc *map_func);
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uint32_t pci_default_read_config(PCIDevice *d,
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uint32_t address, int len);
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void pci_default_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len);
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void pci_device_save(PCIDevice *s, QEMUFile *f);
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int pci_device_load(PCIDevice *s, QEMUFile *f);
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struct qemu_irq;
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typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
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typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
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PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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qemu_irq *pic, int devfn_min, int nirq);
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void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
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void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
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uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
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int pci_bus_num(PCIBus *s);
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void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
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void pci_info(void);
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PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
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pci_map_irq_fn map_irq, const char *name);
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PCIDevice* pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
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void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
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void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val);
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void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val);
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uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr);
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uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr);
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uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr); |