mirror of
https://github.com/gligli/nulldc-360.git
synced 2025-04-02 11:11:56 -04:00
421 lines
No EOL
15 KiB
C++
421 lines
No EOL
15 KiB
C++
#pragma once
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#include "types.h"
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using namespace std;
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#define REG_CLASS(regv) (regv>>16)
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#define REG_ID(regv) (regv&0xFFFF)
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enum reg_class
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{
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reg_GPR=0<<5,
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reg_FPR=0<<5,
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};
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//Enum of all registers
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enum ppc_reg
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{
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R0 = reg_GPR,
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R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17,
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R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31,
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FR0 = reg_FPR,
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FR1, FR2, FR3, FR4, FR5, FR6, FR7, FR8, FR9, FR10, FR11, FR12, FR13, FR14, FR15, FR16, FR17,
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FR18, FR19, FR20, FR21, FR22, FR23, FR24, FR25, FR26, FR27, FR28, FR29, FR30, FR31,
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//misc :p
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NO_REG=-1,
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ERROR_REG=-2,
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};
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extern int ppc_condition_flags[][3];
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#define ppc_fpr_reg ppc_reg
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#define ppc_gpr_reg ppc_reg
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// CR2 bit 2
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#define CR_T_FLAG 10
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#define CR_T_COND_FLAG 9
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#define RTMP 10
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#define RSH4R 2
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// altivec XF handling
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#define RXF0 20
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#define RXF4 (RXF0+1)
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#define RXF8 (RXF0+2)
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#define RXF12 (RXF0+3)
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#include "PowerPC.h"
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extern "C" {
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int disassemble(u32 a, u32 op);
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}
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//memory managment !
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typedef void* dyna_reallocFP(void*ptr,u32 oldsize,u32 newsize);
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typedef void* dyna_finalizeFP(void* ptr,u32 oldsize,u32 newsize);
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//define it here cus we use it on label type ;)
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class ppc_block;
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// a label
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class ppc_Label
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{
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public:
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u32 target_opcode;
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u8 patch_sz;
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ppc_block* owner;
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bool marked;
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void* GetPtr();
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};
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//An empty type that we will use as ptr type.This is ptr-reference
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struct ppc_ptr
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{
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union
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{
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void* ptr;
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unat ptr_int;
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};
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static ppc_ptr create(unat ptr);
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ppc_ptr(void* ptr)
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{
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this->ptr=ptr;
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}
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};
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//This is ptr/imm (for call/jmp)
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struct ppc_ptr_imm
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{
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union
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{
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void* ptr;
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unat ptr_int;
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};
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static ppc_ptr_imm create(unat ptr);
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ppc_ptr_imm(void* ptr)
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{
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this->ptr=ptr;
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}
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};
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struct code_patch
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{
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u8 type;//0 = 8 bit , 2 = 16 bit , 4 = 32 bit , 16[flag] is label
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union
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{
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void* dest; //ptr for patch
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ppc_Label* lbl; //lbl for patch
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};
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u32 offset; //offset in opcode stream :)
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};
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struct ppc_block_externs
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{
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void Apply(void* code_base);
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bool Modify(u32 offs,u8* dst);
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void Free();
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~ppc_block_externs();
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};
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class ppc_block
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{
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private:
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vector<code_patch> patches;
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vector<ppc_Label*> labels;
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void ApplyPatches(u8* base);
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dyna_reallocFP* ralloc;
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dyna_finalizeFP* allocfin;
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u32 bc_tab[0x4000];
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u32 bc_tab_next_idx;
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public:
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u8* ppc_buff;
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u32 ppc_indx;
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u32 ppc_size;
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bool do_realloc;
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bool do_disasm;
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bool do_disasm_imm;
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ppc_block();
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~ppc_block();
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void ppc_buffer_ensure(u32 size);
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void write8(u32 value);
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void write16(u32 value);
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void write32(u32 value);
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//init things
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void Init(dyna_reallocFP* ral,dyna_finalizeFP* alf);
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//Generates code.
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void* Generate();
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ppc_block_externs* GetExterns();
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//void CopyTo(void* to);
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//Will free any used resources exept generated code
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void Free();
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//Label related code
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//NOTE : Label position in mem must not chainge
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void CreateLabel(ppc_Label* lbl,bool mark,u32 sz);
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//Allocate a label and create it :).Will be delete'd when calling free and/or dtor
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ppc_Label* CreateLabel(bool mark,u32 sz);
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void MarkLabel(ppc_Label* lbl);
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//When we want to keep info to mark opcodes dead , there is no need to create labels :p
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//Get an index to next emitted opcode
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u32 GetOpcodeIndex();
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ppc_gpr_reg getHighReg(u16 value);
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void emitBranch(void * addr, int lk);
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void emitLongBranch(void * addr, int lk);
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void emitBranchConditional(void * addr, int bo, int bi, int lk, int force_short);
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void emitLoadDouble(ppc_fpr_reg reg, void * addr);
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void emitLoadFloat(ppc_fpr_reg reg, void * addr);
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void emitLoad32(ppc_gpr_reg reg, void * addr);
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void emitLoad16(ppc_gpr_reg reg, void * addr);
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void emitLoad8(ppc_gpr_reg reg, void * addr);
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void emitStoreDouble(void * addr, ppc_fpr_reg reg);
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void emitStoreFloat(void * addr, ppc_fpr_reg reg);
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void emitStore32(void * addr, ppc_gpr_reg reg);
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void emitStore16(void * addr, ppc_gpr_reg reg);
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void emitStore8(void * addr, ppc_gpr_reg reg);
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void emitMoveRegister(ppc_gpr_reg to,ppc_gpr_reg from);
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void emitLoadImmediate32(ppc_gpr_reg reg, u32 val);
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void emitBranchConditionalToLabel(ppc_Label * lab,int lk,int bo,int bi);
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void emitBranchToLabel(ppc_Label * lab,int lk);
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void emitDebugValue(u32 value);
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void emitDebugReg(ppc_gpr_reg reg);
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void vectorWriteBack(u32 reg);
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void vectorReload(u32 reg);
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};
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#define EMIT_B(ppce,dst,aa,lk) \
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{PowerPC_instr ppc;GEN_B(ppc,dst,aa,lk);ppce->write32(ppc);}
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#define EMIT_MTCTR(ppce,rs) \
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{PowerPC_instr ppc;GEN_MTCTR(ppc,rs);ppce->write32(ppc);}
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#define EMIT_MFCTR(ppce,rd) \
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{PowerPC_instr ppc;GEN_MFCTR(ppc,rd);ppce->write32(ppc);}
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#define EMIT_ADDIS(ppce,rd,ra,immed) \
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{PowerPC_instr ppc;GEN_ADDIS(ppc,rd,ra,immed);ppce->write32(ppc);}
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#define EMIT_LIS(ppce,rd,immed) \
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{PowerPC_instr ppc;GEN_LIS(ppc,rd,immed);ppce->write32(ppc);}
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#define EMIT_LI(ppce,rd,immed) \
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{PowerPC_instr ppc;GEN_LI(ppc,rd,immed);ppce->write32(ppc);}
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#define EMIT_LWZ(ppce,rd,immed,ra) \
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{PowerPC_instr ppc;GEN_LWZ(ppc,rd,immed,ra);ppce->write32(ppc);}
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#define EMIT_LHZ(ppce,rd,immed,ra) \
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{PowerPC_instr ppc;GEN_LHZ(ppc,rd,immed,ra);ppce->write32(ppc);}
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#define EMIT_LHA(ppce,rd,immed,ra) \
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{PowerPC_instr ppc;GEN_LHA(ppc,rd,immed,ra);ppce->write32(ppc);}
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#define EMIT_LBZ(ppce,rd,immed,ra) \
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{PowerPC_instr ppc;GEN_LBZ(ppc,rd,immed,ra);ppce->write32(ppc);}
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#define EMIT_EXTSB(ppce,rd,rs) \
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{PowerPC_instr ppc;GEN_EXTSB(ppc,rd,rs);ppce->write32(ppc);}
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#define EMIT_EXTSH(ppce,rd,rs) \
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{PowerPC_instr ppc;GEN_EXTSH(ppc,rd,rs);ppce->write32(ppc);}
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#define EMIT_EXTSW(ppce,rd,rs) \
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{PowerPC_instr ppc;GEN_EXTSW(ppc,rd,rs);ppce->write32(ppc);}
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#define EMIT_STB(ppce,rs,immed,ra) \
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{PowerPC_instr ppc;GEN_STB(ppc,rs,immed,ra);ppce->write32(ppc);}
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#define EMIT_STH(ppce,rs,immed,ra) \
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{PowerPC_instr ppc;GEN_STH(ppc,rs,immed,ra);ppce->write32(ppc);}
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#define EMIT_STW(ppce,rs,immed,ra) \
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{PowerPC_instr ppc;GEN_STW(ppc,rs,immed,ra);ppce->write32(ppc);}
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#define EMIT_BCTR(ppce) \
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{PowerPC_instr ppc;GEN_BCTR(ppc);ppce->write32(ppc);}
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#define EMIT_BCTRL(ppce) \
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{PowerPC_instr ppc;GEN_BCTRL(ppc);ppce->write32(ppc);}
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#define EMIT_BCCTR(ppce,bo,bi,lk) \
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{PowerPC_instr ppc;GEN_BCCTR(ppc,bo,bi,lk);ppce->write32(ppc);}
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#define EMIT_CMP(ppce,ra,rb,cr) \
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{PowerPC_instr ppc;GEN_CMP(ppc,ra,rb,cr);ppce->write32(ppc);}
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#define EMIT_CMPL(ppce,ra,rb,cr) \
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{PowerPC_instr ppc;GEN_CMPL(ppc,ra,rb,cr);ppce->write32(ppc);}
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#define EMIT_CMPI(ppce,ra,immed,cr) \
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{PowerPC_instr ppc;GEN_CMPI(ppc,ra,immed,cr);ppce->write32(ppc);}
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#define EMIT_CMPLI(ppce,ra,immed,cr) \
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{PowerPC_instr ppc;GEN_CMPLI(ppc,ra,immed,cr);ppce->write32(ppc);}
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#define EMIT_BC(ppce,dst,aa,lk,bo,bi) \
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{PowerPC_instr ppc;GEN_BC(ppc,dst,aa,lk,bo,bi);ppce->write32(ppc);}
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#define EMIT_BNE(ppce,cr,dst,aa,lk) \
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{PowerPC_instr ppc;GEN_BNE(ppc,cr,dst,aa,lk);ppce->write32(ppc);}
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#define EMIT_BEQ(ppce,cr,dst,aa,lk) \
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{PowerPC_instr ppc;GEN_BEQ(ppc,cr,dst,aa,lk);ppce->write32(ppc);}
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#define EMIT_BGT(ppce,cr,dst,aa,lk) \
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{PowerPC_instr ppc;GEN_BGT(ppc,cr,dst,aa,lk);ppce->write32(ppc);}
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#define EMIT_BLE(ppce,cr,dst,aa,lk) \
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{PowerPC_instr ppc;GEN_BLE(ppc,cr,dst,aa,lk);ppce->write32(ppc);}
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#define EMIT_BGE(ppce,cr,dst,aa,lk) \
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{PowerPC_instr ppc;GEN_BGE(ppc,cr,dst,aa,lk);ppce->write32(ppc);}
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#define EMIT_BLT(ppce,cr,dst,aa,lk) \
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{PowerPC_instr ppc;GEN_BLT(ppc,cr,dst,aa,lk);ppce->write32(ppc);}
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#define EMIT_ADDI(ppce,rd,ra,immed) \
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{PowerPC_instr ppc;GEN_ADDI(ppc,rd,ra,immed);ppce->write32(ppc);}
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#define EMIT_RLWINM(ppce,rd,ra,sh,mb,me) \
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{PowerPC_instr ppc;GEN_RLWINM(ppc,rd,ra,sh,mb,me);ppce->write32(ppc);}
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#define EMIT_RLWIMI(ppce,rd,ra,sh,mb,me) \
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{PowerPC_instr ppc;GEN_RLWIMI(ppc,rd,ra,sh,mb,me);ppce->write32(ppc);}
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#define EMIT_SRWI(ppce,rd,ra,sh) \
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{PowerPC_instr ppc;GEN_SRWI(ppc,rd,ra,sh);ppce->write32(ppc);}
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#define EMIT_SLWI(ppce,rd,ra,sh) \
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{PowerPC_instr ppc;GEN_SLWI(ppc,rd,ra,sh);ppce->write32(ppc);}
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#define EMIT_SRAWI(ppce,rd,ra,sh) \
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{PowerPC_instr ppc;GEN_SRAWI(ppc,rd,ra,sh);ppce->write32(ppc);}
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#define EMIT_SLW(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_SLW(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_SRW(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_SRW(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_SRAW(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_SRAW(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_ANDI(ppce,rd,ra,immed) \
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{PowerPC_instr ppc;GEN_ANDI(ppc,rd,ra,immed);ppce->write32(ppc);}
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#define EMIT_ORI(ppce,rd,ra,immed) \
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{PowerPC_instr ppc;GEN_ORI(ppc,rd,ra,immed);ppce->write32(ppc);}
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#define EMIT_XORI(ppce,rd,ra,immed) \
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{PowerPC_instr ppc;GEN_XORI(ppc,rd,ra,immed);ppce->write32(ppc);}
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#define EMIT_XORIS(ppce,rd,ra,immed) \
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{PowerPC_instr ppc;GEN_XORIS(ppc,rd,ra,immed);ppce->write32(ppc);}
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#define EMIT_MULLW(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_MULLW(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_MULHW(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_MULHW(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_MULHWU(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_MULHWU(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_DIVW(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_DIVW(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_DIVWU(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_DIVWU(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_ADD(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_ADD(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_SUBF(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_SUBF(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_SUBFC(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_SUBFC(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_SUBFE(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_SUBFE(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_ADDIC(ppce,rd,ra,immed) \
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{PowerPC_instr ppc;GEN_ADDIC(ppc,rd,ra,immed);ppce->write32(ppc);}
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#define EMIT_SUB(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_SUB(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_AND(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_AND(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_NAND(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_NAND(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_ANDC(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_ANDC(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_NOR(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_NOR(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_OR(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_OR(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_XOR(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_XOR(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_BLR(ppce,lk) \
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{PowerPC_instr ppc;GEN_BLR(ppc,lk);ppce->write32(ppc);}
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#define EMIT_MTLR(ppce,rs) \
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{PowerPC_instr ppc;GEN_MTLR(ppc,rs);ppce->write32(ppc);}
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#define EMIT_MFLR(ppce,rd) \
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{PowerPC_instr ppc;GEN_MFLR(ppc,rd);ppce->write32(ppc);}
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#define EMIT_MTCR(ppce,rs) \
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{PowerPC_instr ppc;GEN_MTCR(ppc,rs);ppce->write32(ppc);}
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#define EMIT_NEG(ppce,rd,rs) \
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{PowerPC_instr ppc;GEN_NEG(ppc,rd,rs);ppce->write32(ppc);}
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#define EMIT_EQV(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_EQV(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_ADDZE(ppce,rd,rs) \
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{PowerPC_instr ppc;GEN_ADDZE(ppc,rd,rs);ppce->write32(ppc);}
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#define EMIT_ADDC(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_ADDC(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_ADDE(ppce,rd,ra,rb) \
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{PowerPC_instr ppc;GEN_ADDE(ppc,rd,ra,rb);ppce->write32(ppc);}
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#define EMIT_SUBFIC(ppce,rd,ra,immed) \
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{PowerPC_instr ppc;GEN_SUBFIC(ppc,rd,ra,immed);ppce->write32(ppc);}
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#define EMIT_STFD(ppce,fs,immed,rb) \
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{PowerPC_instr ppc;GEN_STFD(ppc,fs,immed,rb);ppce->write32(ppc);}
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#define EMIT_STFS(ppce,fs,immed,rb) \
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{PowerPC_instr ppc;GEN_STFS(ppc,fs,immed,rb);ppce->write32(ppc);}
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#define EMIT_LFD(ppce,fd,immed,rb) \
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{PowerPC_instr ppc;GEN_LFD(ppc,fd,immed,rb);ppce->write32(ppc);}
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#define EMIT_LFS(ppce,fd,immed,rb) \
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{PowerPC_instr ppc;GEN_LFS(ppc,fd,immed,rb);ppce->write32(ppc);}
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#define EMIT_FADD(ppce,fd,fa,fb,dbl) \
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{PowerPC_instr ppc;GEN_FADD(ppc,fd,fa,fb,dbl);ppce->write32(ppc);}
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#define EMIT_FSUB(ppce,fd,fa,fb,dbl) \
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{PowerPC_instr ppc;GEN_FSUB(ppc,fd,fa,fb,dbl);ppce->write32(ppc);}
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#define EMIT_FMUL(ppce,fd,fa,fb,dbl) \
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{PowerPC_instr ppc;GEN_FMUL(ppc,fd,fa,fb,dbl);ppce->write32(ppc);}
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#define EMIT_FDIV(ppce,fd,fa,fb,dbl) \
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{PowerPC_instr ppc;GEN_FDIV(ppc,fd,fa,fb,dbl);ppce->write32(ppc);}
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#define EMIT_FABS(ppce,fd,fs) \
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{PowerPC_instr ppc;GEN_FABS(ppc,fd,fs);ppce->write32(ppc);}
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#define EMIT_FCFID(ppce,fd,fs) \
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{PowerPC_instr ppc;GEN_FCFID(ppc,fd,fs);ppce->write32(ppc);}
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#define EMIT_FRSP(ppce,fd,fs) \
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{PowerPC_instr ppc;GEN_FRSP(ppc,fd,fs);ppce->write32(ppc);}
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#define EMIT_FMR(ppce,fd,fs) \
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{PowerPC_instr ppc;GEN_FMR(ppc,fd,fs);ppce->write32(ppc);}
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#define EMIT_FNEG(ppce,fd,fs) \
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{PowerPC_instr ppc;GEN_FNEG(ppc,fd,fs);ppce->write32(ppc);}
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#define EMIT_FCTIW(ppce,fd,fs) \
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{PowerPC_instr ppc;GEN_FCTIW(ppc,fd,fs);ppce->write32(ppc);}
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#define EMIT_FCTIWZ(ppce,fd,fs) \
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{PowerPC_instr ppc;GEN_FCTIWZ(ppc,fd,fs);ppce->write32(ppc);}
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#define EMIT_STFIWX(ppce,fs,ra,rb) \
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{PowerPC_instr ppc;GEN_STFIWX(ppc,fs,ra,rb);ppce->write32(ppc);}
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#define EMIT_MTFSFI(ppce,field,immed) \
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{PowerPC_instr ppc;GEN_MTFSFI(ppc,field,immed);ppce->write32(ppc);}
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#define EMIT_MTFSF(ppce,fields,fs) \
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{PowerPC_instr ppc;GEN_MTFSF(ppc,fields,fs);ppce->write32(ppc);}
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#define EMIT_FCMPU(ppce,fa,fb,cr) \
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{PowerPC_instr ppc;GEN_FCMPU(ppc,fa,fb,cr);ppce->write32(ppc);}
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#define EMIT_FRSQRTE(ppce,fd,fs) \
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{PowerPC_instr ppc;GEN_FRSQRTE(ppc,fd,fs);ppce->write32(ppc);}
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#define EMIT_FSQRT(ppce,fd,fs) \
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{PowerPC_instr ppc;GEN_FSQRT(ppc,fd,fs);ppce->write32(ppc);}
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#define EMIT_FSQRTS(ppce,fd,fs) \
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{PowerPC_instr ppc;GEN_FSQRTS(ppc,fd,fs);ppce->write32(ppc);}
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#define EMIT_FSEL(ppce,fd,fa,fb,fc) \
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{PowerPC_instr ppc;GEN_FSEL(ppc,fd,fa,fb,fc);ppce->write32(ppc);}
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#define EMIT_FRES(ppce,fd,fs) \
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{PowerPC_instr ppc;GEN_FRES(ppc,fd,fs);ppce->write32(ppc);}
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#define EMIT_FNMSUB(ppce,fd,fa,fc,fb) \
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{PowerPC_instr ppc;GEN_FNMSUB(ppc,fd,fa,fc,fb);ppce->write32(ppc);}
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#define EMIT_FNMSUBS(ppce,fd,fa,fc,fb) \
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{PowerPC_instr ppc;GEN_FNMSUBS(ppc,fd,fa,fc,fb);ppce->write32(ppc);}
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#define EMIT_FMADD(ppce,fd,fa,fc,fb) \
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{PowerPC_instr ppc;GEN_FMADD(ppc,fd,fa,fc,fb);ppce->write32(ppc);}
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#define EMIT_FMADDS(ppce,fd,fa,fc,fb) \
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{PowerPC_instr ppc;GEN_FMADDS(ppc,fd,fa,fc,fb);ppce->write32(ppc);}
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#define EMIT_BCLR(ppce,lk,bo,bi) \
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{PowerPC_instr ppc;GEN_BCLR(ppc,lk,bo,bi);ppce->write32(ppc);}
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#define EMIT_BNELR(ppce,cr,lk) \
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{PowerPC_instr ppc;GEN_BNELR(ppc,cr,lk);ppce->write32(ppc);}
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#define EMIT_BLELR(ppce,cr,lk) \
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{PowerPC_instr ppc;GEN_BLELR(ppc,cr,lk);ppce->write32(ppc);}
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#define EMIT_ANDIS(ppce,rd,ra,immed) \
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{PowerPC_instr ppc;GEN_ANDIS(ppc,rd,ra,immed);ppce->write32(ppc);}
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#define EMIT_ORIS(ppce,rd,rs,immed) \
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{PowerPC_instr ppc;GEN_ORIS(ppc,rd,rs,immed);ppce->write32(ppc);}
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#define EMIT_CROR(ppce,cd,ca,cb) \
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{PowerPC_instr ppc;GEN_CROR(ppc,cd,ca,cb);ppce->write32(ppc);}
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#define EMIT_CRNOR(ppce,cd,ca,cb) \
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{PowerPC_instr ppc;GEN_CRNOR(ppc,cd,ca,cb);ppce->write32(ppc);}
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#define EMIT_MFCR(ppce,rt) \
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{PowerPC_instr ppc;GEN_MFCR(ppc,rt);ppce->write32(ppc);}
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#define EMIT_MCRXR(ppce,bf) \
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{PowerPC_instr ppc;GEN_MCRXR(ppc,bf);ppce->write32(ppc);}
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#define EMIT_LVX(ppce,vd,ra,rb) \
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{PowerPC_instr ppc=0x7C0000CE;PPC_SET_RD(ppc,vd);PPC_SET_RA(ppc,ra);PPC_SET_RB(ppc,rb);ppce->write32(ppc);}
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#define EMIT_STVX(ppce,vs,ra,rb) \
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{PowerPC_instr ppc=0x7C0001CE;PPC_SET_RD(ppc,vs);PPC_SET_RA(ppc,ra);PPC_SET_RB(ppc,rb);ppce->write32(ppc);}
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#define EMIT_VOR(ppce,vd,va,vb) \
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{PowerPC_instr ppc=0x10000484;PPC_SET_RD(ppc,vd);PPC_SET_RA(ppc,va);PPC_SET_RB(ppc,vb);ppce->write32(ppc);}
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// debug
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#define EMIT_LINE(ppce) ppce->emitDebugValue(__LINE__); |