mirror of
https://github.com/gligli/nulldc-360.git
synced 2025-04-02 11:11:56 -04:00
103 lines
4.4 KiB
C++
103 lines
4.4 KiB
C++
//ubc is disabled on dreamcast and can't be used ... but kos-debug uses it !...
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#include "types.h"
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#include "dc/mem/sh4_internal_reg.h"
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#include "ubc.h"
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//UBC BARA 0xFF200000 0x1F200000 32 Undefined Held Held Held Iclk
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u32 UBC_BARA;
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//UBC BAMRA 0xFF200004 0x1F200004 8 Undefined Held Held Held Iclk
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u8 UBC_BAMRA;
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//UBC BBRA 0xFF200008 0x1F200008 16 0x0000 Held Held Held Iclk
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u16 UBC_BBRA;
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//UBC BARB 0xFF20000C 0x1F20000C 32 Undefined Held Held Held Iclk
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u32 UBC_BARB;
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//UBC BAMRB 0xFF200010 0x1F200010 8 Undefined Held Held Held Iclk
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u8 UBC_BAMRB;
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//UBC BBRB 0xFF200014 0x1F200014 16 0x0000 Held Held Held Iclk
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u16 UBC_BBRB;
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//UBC BDRB 0xFF200018 0x1F200018 32 Undefined Held Held Held Iclk
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u32 UBC_BDRB;
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//UBC BDMRB 0xFF20001C 0x1F20001C 32 Undefined Held Held Held Iclk
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u32 UBC_BDMRB;
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//UBC BRCR 0xFF200020 0x1F200020 16 0x0000 Held Held Held Iclk
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u16 UBC_BRCR;
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//Init term res
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void ubc_Init()
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{
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//UBC BARA 0xFF200000 0x1F200000 32 Undefined Held Held Held Iclk
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UBC[(u32)(UBC_BARA_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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UBC[(u32)(UBC_BARA_addr&0xFF)>>2].readFunction=0;
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UBC[(u32)(UBC_BARA_addr&0xFF)>>2].writeFunction=0;
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UBC[(u32)(UBC_BARA_addr&0xFF)>>2].data32=&UBC_BARA;
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//UBC BAMRA 0xFF200004 0x1F200004 8 Undefined Held Held Held Iclk
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UBC[(u32)(UBC_BAMRA_addr&0xFF)>>2].flags=REG_8BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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UBC[(u32)(UBC_BAMRA_addr&0xFF)>>2].readFunction=0;
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UBC[(u32)(UBC_BAMRA_addr&0xFF)>>2].writeFunction=0;
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UBC[(u32)(UBC_BAMRA_addr&0xFF)>>2].data8=&UBC_BAMRA;
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//UBC BBRA 0xFF200008 0x1F200008 16 0x0000 Held Held Held Iclk
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UBC[(u32)(UBC_BBRA_addr&0xFF)>>2].flags=REG_16BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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UBC[(u32)(UBC_BBRA_addr&0xFF)>>2].readFunction=0;
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UBC[(u32)(UBC_BBRA_addr&0xFF)>>2].writeFunction=0;
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UBC[(u32)(UBC_BBRA_addr&0xFF)>>2].data16=&UBC_BBRA;
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//UBC BARB 0xFF20000C 0x1F20000C 32 Undefined Held Held Held Iclk
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UBC[(u32)(UBC_BARB_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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UBC[(u32)(UBC_BARB_addr&0xFF)>>2].readFunction=0;
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UBC[(u32)(UBC_BARB_addr&0xFF)>>2].writeFunction=0;
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UBC[(u32)(UBC_BARB_addr&0xFF)>>2].data32=&UBC_BARB;
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//UBC BAMRB 0xFF200010 0x1F200010 8 Undefined Held Held Held Iclk
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UBC[(u32)(UBC_BAMRB_addr&0xFF)>>2].flags=REG_8BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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UBC[(u32)(UBC_BAMRB_addr&0xFF)>>2].readFunction=0;
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UBC[(u32)(UBC_BAMRB_addr&0xFF)>>2].writeFunction=0;
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UBC[(u32)(UBC_BAMRB_addr&0xFF)>>2].data8=&UBC_BAMRB;
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//UBC BBRB 0xFF200014 0x1F200014 16 0x0000 Held Held Held Iclk
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UBC[(u32)(UBC_BBRB_addr&0xFF)>>2].flags=REG_16BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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UBC[(u32)(UBC_BBRB_addr&0xFF)>>2].readFunction=0;
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UBC[(u32)(UBC_BBRB_addr&0xFF)>>2].writeFunction=0;
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UBC[(u32)(UBC_BBRB_addr&0xFF)>>2].data16=&UBC_BBRB;
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//UBC BDRB 0xFF200018 0x1F200018 32 Undefined Held Held Held Iclk
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UBC[(u32)(UBC_BDRB_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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UBC[(u32)(UBC_BDRB_addr&0xFF)>>2].readFunction=0;
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UBC[(u32)(UBC_BDRB_addr&0xFF)>>2].writeFunction=0;
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UBC[(u32)(UBC_BDRB_addr&0xFF)>>2].data32=&UBC_BDRB;
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//UBC BDMRB 0xFF20001C 0x1F20001C 32 Undefined Held Held Held Iclk
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UBC[(u32)(UBC_BDMRB_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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UBC[(u32)(UBC_BDMRB_addr&0xFF)>>2].readFunction=0;
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UBC[(u32)(UBC_BDMRB_addr&0xFF)>>2].writeFunction=0;
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UBC[(u32)(UBC_BDMRB_addr&0xFF)>>2].data32=&UBC_BDMRB;
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//UBC BRCR 0xFF200020 0x1F200020 16 0x0000 Held Held Held Iclk
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UBC[(u32)(UBC_BRCR_addr&0xFF)>>2].flags=REG_16BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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UBC[(u32)(UBC_BRCR_addr&0xFF)>>2].readFunction=0;
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UBC[(u32)(UBC_BRCR_addr&0xFF)>>2].writeFunction=0;
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UBC[(u32)(UBC_BRCR_addr&0xFF)>>2].data16=&UBC_BRCR;
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}
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void ubc_Reset(bool Manual)
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{
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/*
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BARA H'FF20 0000 H'1F20 0000 32 Undefined Held Held Held Iclk
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UBC BAMRA H'FF20 0004 H'1F20 0004 8 Undefined Held Held Held Iclk
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UBC BBRA H'FF20 0008 H'1F20 0008 16 H'0000 Held Held Held Iclk
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UBC BARB H'FF20 000C H'1F20 000C 32 Undefined Held Held Held Iclk
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UBC BAMRB H'FF20 0010 H'1F20 0010 8 Undefined Held Held Held Iclk
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UBC BBRB H'FF20 0014 H'1F20 0014 16 H'0000 Held Held Held Iclk
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UBC BDRB H'FF20 0018 H'1F20 0018 32 Undefined Held Held Held Iclk
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UBC BDMRB H'FF20 001C H'1F20 001C 32 Undefined Held Held Held Iclk
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UBC BRCR H'FF20 0020 H'1F20 0020 16 H'0000*2 Held Held Held Iclk
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*/
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UBC_BBRA = 0x0;
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UBC_BBRB = 0x0;
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UBC_BRCR = 0x0;
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}
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void ubc_Term()
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{
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}
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