mirror of
https://github.com/gligli/nulldc-360.git
synced 2025-04-02 11:11:56 -04:00
241 lines
7.7 KiB
C++
241 lines
7.7 KiB
C++
/*
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Lovely timers, its amazing how many times this module was bugged
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*/
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#include "types.h"
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#include "tmu.h"
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#include "intc.h"
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#include "dc/mem/sh4_internal_reg.h"
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#define tmu_underflow 0x0100
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#define tmu_UNIE 0x0020
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u32 tmu_prescaler[3];
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u32 tmu_prescaler_shift[3];
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u32 tmu_prescaler_mask[3];
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const u32 tmu_ch_bit[3]={1,2,4};
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u32 tmu_regs_CNT[3];
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u32 tmu_regs_COR[3];
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u16 tmu_regs_CR[3];
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u32 old_mode[3] = {0xFFFF,0xFFFF,0xFFFF};
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u8 TMU_TOCR,TMU_TSTR;
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const InterruptID tmu_intID[3]={sh4_TMU0_TUNI0,sh4_TMU1_TUNI1,sh4_TMU2_TUNI2};
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//Accurate counts for the chanel ch
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template<u32 ch>
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void UpdateTMU_chan(u32 clc)
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{
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//if chanel is on
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if ((TMU_TSTR & tmu_ch_bit[ch])!=0)
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{
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//count :D
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tmu_prescaler[ch]+=clc;
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u32 steps=tmu_prescaler[ch]>>tmu_prescaler_shift[ch];
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if (steps>tmu_regs_CNT[ch])
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{
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//remove the 'extra' steps to overflow
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steps-=tmu_regs_CNT[ch];
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//refill the counter
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tmu_regs_CNT[ch] = tmu_regs_COR[ch];
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//raise the interrupt
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tmu_regs_CR[ch] |= tmu_underflow;
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InterruptPend(tmu_intID[ch],1);
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//remove the full underflows (possible because we only check every 448 cycles)
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//this can be done with a div, but its very very very rare so this is probably faster
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//THIS can probably be replaced with a verify check on counter setup (havn't seen any game do this)
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while(steps>tmu_regs_COR[ch])
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steps-=tmu_regs_COR[ch];
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//steps now has the partial steps needed for update, guaranteeded it won't cause an overflow
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}
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//count down
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tmu_regs_CNT[ch]-=steps;
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//remove the full steps from the prescaler counter
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tmu_prescaler[ch]&=tmu_prescaler_mask[ch];
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}
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}
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void UpdateTMU(u32 Cycles)
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{
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UpdateTMU_chan<0>(Cycles);
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UpdateTMU_chan<1>(Cycles);
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UpdateTMU_chan<2>(Cycles);
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}
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//Update internal counter registers
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void UpdateTMUCounts(u32 reg)
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{
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InterruptPend(tmu_intID[reg],tmu_regs_CR[reg] & tmu_underflow);
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InterruptMask(tmu_intID[reg],tmu_regs_CR[reg] & tmu_UNIE);
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if (old_mode[reg]==(u32)(tmu_regs_CR[reg] & 0x7))
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return;
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else
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old_mode[reg]=(tmu_regs_CR[reg] & 0x7);
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switch(tmu_regs_CR[reg] & 0x7)
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{
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case 0: //4
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tmu_prescaler_shift[reg]=2;
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break;
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case 1: //16
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tmu_prescaler_shift[reg]=4;
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break;
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case 2: //64
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tmu_prescaler_shift[reg]=6;
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break;
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case 3: //256
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tmu_prescaler_shift[reg]=8;
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break;
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case 4: //1024
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tmu_prescaler_shift[reg]=10;
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break;
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case 5: //reserved
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dlog("TMU ch%d , TCR%d mode is reserved (5)",reg,reg);
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break;
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case 6: //RTC
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dlog("TMU ch%d , TCR%d mode is RTC (6) , can't be used on dreamcast",reg,reg);
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break;
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case 7: //external
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dlog("TMU ch%d , TCR%d mode is External (7) , can't be used on dreamcast",reg,reg);
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break;
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}
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tmu_prescaler_shift[reg]+=2;// because we count in Io cycles (cpu core cycles) and the tmu is provided w/
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// the Po (perhipal clock)
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tmu_prescaler_mask[reg]=(1<<tmu_prescaler_shift[reg])-1;
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tmu_prescaler[reg]=0;
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}
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//Write to status registers
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void TMU_TCR0_write(u32 data)
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{
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tmu_regs_CR[0]=(u16)data;
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UpdateTMUCounts(0);
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}
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void TMU_TCR1_write(u32 data)
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{
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tmu_regs_CR[1]=(u16)data;
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UpdateTMUCounts(1);
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}
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void TMU_TCR2_write(u32 data)
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{
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tmu_regs_CR[2]=(u16)data;
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UpdateTMUCounts(2);
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}
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//Chan 2 not used functions
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u32 TMU_TCPR2_read()
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{
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EMUERROR("Read from TMU_TCPR2 , this regiser should be not used on dreamcast according to docs");
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return 0;
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}
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void TMU_TCPR2_write(u32 data)
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{
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EMUERROR2("Write to TMU_TCPR2 , this regiser should be not used on dreamcast according to docs , data=%d",data);
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}
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//Init/Res/Term
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void tmu_Init()
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{
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//TMU TOCR 0xFFD80000 0x1FD80000 8 0x00 0x00 Held Held Pclk
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TMU[(u32)(TMU_TOCR_addr&0xFF)>>2].flags=REG_8BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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TMU[(u32)(TMU_TOCR_addr&0xFF)>>2].readFunction=0;
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TMU[(u32)(TMU_TOCR_addr&0xFF)>>2].writeFunction=0;
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TMU[(u32)(TMU_TOCR_addr&0xFF)>>2].data8=(u8*)&TMU_TOCR;
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//TMU TSTR 0xFFD80004 0x1FD80004 8 0x00 0x00 Held 0x00 Pclk
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TMU[(u32)(TMU_TSTR_addr&0xFF)>>2].flags=REG_8BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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TMU[(u32)(TMU_TSTR_addr&0xFF)>>2].readFunction=0;
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TMU[(u32)(TMU_TSTR_addr&0xFF)>>2].writeFunction=0;
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TMU[(u32)(TMU_TSTR_addr&0xFF)>>2].data8=(u8*)&TMU_TSTR;
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//TMU TCOR0 0xFFD80008 0x1FD80008 32 0xFFFFFFFF 0xFFFFFFFF Held Held Pclk
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TMU[(u32)(TMU_TCOR0_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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TMU[(u32)(TMU_TCOR0_addr&0xFF)>>2].readFunction=0;
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TMU[(u32)(TMU_TCOR0_addr&0xFF)>>2].writeFunction=0;
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TMU[(u32)(TMU_TCOR0_addr&0xFF)>>2].data32=(u32*)&tmu_regs_COR[0];
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//TMU TCNT0 0xFFD8000C 0x1FD8000C 32 0xFFFFFFFF 0xFFFFFFFF Held Held Pclk
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TMU[(u32)(TMU_TCNT0_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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TMU[(u32)(TMU_TCNT0_addr&0xFF)>>2].readFunction=0;
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TMU[(u32)(TMU_TCNT0_addr&0xFF)>>2].writeFunction=0;
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TMU[(u32)(TMU_TCNT0_addr&0xFF)>>2].data32=(u32*)&tmu_regs_CNT[0];
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//TMU TCR0 0xFFD80010 0x1FD80010 16 0x0000 0x0000 Held Held Pclk
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TMU[(u32)(TMU_TCR0_addr&0xFF)>>2].flags=REG_16BIT_READWRITE | REG_READ_DATA;
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TMU[(u32)(TMU_TCR0_addr&0xFF)>>2].readFunction=0;
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TMU[(u32)(TMU_TCR0_addr&0xFF)>>2].writeFunction=TMU_TCR0_write;
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TMU[(u32)(TMU_TCR0_addr&0xFF)>>2].data16=(u16*)&tmu_regs_CR[0];
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//TMU TCOR1 0xFFD80014 0x1FD80014 32 0xFFFFFFFF 0xFFFFFFFF Held Held Pclk
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TMU[(u32)(TMU_TCOR1_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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TMU[(u32)(TMU_TCOR1_addr&0xFF)>>2].readFunction=0;
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TMU[(u32)(TMU_TCOR1_addr&0xFF)>>2].writeFunction=0;
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TMU[(u32)(TMU_TCOR1_addr&0xFF)>>2].data32=(u32*)&tmu_regs_COR[1];
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//TMU TCNT1 0xFFD80018 0x1FD80018 32 0xFFFFFFFF 0xFFFFFFFF Held Held Pclk
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TMU[(u32)(TMU_TCNT1_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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TMU[(u32)(TMU_TCNT1_addr&0xFF)>>2].readFunction=0;
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TMU[(u32)(TMU_TCNT1_addr&0xFF)>>2].writeFunction=0;
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TMU[(u32)(TMU_TCNT1_addr&0xFF)>>2].data32=(u32*)&tmu_regs_CNT[1];
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//TMU TCR1 0xFFD8001C 0x1FD8001C 16 0x0000 0x0000 Held Held Pclk
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TMU[(u32)(TMU_TCR1_addr&0xFF)>>2].flags=REG_16BIT_READWRITE | REG_READ_DATA;
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TMU[(u32)(TMU_TCR1_addr&0xFF)>>2].readFunction=0;
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TMU[(u32)(TMU_TCR1_addr&0xFF)>>2].writeFunction=TMU_TCR1_write;
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TMU[(u32)(TMU_TCR1_addr&0xFF)>>2].data16=(u16*)&tmu_regs_CR[1];
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//TMU TCOR2 0xFFD80020 0x1FD80020 32 0xFFFFFFFF 0xFFFFFFFF Held Held Pclk
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TMU[(u32)(TMU_TCOR2_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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TMU[(u32)(TMU_TCOR2_addr&0xFF)>>2].readFunction=0;
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TMU[(u32)(TMU_TCOR2_addr&0xFF)>>2].writeFunction=0;
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TMU[(u32)(TMU_TCOR2_addr&0xFF)>>2].data32=(u32*)&tmu_regs_COR[2];
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//TMU TCNT2 0xFFD80024 0x1FD80024 32 0xFFFFFFFF 0xFFFFFFFF Held Held Pclk
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TMU[(u32)(TMU_TCNT2_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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TMU[(u32)(TMU_TCNT2_addr&0xFF)>>2].readFunction=0;
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TMU[(u32)(TMU_TCNT2_addr&0xFF)>>2].writeFunction=0;
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TMU[(u32)(TMU_TCNT2_addr&0xFF)>>2].data32=(u32*)&tmu_regs_CNT[2];
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//TMU TCR2 0xFFD80028 0x1FD80028 16 0x0000 0x0000 Held Held Pclk
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TMU[(u32)(TMU_TCR2_addr&0xFF)>>2].flags=REG_16BIT_READWRITE | REG_READ_DATA;
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TMU[(u32)(TMU_TCR2_addr&0xFF)>>2].readFunction=0;
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TMU[(u32)(TMU_TCR2_addr&0xFF)>>2].writeFunction=TMU_TCR2_write;
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TMU[(u32)(TMU_TCR2_addr&0xFF)>>2].data16=(u16*)&tmu_regs_CR[2];
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//TMU TCPR2 0xFFD8002C 0x1FD8002C 32 Held Held Held Held Pclk
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TMU[(u32)(TMU_TCPR2_addr&0xFF)>>2].flags=REG_32BIT_READWRITE;
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TMU[(u32)(TMU_TCPR2_addr&0xFF)>>2].readFunction=TMU_TCPR2_read;
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TMU[(u32)(TMU_TCPR2_addr&0xFF)>>2].writeFunction=TMU_TCPR2_write;
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TMU[(u32)(TMU_TCPR2_addr&0xFF)>>2].data32=0;
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}
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void tmu_Reset(bool Manual)
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{
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TMU_TOCR=TMU_TSTR=0;
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tmu_regs_COR[0] = tmu_regs_COR[1] = tmu_regs_COR[2] = 0xffffffff;
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tmu_regs_CNT[0] = tmu_regs_CNT[1] = tmu_regs_CNT[2] = 0xffffffff;
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tmu_regs_CR[0] = tmu_regs_CR[1] = tmu_regs_CR[2] = 0;
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UpdateTMUCounts(0);
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UpdateTMUCounts(1);
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UpdateTMUCounts(2);
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}
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void tmu_Term()
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{
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}
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