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https://github.com/gligli/nulldc-360.git
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55 lines
1.5 KiB
C
55 lines
1.5 KiB
C
#pragma once
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#include "types.h"
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#include "sh4_if.h"
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#include "intc.h"
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#undef sh4op
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#define sh4op(str) void __fastcall str (u32 op)
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#define rsh4op(str) void __fastcall str (u32 op)
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typedef void (__fastcall OpCallFP) (u32 op);
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enum OpcodeType
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{
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//basic
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Normal=0, //heh , nothing special :P
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ReadsPC=1, //pc must be set upon calling it
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WritesPC=2, //it will write pc (branch)
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Delayslot=4, //has a delayslot opcode , valid olny when WritesPC is set
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WritesSR=8, //Writes to SR , and UpdateSR needs to be called
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WritesFPSCR=16, //Writes to FPSCR , and UpdateSR needs to be called
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Invalid=128, //invalid
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//heh not basic :P
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ReadWritePC=ReadsPC|WritesPC, //Read and writes pc :P
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//branches :
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//not delay slot
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Branch_dir=ReadWritePC, //direct (eg , pc=r[xx]) -- this one is ReadWritePC b/c the delayslot may use pc ;)
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Branch_rel=ReadWritePC, //relative (rg pc+=10);
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//delay slot
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Branch_dir_d=Delayslot|Branch_dir, //direct (eg , pc=r[xx])
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Branch_rel_d=Delayslot|Branch_rel, //relative (rg pc+=10);
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};
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//interface
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void Sh4_int_Run();
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void Sh4_int_Stop();
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void Sh4_int_Step();
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void Sh4_int_Skip();
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void Sh4_int_Reset(bool Manual);
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void Sh4_int_Init();
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void Sh4_int_Term();
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bool Sh4_int_IsCpuRunning();
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void __fastcall sh4_int_RaiseExeption(u32 ExeptionCode,u32 VectorAddr);
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u32 Sh4_int_GetRegister(Sh4RegType reg);
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void Sh4_int_SetRegister(Sh4RegType reg,u32 regdata);
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//Other things (mainly used by the cpu core
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bool ExecuteDelayslot();
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bool ExecuteDelayslot_RTE();
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extern "C" {
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int __fastcall UpdateSystem();
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}
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