mirror of
https://github.com/gligli/nulldc-360.git
synced 2025-04-02 11:11:56 -04:00
178 lines
No EOL
6 KiB
C++
178 lines
No EOL
6 KiB
C++
//gah , ccn emulation
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//CCN: Cache and TLB controller
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#include "types.h"
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#include "dc/mem/sh4_internal_reg.h"
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#include "dc/mem/sh4_internal_reg.h"
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#include "dc/mem/mmu.h"
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#include "ccn.h"
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#include "dc/sh4/rec_v1/blockmanager.h"
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//Types
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CCN_PTEH_type CCN_PTEH;
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CCN_PTEL_type CCN_PTEL;
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u32 CCN_TTB;
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u32 CCN_TEA;
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CCN_MMUCR_type CCN_MMUCR;
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u8 CCN_BASRA;
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u8 CCN_BASRB;
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CCN_CCR_type CCN_CCR;
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u32 CCN_TRA;
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u32 CCN_EXPEVT;
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u32 CCN_INTEVT;
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CCN_PTEA_type CCN_PTEA;
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CCN_QACR_type CCN_QACR[2];
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__attribute__((aligned(65536))) u32 CCN_QACR_TR[2];
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template<int idx>
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void CCN_QACR_write(u32 value)
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{
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CCN_QACR[idx].reg_data=value;
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CCN_QACR_TR[idx]=(CCN_QACR[idx].Area<<26)-0xE0000000;
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}
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void CCN_MMUCR_write(u32 value)
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{
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CCN_MMUCR_type temp;
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temp.reg_data=value;
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#ifdef NO_MMU
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if ((temp.AT!=CCN_MMUCR.AT) && (temp.AT==1))
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{
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dlog("<*******>MMU Enabled , OLNY SQ remaps work<*******>\n");
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//getchar();
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}
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#endif
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if (temp.TI)
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{
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dlog("TI , invalidating *TLB\n");
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temp.TI=0;
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for (u32 i=0;i<4;i++)
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{
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ITLB[i].Data.V=0;
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}
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for (u32 i=0;i<64;i++)
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{
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UTLB[i].Data.V=0;
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}
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}
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CCN_MMUCR=temp;
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}
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u32 ici_count=0;
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void CCN_CCR_write(u32 value)
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{
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CCN_CCR_type temp;
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temp.reg_data=value;
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if (temp.ICI==1)
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{
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//invalidate i-cache
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temp.ICI=0;
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ici_count++;
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dlog("i-cache invalidation requested! (%d total)\n",ici_count);
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SuspendAllBlocks();
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}
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CCN_CCR=temp;
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}
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//Init/Res/Term
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void ccn_Init()
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{
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//CCN PTEH 0xFF000000 0x1F000000 32 Undefined Undefined Held Held Iclk
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CCN[(u32)(CCN_PTEH_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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CCN[(u32)(CCN_PTEH_addr&0xFF)>>2].readFunction=0;
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CCN[(u32)(CCN_PTEH_addr&0xFF)>>2].writeFunction=0;
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CCN[(u32)(CCN_PTEH_addr&0xFF)>>2].data32=&CCN_PTEH.reg_data;
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//CCN PTEL 0xFF000004 0x1F000004 32 Undefined Undefined Held Held Iclk
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CCN[(u32)(CCN_PTEL_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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CCN[(u32)(CCN_PTEL_addr&0xFF)>>2].readFunction=0;
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CCN[(u32)(CCN_PTEL_addr&0xFF)>>2].writeFunction=0;
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CCN[(u32)(CCN_PTEL_addr&0xFF)>>2].data32=&CCN_PTEL.reg_data;
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//CCN TTB 0xFF000008 0x1F000008 32 Undefined Undefined Held Held Iclk
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CCN[(u32)(CCN_TTB_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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CCN[(u32)(CCN_TTB_addr&0xFF)>>2].readFunction=0;
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CCN[(u32)(CCN_TTB_addr&0xFF)>>2].writeFunction=0;
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CCN[(u32)(CCN_TTB_addr&0xFF)>>2].data32=&CCN_TTB;
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//CCN TEA 0xFF00000C 0x1F00000C 32 Undefined Held Held Held Iclk
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CCN[(u32)(CCN_TEA_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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CCN[(u32)(CCN_TEA_addr&0xFF)>>2].readFunction=0;
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CCN[(u32)(CCN_TEA_addr&0xFF)>>2].writeFunction=0;
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CCN[(u32)(CCN_TEA_addr&0xFF)>>2].data32=&CCN_TEA;
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//CCN MMUCR 0xFF000010 0x1F000010 32 0x00000000 0x00000000 Held Held Iclk
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CCN[(u32)(CCN_MMUCR_addr&0xFF)>>2].flags= REG_32BIT_READWRITE | REG_READ_DATA ;
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CCN[(u32)(CCN_MMUCR_addr&0xFF)>>2].readFunction=0;
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CCN[(u32)(CCN_MMUCR_addr&0xFF)>>2].writeFunction=CCN_MMUCR_write;
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CCN[(u32)(CCN_MMUCR_addr&0xFF)>>2].data32=&CCN_MMUCR.reg_data;
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//CCN BASRA 0xFF000014 0x1F000014 8 Undefined Held Held Held Iclk
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CCN[(u32)(CCN_BASRA_addr&0xFF)>>2].flags=REG_8BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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CCN[(u32)(CCN_BASRA_addr&0xFF)>>2].readFunction=0;
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CCN[(u32)(CCN_BASRA_addr&0xFF)>>2].writeFunction=0;
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CCN[(u32)(CCN_BASRA_addr&0xFF)>>2].data8=&CCN_BASRA;
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//CCN BASRB 0xFF000018 0x1F000018 8 Undefined Held Held Held Iclk
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CCN[(u32)(CCN_BASRB_addr&0xFF)>>2].flags=REG_8BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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CCN[(u32)(CCN_BASRB_addr&0xFF)>>2].readFunction=0;
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CCN[(u32)(CCN_BASRB_addr&0xFF)>>2].writeFunction=0;
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CCN[(u32)(CCN_BASRB_addr&0xFF)>>2].data8=&CCN_BASRB;
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//CCN CCR 0xFF00001C 0x1F00001C 32 0x00000000 0x00000000 Held Held Iclk
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CCN[(u32)(CCN_CCR_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA;
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CCN[(u32)(CCN_CCR_addr&0xFF)>>2].readFunction=0;
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CCN[(u32)(CCN_CCR_addr&0xFF)>>2].writeFunction=CCN_CCR_write;
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CCN[(u32)(CCN_CCR_addr&0xFF)>>2].data32=&CCN_CCR.reg_data;
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//CCN TRA 0xFF000020 0x1F000020 32 Undefined Undefined Held Held Iclk
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CCN[(u32)(CCN_TRA_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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CCN[(u32)(CCN_TRA_addr&0xFF)>>2].readFunction=0;
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CCN[(u32)(CCN_TRA_addr&0xFF)>>2].writeFunction=0;
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CCN[(u32)(CCN_TRA_addr&0xFF)>>2].data32=&CCN_TRA;
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//CCN EXPEVT 0xFF000024 0x1F000024 32 0x00000000 0x00000020 Held Held Iclk
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CCN[(u32)(CCN_EXPEVT_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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CCN[(u32)(CCN_EXPEVT_addr&0xFF)>>2].readFunction=0;
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CCN[(u32)(CCN_EXPEVT_addr&0xFF)>>2].writeFunction=0;
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CCN[(u32)(CCN_EXPEVT_addr&0xFF)>>2].data32=&CCN_EXPEVT;
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//CCN INTEVT 0xFF000028 0x1F000028 32 Undefined Undefined Held Held Iclk
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CCN[(u32)(CCN_INTEVT_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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CCN[(u32)(CCN_INTEVT_addr&0xFF)>>2].readFunction=0;
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CCN[(u32)(CCN_INTEVT_addr&0xFF)>>2].writeFunction=0;
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CCN[(u32)(CCN_INTEVT_addr&0xFF)>>2].data32=&CCN_INTEVT;
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//CCN PTEA 0xFF000034 0x1F000034 32 Undefined Undefined Held Held Iclk
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CCN[(u32)(CCN_PTEA_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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CCN[(u32)(CCN_PTEA_addr&0xFF)>>2].readFunction=0;
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CCN[(u32)(CCN_PTEA_addr&0xFF)>>2].writeFunction=0;
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CCN[(u32)(CCN_PTEA_addr&0xFF)>>2].data32=&CCN_PTEA.reg_data;
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//CCN QACR0 0xFF000038 0x1F000038 32 Undefined Undefined Held Held Iclk
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CCN[(u32)(CCN_QACR0_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA;
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CCN[(u32)(CCN_QACR0_addr&0xFF)>>2].readFunction=0;
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CCN[(u32)(CCN_QACR0_addr&0xFF)>>2].writeFunction=CCN_QACR_write<0>;
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CCN[(u32)(CCN_QACR0_addr&0xFF)>>2].data32=&CCN_QACR[0].reg_data;
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//CCN QACR1 0xFF00003C 0x1F00003C 32 Undefined Undefined Held Held Iclk
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CCN[(u32)(CCN_QACR1_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA;
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CCN[(u32)(CCN_QACR1_addr&0xFF)>>2].readFunction=0;
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CCN[(u32)(CCN_QACR1_addr&0xFF)>>2].writeFunction=CCN_QACR_write<1>;
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CCN[(u32)(CCN_QACR1_addr&0xFF)>>2].data32=&CCN_QACR[1].reg_data;
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}
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void ccn_Reset(bool Manual)
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{
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CCN_TRA = 0x0;
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CCN_EXPEVT = 0x0;
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CCN_MMUCR.reg_data = 0x0;
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CCN_CCR.reg_data = 0x0;
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}
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void ccn_Term()
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{
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} |