mirror of
https://github.com/gligli/nulldc-360.git
synced 2025-04-02 11:11:56 -04:00
267 lines
No EOL
8.8 KiB
C++
267 lines
No EOL
8.8 KiB
C++
//Bus state controller registers
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#include "types.h"
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#include "dc/mem/sh4_internal_reg.h"
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#include "bsc.h"
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//32 bits
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//All bits exept A0MPX,MASTER,ENDIAN are editable and reseted to 0
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BCR1_type BSC_BCR1;
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//16 bit
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//A0SZ0,A0SZ1 are read olny , ohters are are editable and reseted to 0
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BCR2_type BSC_BCR2;
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//32 bits
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WCR1_type BSC_WCR1;
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//32 bits
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WCR2_type BSC_WCR2;
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//32 bits
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WCR3_type BSC_WCR3;
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//32 bits
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MCR_type BSC_MCR;
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//16 bits
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PCR_type BSC_PCR;
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//16 bits -> misstype on manual ? RTSCR vs RTCSR...
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RTCSR_type BSC_RTCSR;
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//16 bits
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RTCNT_type BSC_RTCNT;
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//16 bits
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RTCOR_type BSC_RTCOR;
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//16 bits
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RFCR_type BSC_RFCR;
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//32 bits
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PCTRA_type BSC_PCTRA;
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//16 bits
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PDTRA_type BSC_PDTRA;
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//32 bits
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PCTRB_type BSC_PCTRB;
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//16 bits
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PDTRB_type BSC_PDTRB;
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//16 bits
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GPIOIC_type BSC_GPIOIC;
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#include "naomi/naomi.h"
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void write_BSC_PCTRA(u32 data)
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{
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BSC_PCTRA.full=(u16)data;
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#if defined(BUILD_NAOMI ) || defined(BUILD_ATOMISWAVE)
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NaomiBoardIDWriteControl((u16)data);
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#else
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//dlog("C:BSC_PCTRA = %08X\n",data);
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#endif
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}
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//u32 port_out_data;
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void write_BSC_PDTRA(u32 data)
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{
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BSC_PDTRA.full=(u16)data;
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//dlog("D:BSC_PDTRA = %08X\n",data);
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#if defined(BUILD_NAOMI ) || defined(BUILD_ATOMISWAVE)
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NaomiBoardIDWrite((u16)data);
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#endif
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}
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u32 read_BSC_PDTRA()
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{
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#if defined(BUILD_NAOMI ) || defined(BUILD_ATOMISWAVE)
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return NaomiBoardIDRead();
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#else
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/* as seen on chankast */
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u32 tpctra = BSC_PCTRA.full;
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u32 tpdtra = BSC_PDTRA.full;
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u32 tfinal=0;
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// magic values
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if ((tpctra&0xf) == 0x8)
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tfinal = 3;
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else if ((tpctra&0xf) == 0xB)
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tfinal = 3;
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else
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tfinal = 0;
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if ((tpctra&0xf) == 0xB && (tpdtra&0xf) == 2)
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tfinal = 0;
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else if ((tpctra&0xf) == 0xC && (tpdtra&0xf) == 2)
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tfinal = 3;
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tfinal |= settings.dreamcast.cable <<8;
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return tfinal;
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#endif
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}
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u32 read_BSC_PDTRB()
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{
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die("read_BSC_PDTRB");
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return 0;
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}
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//Init term res
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void bsc_Init()
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{
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//BSC BCR1 0xFF800000 0x1F800000 32 0x00000000 Held Held Held Bclk
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BSC[(u32)(BSC_BCR1_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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BSC[(u32)(BSC_BCR1_addr&0xFF)>>2].readFunction=0;
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BSC[(u32)(BSC_BCR1_addr&0xFF)>>2].writeFunction=0;
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BSC[(u32)(BSC_BCR1_addr&0xFF)>>2].data32=&BSC_BCR1.full;
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//BSC BCR2 0xFF800004 0x1F800004 16 0x3FFC Held Held Held Bclk
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BSC[(u32)(BSC_BCR2_addr&0xFF)>>2].flags=REG_16BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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BSC[(u32)(BSC_BCR2_addr&0xFF)>>2].readFunction=0;
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BSC[(u32)(BSC_BCR2_addr&0xFF)>>2].writeFunction=0;
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BSC[(u32)(BSC_BCR2_addr&0xFF)>>2].data16=&BSC_BCR2.full;
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//BSC WCR1 0xFF800008 0x1F800008 32 0x77777777 Held Held Held Bclk
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BSC[(u32)(BSC_WCR1_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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BSC[(u32)(BSC_WCR1_addr&0xFF)>>2].readFunction=0;
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BSC[(u32)(BSC_WCR1_addr&0xFF)>>2].writeFunction=0;
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BSC[(u32)(BSC_WCR1_addr&0xFF)>>2].data32=&BSC_WCR1.full;
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//BSC WCR2 0xFF80000C 0x1F80000C 32 0xFFFEEFFF Held Held Held Bclk
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BSC[(u32)(BSC_WCR2_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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BSC[(u32)(BSC_WCR2_addr&0xFF)>>2].readFunction=0;
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BSC[(u32)(BSC_WCR2_addr&0xFF)>>2].writeFunction=0;
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BSC[(u32)(BSC_WCR2_addr&0xFF)>>2].data32=&BSC_WCR2.full;
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//BSC WCR3 0xFF800010 0x1F800010 32 0x07777777 Held Held Held Bclk
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BSC[(u32)(BSC_WCR3_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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BSC[(u32)(BSC_WCR3_addr&0xFF)>>2].readFunction=0;
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BSC[(u32)(BSC_WCR3_addr&0xFF)>>2].writeFunction=0;
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BSC[(u32)(BSC_WCR3_addr&0xFF)>>2].data32=&BSC_WCR3.full;
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//BSC MCR 0xFF800014 0x1F800014 32 0x00000000 Held Held Held Bclk
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BSC[(u32)(BSC_MCR_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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BSC[(u32)(BSC_MCR_addr&0xFF)>>2].readFunction=0;
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BSC[(u32)(BSC_MCR_addr&0xFF)>>2].writeFunction=0;
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BSC[(u32)(BSC_MCR_addr&0xFF)>>2].data32=&BSC_MCR.full;
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//BSC PCR 0xFF800018 0x1F800018 16 0x0000 Held Held Held Bclk
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BSC[(u32)(BSC_PCR_addr&0xFF)>>2].flags=REG_16BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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BSC[(u32)(BSC_PCR_addr&0xFF)>>2].readFunction=0;
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BSC[(u32)(BSC_PCR_addr&0xFF)>>2].writeFunction=0;
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BSC[(u32)(BSC_PCR_addr&0xFF)>>2].data16=&BSC_PCR.full;
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//BSC RTCSR 0xFF80001C 0x1F80001C 16 0x0000 Held Held Held Bclk
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BSC[(u32)(BSC_RTCSR_addr&0xFF)>>2].flags=REG_16BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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BSC[(u32)(BSC_RTCSR_addr&0xFF)>>2].readFunction=0;
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BSC[(u32)(BSC_RTCSR_addr&0xFF)>>2].writeFunction=0;
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BSC[(u32)(BSC_RTCSR_addr&0xFF)>>2].data16=&BSC_RTCSR.full;
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//BSC RTCNT 0xFF800020 0x1F800020 16 0x0000 Held Held Held Bclk
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BSC[(u32)(BSC_RTCNT_addr&0xFF)>>2].flags=REG_16BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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BSC[(u32)(BSC_RTCNT_addr&0xFF)>>2].readFunction=0;
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BSC[(u32)(BSC_RTCNT_addr&0xFF)>>2].writeFunction=0;
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BSC[(u32)(BSC_RTCNT_addr&0xFF)>>2].data16=&BSC_RTCNT.full;
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//BSC RTCOR 0xFF800024 0x1F800024 16 0x0000 Held Held Held Bclk
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BSC[(u32)(BSC_RTCOR_addr&0xFF)>>2].flags=REG_16BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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BSC[(u32)(BSC_RTCOR_addr&0xFF)>>2].readFunction=0;
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BSC[(u32)(BSC_RTCOR_addr&0xFF)>>2].writeFunction=0;
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BSC[(u32)(BSC_RTCOR_addr&0xFF)>>2].data16=&BSC_RTCOR.full;
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//BSC RFCR 0xFF800028 0x1F800028 16 0x0000 Held Held Held Bclk
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BSC[(u32)(BSC_RFCR_addr&0xFF)>>2].flags=REG_16BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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BSC[(u32)(BSC_RFCR_addr&0xFF)>>2].readFunction=0;
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BSC[(u32)(BSC_RFCR_addr&0xFF)>>2].writeFunction=0;
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BSC[(u32)(BSC_RFCR_addr&0xFF)>>2].data16=&BSC_RFCR.full;
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//BSC PCTRA 0xFF80002C 0x1F80002C 32 0x00000000 Held Held Held Bclk
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BSC[(u32)(BSC_PCTRA_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA;
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BSC[(u32)(BSC_PCTRA_addr&0xFF)>>2].readFunction=0;
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BSC[(u32)(BSC_PCTRA_addr&0xFF)>>2].writeFunction=write_BSC_PCTRA;
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BSC[(u32)(BSC_PCTRA_addr&0xFF)>>2].data32=&BSC_PCTRA.full;
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//BSC PDTRA 0xFF800030 0x1F800030 16 Undefined Held Held Held Bclk
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BSC[(u32)(BSC_PDTRA_addr&0xFF)>>2].flags=REG_16BIT_READWRITE;
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BSC[(u32)(BSC_PDTRA_addr&0xFF)>>2].readFunction=read_BSC_PDTRA;
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BSC[(u32)(BSC_PDTRA_addr&0xFF)>>2].writeFunction=write_BSC_PDTRA;
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BSC[(u32)(BSC_PDTRA_addr&0xFF)>>2].data16=0;//&BSC_PDTRA.full;
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//BSC PCTRB 0xFF800040 0x1F800040 32 0x00000000 Held Held Held Bclk
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BSC[(u32)(BSC_PCTRB_addr&0xFF)>>2].flags=REG_32BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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BSC[(u32)(BSC_PCTRB_addr&0xFF)>>2].readFunction=0;
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BSC[(u32)(BSC_PCTRB_addr&0xFF)>>2].writeFunction=0;
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BSC[(u32)(BSC_PCTRB_addr&0xFF)>>2].data32=&BSC_PCTRB.full;
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//BSC PDTRB 0xFF800044 0x1F800044 16 Undefined Held Held Held Bclk
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BSC[(u32)(BSC_PDTRB_addr&0xFF)>>2].flags=REG_16BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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BSC[(u32)(BSC_PDTRB_addr&0xFF)>>2].readFunction=read_BSC_PDTRB;
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BSC[(u32)(BSC_PDTRB_addr&0xFF)>>2].writeFunction=0;
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BSC[(u32)(BSC_PDTRB_addr&0xFF)>>2].data16=&BSC_PDTRB.full;
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//BSC GPIOIC 0xFF800048 0x1F800048 16 0x00000000 Held Held Held Bclk
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BSC[(u32)(BSC_GPIOIC_addr&0xFF)>>2].flags=REG_16BIT_READWRITE | REG_READ_DATA | REG_WRITE_DATA;
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BSC[(u32)(BSC_GPIOIC_addr&0xFF)>>2].readFunction=0;
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BSC[(u32)(BSC_GPIOIC_addr&0xFF)>>2].writeFunction=0;
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BSC[(u32)(BSC_GPIOIC_addr&0xFF)>>2].data16=&BSC_GPIOIC.full;
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#if defined(BUILD_NAOMI ) || defined(BUILD_ATOMISWAVE)
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BSC_RFCR.full = 17;
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BSC[(u32)(BSC_RFCR_addr&0xFF)>>2].flags=REG_16BIT_READWRITE | REG_READ_DATA ;//| REG_WRITE_DATA;
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#endif
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}
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void bsc_Reset(bool Manual)
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{
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#if defined(BUILD_NAOMI ) || defined(BUILD_ATOMISWAVE)
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BSC_RFCR.full = 17;
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#endif
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/*
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BSC BCR1 H'FF80 0000 H'1F80 0000 32 H'0000 0000*2 Held Held Held Bclk
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BSC BCR2 H'FF80 0004 H'1F80 0004 16 H'3FFC*2 Held Held Held Bclk
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BSC WCR1 H'FF80 0008 H'1F80 0008 32 H'7777 7777 Held Held Held Bclk
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BSC WCR2 H'FF80 000C H'1F80 000C 32 H'FFFE EFFF Held Held Held Bclk
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BSC WCR3 H'FF80 0010 H'1F80 0010 32 H'0777 7777 Held Held Held Bclk
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BSC MCR H'FF80 0014 H'1F80 0014 32 H'0000 0000 Held Held Held Bclk
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BSC PCR H'FF80 0018 H'1F80 0018 16 H'0000 Held Held Held Bclk
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BSC RTCSR H'FF80 001C H'1F80 001C 16 H'0000 Held Held Held Bclk
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BSC RTCNT H'FF80 0020 H'1F80 0020 16 H'0000 Held Held Held Bclk
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BSC RTCOR H'FF80 0024 H'1F80 0024 16 H'0000 Held Held Held Bclk
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BSC RFCR H'FF80 0028 H'1F80 0028 16 H'0000 Held Held Held Bclk
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BSC PCTRA H'FF80 002C H'1F80 002C 32 H'0000 0000 Held Held Held Bclk
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BSC PDTRA H'FF80 0030 H'1F80 0030 16 Undefined Held Held Held Bclk
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BSC PCTRB H'FF80 0040 H'1F80 0040 32 H'0000 0000 Held Held Held Bclk
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BSC PDTRB H'FF80 0044 H'1F80 0044 16 Undefined Held Held Held Bclk
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BSC GPIOIC H'FF80 0048 H'1F80 0048 16 H'0000 0000 Held Held Held Bclk
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BSC SDMR2 H'FF90 xxxx H'1F90 xxxx 8 Write-only Bclk
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BSC SDMR3 H'FF94 xxxx H'1F94 xxxx 8 Bclk
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*/
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BSC_BCR1.full=0x0;
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BSC_BCR2.full=0x3FFC;
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BSC_WCR1.full=0x77777777;
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BSC_WCR2.full=0xFFFEEFFF;
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BSC_WCR3.full=0x07777777;
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BSC_MCR.full=0x0;
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BSC_PCR.full=0x0;
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BSC_RTCSR.full=0x0;
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BSC_RTCNT.full=0x0;
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BSC_RTCOR.full=0x0;
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BSC_PCTRA.full=0x0;
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//BSC_PDTRA.full; undef
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BSC_PCTRB.full=0x0;
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//BSC_PDTRB.full; undef
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BSC_GPIOIC.full=0x0;
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}
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void bsc_Term()
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{
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} |