/* sh4 base core most of it is (very) old could use many cleanups, lets hope someone does them */ #include "types.h" #include "sh4_cpu.h" #include "sh4_fpu.h" #include "dc/mem/memutil.h" #include "sh4_opcode_list.h" #include "rec_v1/ops.h" #include "plugins/plugin_manager.h" OpCallFP* OpPtr[0x10000]; RecOpCallFP* RecOpPtr[0x10000]; OpcodeType OpTyp[0x10000]; sh4_opcodelistentry* OpDesc[0x10000]; INLINE bool strcmp2(const char* &str1_o,const char * str2) { u32 sz=0; const char* str1=str1_o; while (*str2!='\0') { if (*str1!=*str2) { return false;// nope , theyre diferent } sz++; str1++;str2++;//next char } str1_o+=sz; return true; } //custom format string void OpDissCFS(char* text,const char* tx1,u32 pc,u16 opcode) { while (*tx1!='\0') { if (*tx1=='<') { tx1++; if (strcmp2(tx1,"REG_N>")) { text+=sprintf(text,"R%d",GetN(opcode)); } else if (strcmp2(tx1,"REG_M>") ) { text+=sprintf(text,"R%d",GetM(opcode)); } else if (strcmp2(tx1,"FREG_N>")) { text+=sprintf(text,"FR%d",GetN(opcode)); } else if (strcmp2(tx1,"FREG_M>")) { text+=sprintf(text,"FR%d",GetM(opcode)); } else if (strcmp2(tx1,"RM_BANK>")) { text+=sprintf(text,"R%d_BANK",GetM(opcode)&0x7); } else if (strcmp2(tx1,"DFREG_N>")) { text+=sprintf(text,"DR%d",GetN(opcode)>>1); } else if (strcmp2(tx1,"DFREG_M>")) { text+=sprintf(text,"DR%d",GetM(opcode)>>1); } else if (strcmp2(tx1,"XDFREG_N>")) { u32 t=GetN(opcode); if (t & 0x1) text+=sprintf(text,"XD%d",t>>1); else text+=sprintf(text,"DR%d",t>>1); } else if (strcmp2(tx1,"XDFREG_M>")) { u32 t=GetM(opcode); if (t & 0x1) text+=sprintf(text,"XD%d",t>>1); else text+=sprintf(text,"DR%d",t>>1); } else if (strcmp2(tx1,"disp4b>")) { text+=sprintf(text,"0x%X",GetImm4(opcode)*1); } else if (strcmp2(tx1,"disp4w>")) { text+=sprintf(text,"0x%X",GetImm4(opcode)*2); } else if (strcmp2(tx1,"disp4dw>")) { text+=sprintf(text,"0x%X",GetImm4(opcode)*4); } else if (strcmp2(tx1,"PCdisp8w>")) { text+=sprintf(text,"0x%X[PC]",(pc)+4+(GetImm8(opcode)<<1)); } else if (strcmp2(tx1,"PCdisp8d>")) { text+=sprintf(text,"0x%X[PC]",(pc&0xFFFFFFFC)+4+(GetImm8(opcode)<<2)); } else if (strcmp2(tx1,"disp8b>")) { text+=sprintf(text,"0x%X",GetImm8(opcode)*1); } else if (strcmp2(tx1,"disp8w>")) { text+=sprintf(text,"0x%X",GetImm8(opcode)*2); } else if (strcmp2(tx1,"disp8dw>")) { text+=sprintf(text,"0x%X",GetImm8(opcode)*4); } else if (strcmp2(tx1,"GBRdisp8b>")) { text+=sprintf(text,"0x%X",GetImm8(opcode)*1 + sh4_cpu->GetRegister(reg_gbr)); } else if (strcmp2(tx1,"GBRdisp8w>")) { text+=sprintf(text,"0x%X",GetImm8(opcode)*2 + sh4_cpu->GetRegister(reg_gbr)); } else if (strcmp2(tx1,"GBRdisp8dw>")) { text+=sprintf(text,"0x%X",GetImm8(opcode)*4 + sh4_cpu->GetRegister(reg_gbr)); } else if (strcmp2(tx1,"bdisp8>")) { text+=sprintf(text,"0x%X",((GetSImm8(opcode))*2 + 4 + pc)); } else if (strcmp2(tx1,"bdisp12>")) { text+=sprintf(text,"0x%X",(( ((s16)((GetImm12(opcode))<<4)) >>3) + pc + 4)); } else if (strcmp2(tx1,"imm8>")) { text+=sprintf(text,"0x%X",GetImm8(opcode)); } else if (strcmp2(tx1,"simm8>")) { text+=sprintf(text,"%d",GetSImm8(opcode)); } else if (strcmp2(tx1,"simm8hex>")) { text+=sprintf(text,"0x%X",GetSImm8(opcode)); } else { u32 ti=0; while (tx1[ti]!='\0') { if (tx1[ti]=='>') break; else ti++; } // char old=tx1[ti]; //tx1[ti]='\0'; dlog("Sh4Dissasm : Tag not known\"%s\"\n",tx1); //tx1[ti]=old; *text='<';text++; *text=*tx1; tx1++; text++; } } else { *text=*tx1; tx1++; text++; } } *text='\0'; tx1++; text++; } fpscr_type Get_fpscr() { fpscr_type t; t.full=sh4_cpu->GetRegister(reg_fpscr); return t; } //fadd , void d1111_nnnn_mmmm_0000(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().PR==0) { OpDissCFS(text,"fadd ,",pc,opcode); } else { OpDissCFS(text,"fadd ,",pc,opcode); } } //fsub , void d1111_nnnn_mmmm_0001(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().PR==0) { OpDissCFS(text,"fsub ,",pc,opcode); } else { OpDissCFS(text,"fsub ,",pc,opcode); } } //fmul , void d1111_nnnn_mmmm_0010(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().PR==0) { OpDissCFS(text,"fmul ,",pc,opcode); } else { OpDissCFS(text,"fmul ,",pc,opcode); } } //fdiv , void d1111_nnnn_mmmm_0011(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().PR==0) { OpDissCFS(text,"fdiv ,",pc,opcode); } else { OpDissCFS(text,"fdiv ,",pc,opcode); } } //fcmp/eq , void d1111_nnnn_mmmm_0100(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().PR==0) { OpDissCFS(text,"fcmp/eq ,",pc,opcode); } else { OpDissCFS(text,"fcmp/eq ,",pc,opcode); } } //fcmp/gt , void d1111_nnnn_mmmm_0101(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().PR==0) { OpDissCFS(text,"fcmp/gt ,",pc,opcode); } else { OpDissCFS(text,"fcmp/gt ,",pc,opcode); } } //fmov.s @(R0,), void d1111_nnnn_mmmm_0110(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().SZ==0) { OpDissCFS(text,"fmov.s @(R0,),",pc,opcode); } else { OpDissCFS(text,"fmov.s @(R0,),",pc,opcode); } } //fmov.s ,@(R0,) void d1111_nnnn_mmmm_0111(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().SZ==0) { OpDissCFS(text,"fmov.s ,@(R0,)",pc,opcode); } else { OpDissCFS(text,"fmov.s ,@(R0,)",pc,opcode); } } //fmov.s @, void d1111_nnnn_mmmm_1000(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().SZ==0) { OpDissCFS(text,"fmov.s @,",pc,opcode); } else { OpDissCFS(text,"fmov.s @,",pc,opcode); } } //fmov.s @+, void d1111_nnnn_mmmm_1001(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().SZ==0) { OpDissCFS(text,"fmov.s @+,",pc,opcode); } else { OpDissCFS(text,"fmov.s @+,",pc,opcode); } } //fmov.s ,@ void d1111_nnnn_mmmm_1010(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().SZ==0) { OpDissCFS(text,"fmov.s ,@",pc,opcode); } else { OpDissCFS(text,"fmov.s ,@",pc,opcode); } } //fmov.s ,@- void d1111_nnnn_mmmm_1011(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().SZ==0) { OpDissCFS(text,"fmov.s ,@-",pc,opcode); } else { OpDissCFS(text,"fmov.s ,@-",pc,opcode); } } //fmov , void d1111_nnnn_mmmm_1100(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().SZ==0) { OpDissCFS(text,"fmov ,",pc,opcode); } else { OpDissCFS(text,"fmov ,",pc,opcode); } } //fabs void d1111_nnnn_0101_1101(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().PR==0) { OpDissCFS(text,"fabs ",pc,opcode); } else { OpDissCFS(text,"fabs ",pc,opcode); } } //FSCA FPUL, DRn//F0FD//1111_nnn0_1111_1101 void OpDissFSCA(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().PR==0) { int n=GetN(opcode)&0xE; sprintf(text,"fsca FPUL,FR%d",n); } else { OpDissCFS(text,"fsca n/a [64bit]",pc,opcode); } } //fcnvds ,FPUL void d1111_nnnn_1011_1101(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().PR==0) { OpDissCFS(text,"fcnvds n/a [32bit]",pc,opcode); } else { OpDissCFS(text,"fcnvds ,FPUL",pc,opcode); } } //fcnvsd FPUL, void d1111_nnnn_1010_1101(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().PR==0) { OpDissCFS(text,"fcnvsd n/a [32bit]",pc,opcode); } else { OpDissCFS(text,"fcnvsd FPUL,",pc,opcode); } } //fipr , void OpDissfipr(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().PR==0) { int n=GetN(opcode); int m=GetM(opcode); sprintf(text,"fipr FV%d,FV%d",m,n); } else { OpDissCFS(text,"fipr n/a [64bit]",pc,opcode); } } //fldi0 void d1111_nnnn_1000_1101(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().PR==0) { OpDissCFS(text,"fldi0 ",pc,opcode); } else { OpDissCFS(text,"fldi0 n/a [64bit]",pc,opcode); } } //fldi1 void d1111_nnnn_1001_1101(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().PR==0) { OpDissCFS(text,"fldi1 ",pc,opcode); } else { OpDissCFS(text,"fldi1 n/a [64bit]",pc,opcode); } } //flds ,FPUL void d1111_nnnn_0001_1101(char* text,const char* tx1,u32 pc,u16 opcode) { //if (Get_fpscr().PR==0) { OpDissCFS(text,"flds ,FPUL",pc,opcode); } /* else { OpDissCFS(text,"flds ,FPUL",pc,opcode); }*/ } //float FPUL, void d1111_nnnn_0010_1101(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().PR==0) { OpDissCFS(text,"float FPUL,",pc,opcode); } else { OpDissCFS(text,"float FPUL,",pc,opcode); } } //fneg void d1111_nnnn_0100_1101(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().PR==0) { OpDissCFS(text,"fneg ",pc,opcode); } else { OpDissCFS(text,"fneg ",pc,opcode); } } //frchg - no need //fschg - no need //fsqrt void d1111_nnnn_0110_1101(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().PR==0) { OpDissCFS(text,"fsqrt ",pc,opcode); } else { OpDissCFS(text,"fsqrt ",pc,opcode); } } //ftrc , FPUL void d1111_nnnn_0011_1101(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().PR==0) { OpDissCFS(text,"ftrc , FPUL",pc,opcode); } else { OpDissCFS(text,"ftrc , FPUL",pc,opcode); } } //fsts FPUL, void d1111_nnnn_0000_1101(char* text,const char* tx1,u32 pc,u16 opcode) { /* if (Get_fpscr().PR==0) {*/ OpDissCFS(text,"fsts FPUL,",pc,opcode); /*} else { OpDissCFS(text,"fsts FPUL,",pc,opcode); }*/ } //ftrv xmtrx, void OpDissftrv(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().PR==0) { int n=GetN(opcode)>>2; sprintf(text,"ftrv xmtrx,FV%d ",n); } else { OpDissCFS(text,"ftrv n/a [64 bit]",pc,opcode); } } //fmac ,, void OpDissfmac(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().PR==0) { int n=GetN(opcode); int m=GetM(opcode); sprintf(text,"fmac FR0,FR%d,FR%d ",n,m); } else { OpDissCFS(text,"fmac n/a [64 bit]",pc,opcode); } } //FSRRA (1111nnnn 01111101) void d1111_nnnn_0111_1101(char* text,const char* tx1,u32 pc,u16 opcode) { if (Get_fpscr().PR==0) { OpDissCFS(text,"fsrra ",pc,opcode); } else { OpDissCFS(text,"fsrra ",pc,opcode); } } void OpNoDiss(char* text,const char* tx1,u32 pc,u16 opcode) { sprintf(text,"Missing Disassemble"); } void dissasm_Break(char* text,const char* tx1,u32 pc,u16 opcode) { DissasembleOpcode(0,pc,text); strcat(text,"[Break]"); } void dissasm_GDROM(char* text,const char* tx1,u32 pc,u16 opcode) { sprintf(text,"gdrom opcode *ADD REAL DISASM*"); } //jump for now.. //how about a decoded switch list ? could that _much_ faster ? //also, it could be really autogenerated (hint hint :P) // sh4_opcodelistentry opcodes[214]= { //CPU {rec_shil_icpu_nimp ,i0000_nnnn_0000_0010 ,Mask_n ,0x0002 ,Normal ,OpDissCFS,"stc SR," ,2,2,CO,fix_none}, //stc SR, {rec_shil_i0000_nnnn_0001_0010 ,i0000_nnnn_0001_0010 ,Mask_n ,0x0012 ,Normal ,OpDissCFS,"stc GBR," ,2,2,CO,fix_none}, //stc GBR, {rec_shil_i0000_nnnn_0010_0010 ,i0000_nnnn_0010_0010 ,Mask_n ,0x0022 ,Normal ,OpDissCFS,"stc VBR," ,2,2,CO,fix_none}, //stc VBR, {rec_shil_i0000_nnnn_0011_0010 ,i0000_nnnn_0011_0010 ,Mask_n ,0x0032 ,Normal ,OpDissCFS,"stc SSR," ,2,2,CO,fix_none}, //stc SSR, //STC SGR,Rn SGR > Rn 0000_nnnn_0011_1010 Privileged -(this one is 0x0f3A) {rec_shil_i0000_nnnn_0011_1010 ,i0000_nnnn_0011_1010 ,Mask_n ,0x003A ,Normal ,OpDissCFS,"stc SGR," ,3,3,CO,fix_none}, //stc SGR, {rec_shil_i0000_nnnn_0100_0010 ,i0000_nnnn_0100_0010 ,Mask_n ,0x0042 ,Normal ,OpDissCFS,"stc SPC," ,2,2,CO,fix_none}, //stc SPC, {rec_shil_i0000_nnnn_1mmm_0010 ,i0000_nnnn_1mmm_0010 ,Mask_n_ml3bit,0x0082,Normal ,OpDissCFS,"stc R0_BANK," ,2,2,CO,fix_none}, //stc R0_BANK, {rec_shil_i0000_nnnn_0010_0011 ,i0000_nnnn_0010_0011 ,Mask_n ,0x0023 ,Branch_rel_d ,OpDissCFS,"braf " ,2,3,CO,fix_none}, //braf {rec_shil_i0000_nnnn_0000_0011 ,i0000_nnnn_0000_0011 ,Mask_n ,0x0003 ,Branch_rel_d ,OpDissCFS,"bsrf " ,2,3,CO,fix_none}, //bsrf {rec_shil_i0000_nnnn_1100_0011 ,i0000_nnnn_1100_0011 ,Mask_n ,0x00C3 ,Normal ,OpDissCFS,"movca.l R0, @" ,2,4,MA,fix_none}, //movca.l R0, @ {rec_shil_i0000_nnnn_1001_0011 ,i0000_nnnn_1001_0011 ,Mask_n ,0x0093 ,Normal ,OpDissCFS,"ocbi @" ,1,2,MA,fix_none}, //ocbi @ {rec_shil_i0000_nnnn_1010_0011 ,i0000_nnnn_1010_0011 ,Mask_n ,0x00A3 ,Normal ,OpDissCFS,"ocbp @" ,1,2,MA,fix_none}, //ocbp @ {rec_shil_i0000_nnnn_1011_0011 ,i0000_nnnn_1011_0011 ,Mask_n ,0x00B3 ,Normal ,OpDissCFS,"ocbwb @" ,1,2,MA,fix_none}, //ocbwb @ {rec_shil_i0000_nnnn_1000_0011 ,i0000_nnnn_1000_0011 ,Mask_n ,0x0083 ,Normal ,OpDissCFS,"pref @" ,1,2,LS,fix_none}, //pref @ {rec_shil_i0000_nnnn_mmmm_0100 ,i0000_nnnn_mmmm_0100 ,Mask_n_m ,0x0004 ,Normal ,OpDissCFS,"mov.b ,@(R0,)" ,1,1,LS,fix_none}, //mov.b ,@(R0,) {rec_shil_i0000_nnnn_mmmm_0101 ,i0000_nnnn_mmmm_0101 ,Mask_n_m ,0x0005 ,Normal ,OpDissCFS,"mov.w ,@(R0,)" ,1,1,LS,fix_none}, //mov.w ,@(R0,) {rec_shil_i0000_nnnn_mmmm_0110 ,i0000_nnnn_mmmm_0110 ,Mask_n_m ,0x0006 ,Normal ,OpDissCFS,"mov.l ,@(R0,)" ,1,1,LS,fix_none}, //mov.l ,@(R0,) {rec_shil_i0000_nnnn_mmmm_0111 ,i0000_nnnn_mmmm_0111 ,Mask_n_m ,0x0007 ,Normal ,OpDissCFS,"mul.l ," ,2,4,CO,fix_none}, //mul.l , {rec_shil_i0000_0000_0010_1000 ,i0000_0000_0010_1000 ,Mask_none ,0x0028 ,Normal ,OpDissCFS,"clrmac" ,1,3,LS,fix_none}, //clrmac {rec_shil_i0000_0000_0100_1000 ,i0000_0000_0100_1000 ,Mask_none ,0x0048 ,Normal ,OpDissCFS,"clrs" ,1,1,CO,fix_none}, //clrs {rec_shil_i0000_0000_0000_1000 ,i0000_0000_0000_1000 ,Mask_none ,0x0008 ,Normal ,OpDissCFS,"clrt" ,1,1,MT,fix_none}, //clrt {rec_shil_i0000_0000_0011_1000 ,i0000_0000_0011_1000 ,Mask_none ,0x0038 ,Normal ,OpDissCFS,"ldtlb" ,1,1,CO,fix_none},//ldtlb {rec_shil_i0000_0000_0101_1000 ,i0000_0000_0101_1000 ,Mask_none ,0x0058 ,Normal ,OpDissCFS,"sets" ,1,1,CO,fix_none}, //sets {rec_shil_i0000_0000_0001_1000 ,i0000_0000_0001_1000 ,Mask_none ,0x0018 ,Normal ,OpDissCFS,"sett" ,1,1,MT,fix_none}, //sett {rec_shil_i0000_0000_0001_1001 ,i0000_0000_0001_1001 ,Mask_none ,0x0019 ,Normal ,OpDissCFS,"div0u" ,1,1,EX,fix_none},//div0u {rec_shil_i0000_nnnn_0010_1001 ,i0000_nnnn_0010_1001 ,Mask_n ,0x0029 ,Normal ,OpDissCFS,"movt " ,1,1,EX,fix_none}, //movt {rec_shil_i0000_0000_0000_1001 ,i0000_0000_0000_1001 ,Mask_none ,0x0009 ,Normal ,OpDissCFS,"nop" ,1,0,MT,fix_none}, //nop {rec_shil_i0000_nnnn_0101_1010 ,i0000_nnnn_0101_1010 ,Mask_n ,0x005A ,Normal ,OpDissCFS,"sts FPUL," ,1,3,LS,fix_none}, //sts FPUL, {rec_shil_icpu_nimp ,i0000_nnnn_0110_1010 ,Mask_n ,0x006A ,Normal ,OpDissCFS,"sts FPSCR," ,1,3,CO,fix_none},//sts FPSCR, {rec_shil_i0000_nnnn_1111_1010 ,i0000_nnnn_1111_1010 ,Mask_n ,0x00FA ,Normal ,OpDissCFS,"stc DBR," ,1,2,CO,fix_none}, //stc DBR, //guess {rec_shil_i0000_nnnn_0000_1010 ,i0000_nnnn_0000_1010 ,Mask_n ,0x000A ,Normal ,OpDissCFS,"sts MACH," ,1,3,CO,fix_none}, //sts MACH, {rec_shil_i0000_nnnn_0001_1010 ,i0000_nnnn_0001_1010 ,Mask_n ,0x001A ,Normal ,OpDissCFS,"sts MACL," ,1,3,CO,fix_none}, //sts MACL, {rec_shil_i0000_nnnn_0010_1010 ,i0000_nnnn_0010_1010 ,Mask_n ,0x002A ,Normal ,OpDissCFS,"sts PR," ,2,2,CO,fix_none}, //sts PR, {rec_shil_i0000_0000_0010_1011 ,i0000_0000_0010_1011 ,Mask_none ,0x002B ,WritesPC ,OpDissCFS,"rte" ,5,5,CO,fix_none}, //rte {rec_shil_i0000_0000_0000_1011 ,i0000_0000_0000_1011 ,Mask_none ,0x000B ,Branch_dir_d ,OpDissCFS,"rts" ,2,3,CO,fix_none}, //rts {rec_shil_i0000_0000_0001_1011 ,i0000_0000_0001_1011 ,Mask_none ,0x001B ,ReadWritePC ,OpDissCFS,"sleep" ,4,4,CO,fix_none}, //sleep {rec_shil_i0000_nnnn_mmmm_1100 ,i0000_nnnn_mmmm_1100 ,Mask_n_m ,0x000C ,Normal ,OpDissCFS,"mov.b @(R0,)," ,1,2,LS,fix_none}, //mov.b @(R0,), {rec_shil_i0000_nnnn_mmmm_1101 ,i0000_nnnn_mmmm_1101 ,Mask_n_m ,0x000D ,Normal ,OpDissCFS,"mov.w @(R0,)," ,1,2,LS,fix_none}, //mov.w @(R0,), {rec_shil_i0000_nnnn_mmmm_1110 ,i0000_nnnn_mmmm_1110 ,Mask_n_m ,0x000E ,Normal ,OpDissCFS,"mov.l @(R0,)," ,1,2,LS,fix_none}, //mov.l @(R0,), {rec_shil_i0000_nnnn_mmmm_1111 ,i0000_nnnn_mmmm_1111 ,Mask_n_m ,0x000F ,Normal ,OpDissCFS,"mac.l @+,@+" ,2,3,CO,fix_none}, //mac.l @+,@+ {rec_shil_i0001_nnnn_mmmm_iiii ,i0001_nnnn_mmmm_iiii ,Mask_n_imm8,0x1000 ,Normal ,OpDissCFS,"mov.l ,@(,)",1,1,LS,fix_none}, //mov.l ,@(,) {rec_shil_i0010_nnnn_mmmm_0000 ,i0010_nnnn_mmmm_0000 ,Mask_n_m ,0x2000 ,Normal ,OpDissCFS,"mov.b ,@" ,1,1,LS,fix_none}, //mov.b ,@ {rec_shil_i0010_nnnn_mmmm_0001 ,i0010_nnnn_mmmm_0001 ,Mask_n_m ,0x2001 ,Normal ,OpDissCFS,"mov.w ,@" ,1,1,LS,fix_none}, // mov.w ,@ {rec_shil_i0010_nnnn_mmmm_0010 ,i0010_nnnn_mmmm_0010 ,Mask_n_m ,0x2002 ,Normal ,OpDissCFS,"mov.l ,@" ,1,1,LS,fix_none}, // mov.l ,@ {rec_shil_i0010_nnnn_mmmm_0100 ,i0010_nnnn_mmmm_0100 ,Mask_n_m ,0x2004 ,Normal ,OpDissCFS,"mov.b ,@-" ,1,1,LS,rn_opt_1}, // mov.b ,@- {rec_shil_i0010_nnnn_mmmm_0101 ,i0010_nnnn_mmmm_0101 ,Mask_n_m ,0x2005 ,Normal ,OpDissCFS,"mov.w ,@-" ,1,1,LS,rn_opt_2}, //mov.w ,@- {rec_shil_i0010_nnnn_mmmm_0110 ,i0010_nnnn_mmmm_0110 ,Mask_n_m ,0x2006 ,Normal ,OpDissCFS,"mov.l ,@-" ,1,1,LS,rn_opt_4}, //mov.l ,@- {rec_shil_i0010_nnnn_mmmm_0111 ,i0010_nnnn_mmmm_0111 ,Mask_n_m ,0x2007 ,Normal ,OpDissCFS,"div0s ," ,1,1,EX,fix_none}, // div0s , {rec_shil_i0010_nnnn_mmmm_1000 ,i0010_nnnn_mmmm_1000 ,Mask_n_m ,0x2008 ,Normal ,OpDissCFS,"tst ," ,1,1,MT,fix_none}, // tst , {rec_shil_i0010_nnnn_mmmm_1001 ,i0010_nnnn_mmmm_1001 ,Mask_n_m ,0x2009 ,Normal ,OpDissCFS,"and ," ,1,1,EX,fix_none}, //and , {rec_shil_i0010_nnnn_mmmm_1010 ,i0010_nnnn_mmmm_1010 ,Mask_n_m ,0x200A ,Normal ,OpDissCFS,"xor ," ,1,1,EX,fix_none}, //xor , {rec_shil_i0010_nnnn_mmmm_1011 ,i0010_nnnn_mmmm_1011 ,Mask_n_m ,0x200B ,Normal ,OpDissCFS,"or ," ,1,1,EX,fix_none}, //or , {rec_shil_i0010_nnnn_mmmm_1100 ,i0010_nnnn_mmmm_1100 ,Mask_n_m ,0x200C ,Normal ,OpDissCFS,"cmp/str ," ,1,1,MT,fix_none}, //cmp/str , {rec_shil_i0010_nnnn_mmmm_1101 ,i0010_nnnn_mmmm_1101 ,Mask_n_m ,0x200D ,Normal ,OpDissCFS,"xtrct ," ,1,1,EX,fix_none}, //xtrct , {rec_shil_i0010_nnnn_mmmm_1110 ,i0010_nnnn_mmmm_1110 ,Mask_n_m ,0x200E ,Normal ,OpDissCFS,"mulu.w ," ,1,4,CO,fix_none}, //mulu.w , {rec_shil_i0010_nnnn_mmmm_1111 ,i0010_nnnn_mmmm_1111 ,Mask_n_m ,0x200F ,Normal ,OpDissCFS,"muls.w ," ,1,4,CO,fix_none}, //muls.w , {rec_shil_i0011_nnnn_mmmm_0000 ,i0011_nnnn_mmmm_0000 ,Mask_n_m ,0x3000 ,Normal ,OpDissCFS,"cmp/eq ," ,1,1,MT,fix_none}, // cmp/eq , {rec_shil_i0011_nnnn_mmmm_0010 ,i0011_nnnn_mmmm_0010 ,Mask_n_m ,0x3002 ,Normal ,OpDissCFS,"cmp/hs ," ,1,1,MT,fix_none}, // cmp/hs , {rec_shil_i0011_nnnn_mmmm_0011 ,i0011_nnnn_mmmm_0011 ,Mask_n_m ,0x3003 ,Normal ,OpDissCFS,"cmp/ge ," ,1,1,MT,fix_none}, //cmp/ge , {rec_shil_i0011_nnnn_mmmm_0100 ,i0011_nnnn_mmmm_0100 ,Mask_n_m ,0x3004 ,Normal ,OpDissCFS,"div1 ," ,1,1,EX,fix_none}, //div1 , {rec_shil_i0011_nnnn_mmmm_0101 ,i0011_nnnn_mmmm_0101 ,Mask_n_m ,0x3005 ,Normal ,OpDissCFS,"dmulu.l ," ,2,4,CO,fix_none}, //dmulu.l , {rec_shil_i0011_nnnn_mmmm_0110 ,i0011_nnnn_mmmm_0110 ,Mask_n_m ,0x3006 ,Normal ,OpDissCFS,"cmp/hi ," ,1,1,MT,fix_none}, // cmp/hi , {rec_shil_i0011_nnnn_mmmm_0111 ,i0011_nnnn_mmmm_0111 ,Mask_n_m ,0x3007 ,Normal ,OpDissCFS,"cmp/gt ," ,1,1,MT,fix_none}, //cmp/gt , {rec_shil_i0011_nnnn_mmmm_1000 ,i0011_nnnn_mmmm_1000 ,Mask_n_m ,0x3008 ,Normal ,OpDissCFS,"sub ," ,1,1,EX,fix_none}, // sub , {rec_shil_i0011_nnnn_mmmm_1010 ,i0011_nnnn_mmmm_1010 ,Mask_n_m ,0x300A ,Normal ,OpDissCFS,"subc ," ,1,1,EX,fix_none}, //subc , {rec_shil_i0011_nnnn_mmmm_1011 ,i0011_nnnn_mmmm_1011 ,Mask_n_m ,0x300B ,Normal ,OpDissCFS,"subv ," ,1,1,EX,fix_none}, //subv , {rec_shil_i0011_nnnn_mmmm_1100 ,i0011_nnnn_mmmm_1100 ,Mask_n_m ,0x300C ,Normal ,OpDissCFS,"add ," ,1,1,EX,fix_none}, //add , {rec_shil_i0011_nnnn_mmmm_1101 ,i0011_nnnn_mmmm_1101 ,Mask_n_m ,0x300D ,Normal ,OpDissCFS,"dmuls.l ," ,1,4,CO,fix_none}, //dmuls.l , {rec_shil_i0011_nnnn_mmmm_1110 ,i0011_nnnn_mmmm_1110 ,Mask_n_m ,0x300E ,Normal ,OpDissCFS,"addc ," ,1,1,EX,fix_none}, //addc , {rec_shil_i0011_nnnn_mmmm_1111 ,i0011_nnnn_mmmm_1111 ,Mask_n_m ,0x300F ,Normal ,OpDissCFS,"addv ," ,1,1,EX,fix_none}, // addv , {rec_shil_i0100_nnnn_0101_0010 ,i0100_nnnn_0101_0010 ,Mask_n ,0x4052 ,Normal ,OpDissCFS,"sts.l FPUL,@-" ,1,1,CO,rn_4 }, //sts.l FPUL,@- {rec_shil_icpu_nimp ,i0100_nnnn_0110_0010 ,Mask_n ,0x4062 ,Normal ,OpDissCFS,"sts.l FPSCR,@-" ,1,2,CO,rn_4 }, //sts.l FPSCR,@- {rec_shil_i0100_nnnn_0000_0010 ,i0100_nnnn_0000_0010 ,Mask_n ,0x4002 ,Normal ,OpDissCFS,"sts.l MACH,@-" ,1,3,CO,rn_4 }, //sts.l MACH,@- {rec_shil_i0100_nnnn_0001_0010 ,i0100_nnnn_0001_0010 ,Mask_n ,0x4012 ,Normal ,OpDissCFS,"sts.l MACL,@-" ,1,3,CO,rn_4 }, //sts.l MACL,@- {rec_shil_i0100_nnnn_0010_0010 ,i0100_nnnn_0010_0010 ,Mask_n ,0x4022 ,Normal ,OpDissCFS,"sts.l PR,@-" ,1,1,CO,rn_4 }, //sts.l PR,@- //STC.L DBR,@-Rn 0100_nnnn_1111_0010 Privileged - {rec_shil_i0100_nnnn_1111_0010 ,i0100_nnnn_1111_0010 ,Mask_n ,0x40F2 ,Normal ,OpDissCFS,"stc.l DBR,@-" ,2,2,CO,rn_4 }, //stc.l DBR,@- {rec_shil_icpu_nimp ,i0100_nnnn_0000_0011 ,Mask_n ,0x4003 ,Normal ,OpDissCFS,"stc.l SR,@-" ,1,1,CO,rn_4 }, //stc.l SR,@- {rec_shil_i0100_nnnn_0001_0011 ,i0100_nnnn_0001_0011 ,Mask_n ,0x4013 ,Normal ,OpDissCFS,"stc.l GBR,@-" ,1,1,CO,rn_4 }, //stc.l GBR,@- {rec_shil_i0100_nnnn_0010_0011 ,i0100_nnnn_0010_0011 ,Mask_n ,0x4023 ,Normal ,OpDissCFS,"stc.l VBR,@-" ,1,1,CO,rn_4 }, //stc.l VBR,@- {rec_shil_i0100_nnnn_0011_0011 ,i0100_nnnn_0011_0011 ,Mask_n ,0x4033 ,Normal ,OpDissCFS,"stc.l SSR,@-" ,1,1,CO,rn_4 }, //stc.l SSR,@- //STC.L SGR,@-Rn 0100_nnnn_0011_0010 Privileged - {rec_shil_i0100_nnnn_0011_0010 ,i0100_nnnn_0011_0010 ,Mask_n ,0x4032 ,Normal ,OpDissCFS,"stc.l SGR,@-" ,3,3,CO,rn_4 }, //stc.l SGR,@- {rec_shil_i0100_nnnn_0100_0011 ,i0100_nnnn_0100_0011 ,Mask_n ,0x4043 ,Normal ,OpDissCFS,"stc.l SPC,@-" ,1,1,CO,rn_4 }, //stc.l SPC,@- {rec_shil_i0100_nnnn_1mmm_0011 ,i0100_nnnn_1mmm_0011 ,Mask_n_ml3bit,0x4083,Normal ,OpDissCFS,"stc ,@-" ,1,1,CO,rn_4 }, //stc Rm_BANK,@- {rec_shil_i0100_nnnn_0000_0110 ,i0100_nnnn_0000_0110 ,Mask_n ,0x4006 ,Normal ,OpDissCFS,"lds.l @+,MACH" ,1,1,CO,fix_none}, //lds.l @+,MACH {rec_shil_i0100_nnnn_0001_0110 ,i0100_nnnn_0001_0110 ,Mask_n ,0x4016 ,Normal ,OpDissCFS,"lds.l @+,MACL" ,1,1,CO,fix_none}, //lds.l @+,MACL {rec_shil_i0100_nnnn_0010_0110 ,i0100_nnnn_0010_0110 ,Mask_n ,0x4026 ,Normal ,OpDissCFS,"lds.l @+,PR" ,1,2,CO,fix_none}, //lds.l @+,PR {rec_shil_i0100_nnnn_0101_0110 ,i0100_nnnn_0101_0110 ,Mask_n ,0x4056 ,Normal ,OpDissCFS,"lds.l @+,FPUL" ,1,1,CO,fix_none}, //lds.l @+,FPUL {rec_shil_icpu_nimp ,i0100_nnnn_0110_0110 ,Mask_n ,0x4066 ,WritesFPSCR ,OpDissCFS,"lds.l @+,FPSCR" ,1,1,CO,fix_none}, //lds.l @+,FPSCR //LDC.L @Rm+,DBR 0100_mmmm_1111_0110 Privileged - {rec_shil_i0100_nnnn_1111_0110 ,i0100_nnnn_1111_0110 ,Mask_n ,0x40F6 ,Normal ,OpDissCFS,"ldc.l @+,DBR" ,1,3,CO,fix_none}, //ldc.l @+,DBR {rec_shil_icpu_nimp ,i0100_nnnn_0000_0111 ,Mask_n ,0x4007 ,WritesSR ,OpDissCFS,"ldc.l @+,SR" ,1,1,CO,fix_none}, //ldc.l @+,SR {rec_shil_i0100_nnnn_0001_0111 ,i0100_nnnn_0001_0111 ,Mask_n ,0x4017 ,Normal ,OpDissCFS,"ldc.l @+,GBR" ,1,1,CO,fix_none}, //ldc.l @+,GBR {rec_shil_i0100_nnnn_0010_0111 ,i0100_nnnn_0010_0111 ,Mask_n ,0x4027 ,Normal ,OpDissCFS,"ldc.l @+,VBR" ,1,1,CO,fix_none}, //ldc.l @+,VBR {rec_shil_i0100_nnnn_0011_0111 ,i0100_nnnn_0011_0111 ,Mask_n ,0x4037 ,Normal ,OpDissCFS,"ldc.l @+,SSR" ,1,1,CO,fix_none}, //ldc.l @+,SSR //LDC.L @Rm+,SGR (Rm) 0100_mmmm_0011_0110 Privileged - {rec_shil_i0100_nnnn_0011_0110 ,i0100_nnnn_0011_0110 ,Mask_n ,0x4036 ,Normal ,OpDissCFS,"ldc.l @+,SGR" ,3,3,CO,fix_none}, //ldc.l @+,SGR {rec_shil_i0100_nnnn_0100_0111 ,i0100_nnnn_0100_0111 ,Mask_n ,0x4047 ,Normal ,OpDissCFS,"ldc.l @+,SPC" ,1,1,CO,fix_none}, //ldc.l @+,SPC {rec_shil_i0100_nnnn_1mmm_0111 ,i0100_nnnn_1mmm_0111 ,Mask_n_ml3bit,0x4087,Normal ,OpDissCFS,"ldc.l @+,RM_BANK" ,1,1,CO,fix_none}, //ldc.l @+,RM_BANK {rec_shil_i0100_nnnn_0000_1010 ,i0100_nnnn_0000_1010 ,Mask_n ,0x400A ,Normal ,OpDissCFS,"lds ,MACH" ,1,3,CO,fix_none}, //lds ,MACH {rec_shil_i0100_nnnn_0001_1010 ,i0100_nnnn_0001_1010 ,Mask_n ,0x401A ,Normal ,OpDissCFS,"lds ,MACL" ,1,3,CO,fix_none}, //lds ,MACL {rec_shil_i0100_nnnn_0010_1010 ,i0100_nnnn_0010_1010 ,Mask_n ,0x402A ,Normal ,OpDissCFS,"lds ,PR" ,1,2,CO,fix_none}, //lds ,PR {rec_shil_i0100_nnnn_0101_1010 ,i0100_nnnn_0101_1010 ,Mask_n ,0x405A ,Normal ,OpDissCFS,"lds ,FPUL" ,1,1,CO,fix_none}, //lds ,FPUL {rec_shil_icpu_nimp ,i0100_nnnn_0110_1010 ,Mask_n ,0x406A ,WritesFPSCR ,OpDissCFS,"lds ,FPSCR" ,1,1,CO,fix_none}, //lds ,FPSCR {rec_shil_i0100_nnnn_1111_1010 ,i0100_nnnn_1111_1010 ,Mask_n ,0x40FA ,Normal ,OpDissCFS,"ldc ,DBR" ,1,1,CO,fix_none}, //ldc ,DBR {rec_shil_icpu_nimp ,i0100_nnnn_0000_1110 ,Mask_n ,0x400E ,WritesSR ,OpDissCFS,"ldc ,SR" ,1,1,CO,fix_none}, //ldc ,SR {rec_shil_i0100_nnnn_0001_1110 ,i0100_nnnn_0001_1110 ,Mask_n ,0x401E ,Normal ,OpDissCFS,"ldc ,GBR" ,1,1,CO,fix_none}, //ldc ,GBR {rec_shil_i0100_nnnn_0010_1110 ,i0100_nnnn_0010_1110 ,Mask_n ,0x402E ,Normal ,OpDissCFS,"ldc ,VBR" ,1,1,CO,fix_none}, //ldc ,VBR {rec_shil_i0100_nnnn_0011_1110 ,i0100_nnnn_0011_1110 ,Mask_n ,0x403E ,Normal ,OpDissCFS,"ldc ,SSR" ,1,1,CO,fix_none}, //ldc ,SSR //LDC Rm,SGR Rm > SGR 0100_mmmm_0011_1010 Privileged - {rec_shil_i0100_nnnn_0011_1010 ,i0100_nnnn_0011_1010 ,Mask_n ,0x403A ,Normal ,OpDissCFS,"ldc ,SGR" ,3,3,CO,fix_none}, //ldc ,SGR {rec_shil_i0100_nnnn_0100_1110 ,i0100_nnnn_0100_1110 ,Mask_n ,0x404E ,Normal ,OpDissCFS,"ldc ,SPC" ,1,1,CO,fix_none}, //ldc ,SPC {rec_shil_i0100_nnnn_1mmm_1110 ,i0100_nnnn_1mmm_1110 ,Mask_n_ml3bit,0x408E,Normal ,OpDissCFS,"ldc ," ,1,1,CO,fix_none}, //ldc , {rec_shil_i0100_nnnn_0000_0000 ,i0100_nnnn_0000_0000 ,Mask_n ,0x4000 ,Normal ,OpDissCFS,"shll " ,1,1,EX,fix_none}, //shll {rec_shil_i0100_nnnn_0001_0000 ,i0100_nnnn_0001_0000 ,Mask_n ,0x4010 ,Normal ,OpDissCFS,"dt " ,1,1,EX,fix_none}, //dt {rec_shil_i0100_nnnn_0010_0000 ,i0100_nnnn_0010_0000 ,Mask_n ,0x4020 ,Normal ,OpDissCFS,"shal " ,1,1,EX,fix_none}, //shal {rec_shil_i0100_nnnn_0000_0001 ,i0100_nnnn_0000_0001 ,Mask_n ,0x4001 ,Normal ,OpDissCFS,"shlr " ,1,1,EX,fix_none}, //shlr {rec_shil_i0100_nnnn_0001_0001 ,i0100_nnnn_0001_0001 ,Mask_n ,0x4011 ,Normal ,OpDissCFS,"cmp/pz " ,1,1,MT,fix_none}, //cmp/pz {rec_shil_i0100_nnnn_0010_0001 ,i0100_nnnn_0010_0001 ,Mask_n ,0x4021 ,Normal ,OpDissCFS,"shar " ,1,1,EX,fix_none}, //shar {rec_shil_i0100_nnnn_0010_0100 ,i0100_nnnn_0010_0100 ,Mask_n ,0x4024 ,Normal ,OpDissCFS,"rotcl " ,1,1,EX,fix_none}, //rotcl {rec_shil_i0100_nnnn_0000_0100 ,i0100_nnnn_0000_0100 ,Mask_n ,0x4004 ,Normal ,OpDissCFS,"rotl " ,1,1,EX,fix_none}, //rotl {rec_shil_i0100_nnnn_0001_0101 ,i0100_nnnn_0001_0101 ,Mask_n ,0x4015 ,Normal ,OpDissCFS,"cmp/pl " ,1,1,MT,fix_none}, //cmp/pl {rec_shil_i0100_nnnn_0010_0101 ,i0100_nnnn_0010_0101 ,Mask_n ,0x4025 ,Normal ,OpDissCFS,"rotcr " ,1,1,EX,fix_none}, //rotcr {rec_shil_i0100_nnnn_0000_0101 ,i0100_nnnn_0000_0101 ,Mask_n ,0x4005 ,Normal ,OpDissCFS,"rotr " ,1,1,EX,fix_none}, //rotr {rec_shil_i0100_nnnn_0000_1000 ,i0100_nnnn_0000_1000 ,Mask_n ,0x4008 ,Normal ,OpDissCFS,"shll2 " ,1,1,EX,fix_none}, //shll2 {rec_shil_i0100_nnnn_0001_1000 ,i0100_nnnn_0001_1000 ,Mask_n ,0x4018 ,Normal ,OpDissCFS,"shll8 " ,1,1,EX,fix_none}, //shll8 {rec_shil_i0100_nnnn_0010_1000 ,i0100_nnnn_0010_1000 ,Mask_n ,0x4028 ,Normal ,OpDissCFS,"shll16 " ,1,1,EX,fix_none}, //shll16 {rec_shil_i0100_nnnn_0000_1001 ,i0100_nnnn_0000_1001 ,Mask_n ,0x4009 ,Normal ,OpDissCFS,"shlr2 " ,1,1,EX,fix_none}, //shlr2 {rec_shil_i0100_nnnn_0001_1001 ,i0100_nnnn_0001_1001 ,Mask_n ,0x4019 ,Normal ,OpDissCFS,"shlr8 " ,1,1,EX,fix_none}, //shlr8 {rec_shil_i0100_nnnn_0010_1001 ,i0100_nnnn_0010_1001 ,Mask_n ,0x4029 ,Normal ,OpDissCFS,"shlr16 " ,1,1,EX,fix_none}, //shlr16 {rec_shil_i0100_nnnn_0010_1011 ,i0100_nnnn_0010_1011 ,Mask_n ,0x402B ,Branch_dir_d ,OpDissCFS,"jmp @" ,2,3,CO,fix_none}, //jmp @ {rec_shil_i0100_nnnn_0000_1011 ,i0100_nnnn_0000_1011 ,Mask_n ,0x400B ,Branch_dir_d ,OpDissCFS,"jsr @" ,2,3,CO,fix_none}, //jsr @ {rec_shil_i0100_nnnn_0001_1011 ,i0100_nnnn_0001_1011 ,Mask_n ,0x401B ,Normal ,OpDissCFS,"tas.b @" ,5,5,CO,fix_none}, //tas.b @ {rec_shil_i0100_nnnn_mmmm_1100 ,i0100_nnnn_mmmm_1100 ,Mask_n_m ,0x400C ,Normal ,OpDissCFS,"shad ," ,1,1,EX,fix_none}, //shad , {rec_shil_i0100_nnnn_mmmm_1101 ,i0100_nnnn_mmmm_1101 ,Mask_n_m ,0x400D ,Normal ,OpDissCFS,"shld ," ,1,1,EX,fix_none}, //shld , {rec_shil_i0100_nnnn_mmmm_1111 ,i0100_nnnn_mmmm_1111 ,Mask_n_m ,0x400F ,Normal ,OpDissCFS,"mac.w @+,@+" ,2,3,CO,fix_none}, //mac.w @+,@+ {rec_shil_i0101_nnnn_mmmm_iiii ,i0101_nnnn_mmmm_iiii ,Mask_n_m_imm4,0x5000,Normal ,OpDissCFS,"mov.l @(,),",1,2,LS,fix_none},//mov.l @(,), {rec_shil_i0110_nnnn_mmmm_0000 ,i0110_nnnn_mmmm_0000 ,Mask_n_m ,0x6000 ,Normal ,OpDissCFS,"mov.b @," ,1,2,LS,fix_none}, //mov.b @, {rec_shil_i0110_nnnn_mmmm_0001 ,i0110_nnnn_mmmm_0001 ,Mask_n_m ,0x6001 ,Normal ,OpDissCFS,"mov.w @," ,1,2,LS,fix_none}, //mov.w @, {rec_shil_i0110_nnnn_mmmm_0010 ,i0110_nnnn_mmmm_0010 ,Mask_n_m ,0x6002 ,Normal ,OpDissCFS,"mov.l @," ,1,2,LS,fix_none}, //mov.l @, {rec_shil_i0110_nnnn_mmmm_0011 ,i0110_nnnn_mmmm_0011 ,Mask_n_m ,0x6003 ,Normal ,OpDissCFS,"mov ," ,1,0,MT,fix_none}, //mov , {rec_shil_i0110_nnnn_mmmm_0100 ,i0110_nnnn_mmmm_0100 ,Mask_n_m ,0x6004 ,Normal ,OpDissCFS,"mov.b @+," ,1,1,LS,fix_none}, //mov.b @+, {rec_shil_i0110_nnnn_mmmm_0101 ,i0110_nnnn_mmmm_0101 ,Mask_n_m ,0x6005 ,Normal ,OpDissCFS,"mov.w @+," ,1,1,LS,fix_none}, //mov.w @+, {rec_shil_i0110_nnnn_mmmm_0110 ,i0110_nnnn_mmmm_0110 ,Mask_n_m ,0x6006 ,Normal ,OpDissCFS,"mov.l @+," ,1,1,LS,fix_none}, //mov.l @+, {rec_shil_i0110_nnnn_mmmm_0111 ,i0110_nnnn_mmmm_0111 ,Mask_n_m ,0x6007 ,Normal ,OpDissCFS,"not ," ,1,1,EX,fix_none}, //not , {rec_shil_i0110_nnnn_mmmm_1000 ,i0110_nnnn_mmmm_1000 ,Mask_n_m ,0x6008 ,Normal ,OpDissCFS,"swap.b ," ,1,1,EX,fix_none}, //swap.b , {rec_shil_i0110_nnnn_mmmm_1001 ,i0110_nnnn_mmmm_1001 ,Mask_n_m ,0x6009 ,Normal ,OpDissCFS,"swap.w ," ,1,1,EX,fix_none}, //swap.w , {rec_shil_i0110_nnnn_mmmm_1010 ,i0110_nnnn_mmmm_1010 ,Mask_n_m ,0x600A ,Normal ,OpDissCFS,"negc ," ,1,1,EX,fix_none}, //negc , {rec_shil_i0110_nnnn_mmmm_1011 ,i0110_nnnn_mmmm_1011 ,Mask_n_m ,0x600B ,Normal ,OpDissCFS,"neg ," ,1,1,EX,fix_none}, //neg , {rec_shil_i0110_nnnn_mmmm_1100 ,i0110_nnnn_mmmm_1100 ,Mask_n_m ,0x600C ,Normal ,OpDissCFS,"extu.b ," ,1,1,EX,fix_none}, //extu.b , {rec_shil_i0110_nnnn_mmmm_1101 ,i0110_nnnn_mmmm_1101 ,Mask_n_m ,0x600D ,Normal ,OpDissCFS,"extu.w ," ,1,1,EX,fix_none}, //extu.w , {rec_shil_i0110_nnnn_mmmm_1110 ,i0110_nnnn_mmmm_1110 ,Mask_n_m ,0x600E ,Normal ,OpDissCFS,"exts.b ," ,1,1,EX,fix_none}, //exts.b , {rec_shil_i0110_nnnn_mmmm_1111 ,i0110_nnnn_mmmm_1111 ,Mask_n_m ,0x600F ,Normal ,OpDissCFS,"exts.w ," ,1,1,EX,fix_none}, //exts.w , {rec_shil_i0111_nnnn_iiii_iiii ,i0111_nnnn_iiii_iiii ,Mask_n_imm8,0x7000 ,Normal ,OpDissCFS,"add #," ,1,1,EX,fix_none}, //add #, {rec_shil_i1000_1011_iiii_iiii ,i1000_1011_iiii_iiii ,Mask_imm8 ,0x8B00 ,Branch_rel ,OpDissCFS,"bf " ,1,1,BR,fix_none}, // bf {rec_shil_i1000_1111_iiii_iiii ,i1000_1111_iiii_iiii ,Mask_imm8 ,0x8F00 ,Branch_rel_d ,OpDissCFS,"bf.s " ,1,1,BR,fix_none}, // bf.s {rec_shil_i1000_1001_iiii_iiii ,i1000_1001_iiii_iiii ,Mask_imm8 ,0x8900 ,Branch_rel ,OpDissCFS,"bt " ,1,1,BR,fix_none}, // bt {rec_shil_i1000_1101_iiii_iiii ,i1000_1101_iiii_iiii ,Mask_imm8 ,0x8D00 ,Branch_rel_d ,OpDissCFS,"bt.s " ,1,1,BR,fix_none}, // bt.s {rec_shil_i1000_1000_iiii_iiii ,i1000_1000_iiii_iiii ,Mask_imm8 ,0x8800 ,Normal ,OpDissCFS,"cmp/eq #,R0" ,1,1,MT,fix_none}, // cmp/eq #,R0 {rec_shil_i1000_0000_mmmm_iiii ,i1000_0000_mmmm_iiii ,Mask_imm8 ,0x8000 ,Normal ,OpDissCFS,"mov.b R0,@(,)" ,1,1,LS,fix_none}, // mov.b R0,@(,) {rec_shil_i1000_0001_mmmm_iiii ,i1000_0001_mmmm_iiii ,Mask_imm8 ,0x8100 ,Normal ,OpDissCFS,"mov.w R0,@(,)" ,1,1,LS,fix_none}, // mov.w R0,@(,) {rec_shil_i1000_0100_mmmm_iiii ,i1000_0100_mmmm_iiii ,Mask_imm8 ,0x8400 ,Normal ,OpDissCFS,"mov.b @(,),R0" ,1,2,LS,fix_none}, // mov.b @(,),R0 {rec_shil_i1000_0101_mmmm_iiii ,i1000_0101_mmmm_iiii ,Mask_imm8 ,0x8500 ,Normal ,OpDissCFS,"mov.w @(,),R0" ,1,2,LS,fix_none}, // mov.w @(,),R0 {rec_shil_i1001_nnnn_iiii_iiii ,i1001_nnnn_iiii_iiii ,Mask_n_imm8,0x9000 ,ReadsPC ,OpDissCFS,"mov.w @()," ,1,2,LS,fix_none}, //mov.w @(,PC), {rec_shil_i1010_iiii_iiii_iiii ,i1010_iiii_iiii_iiii ,Mask_n_imm8,0xA000 ,Branch_rel_d ,OpDissCFS,"bra " ,1,2,BR,fix_none}, // bra {rec_shil_i1011_iiii_iiii_iiii ,i1011_iiii_iiii_iiii ,Mask_n_imm8,0xB000 ,Branch_rel_d ,OpDissCFS,"bsr " ,1,2,BR,fix_none}, // bsr {rec_shil_i1100_0000_iiii_iiii ,i1100_0000_iiii_iiii ,Mask_imm8 ,0xC000 ,Normal ,OpDissCFS,"mov.b R0,@(,GBR)" ,1,1,LS,fix_none}, // mov.b R0,@(,GBR) {rec_shil_i1100_0001_iiii_iiii ,i1100_0001_iiii_iiii ,Mask_imm8 ,0xC100 ,Normal ,OpDissCFS,"mov.w R0,@(,GBR)" ,1,1,LS,fix_none}, // mov.w R0,@(,GBR) {rec_shil_i1100_0010_iiii_iiii ,i1100_0010_iiii_iiii ,Mask_imm8 ,0xC200 ,Normal ,OpDissCFS,"mov.l R0,@(,GBR)" ,1,1,LS,fix_none}, // mov.l R0,@(,GBR) {rec_shil_i1100_0011_iiii_iiii ,i1100_0011_iiii_iiii ,Mask_imm8 ,0xC300 ,ReadWritePC ,OpDissCFS,"trapa #" ,7,7,CO,fix_none}, // trapa # {rec_shil_i1100_0100_iiii_iiii ,i1100_0100_iiii_iiii ,Mask_imm8 ,0xC400 ,Normal ,OpDissCFS,"mov.b @(),R0" ,1,2,LS,fix_none}, // mov.b @(,GBR),R0 {rec_shil_i1100_0101_iiii_iiii ,i1100_0101_iiii_iiii ,Mask_imm8 ,0xC500 ,Normal ,OpDissCFS,"mov.w @(),R0" ,1,2,LS,fix_none}, // mov.w @(,GBR),R0 {rec_shil_i1100_0110_iiii_iiii ,i1100_0110_iiii_iiii ,Mask_imm8 ,0xC600 ,Normal ,OpDissCFS,"mov.l @(),R0" ,1,2,LS,fix_none}, // mov.l @(,GBR),R0 {rec_shil_i1100_0111_iiii_iiii ,i1100_0111_iiii_iiii ,Mask_imm8 ,0xC700 ,ReadsPC ,OpDissCFS,"mova @(),R0" ,1,1,EX,fix_none}, // mova @(,PC),R0 {rec_shil_i1100_1000_iiii_iiii ,i1100_1000_iiii_iiii ,Mask_imm8 ,0xC800 ,Normal ,OpDissCFS,"tst #,R0" ,1,1,MT,fix_none}, // tst #,R0 {rec_shil_i1100_1001_iiii_iiii ,i1100_1001_iiii_iiii ,Mask_imm8 ,0xC900 ,Normal ,OpDissCFS,"and #,R0" ,1,1,EX,fix_none}, // and #,R0 {rec_shil_i1100_1010_iiii_iiii ,i1100_1010_iiii_iiii ,Mask_imm8 ,0xCA00 ,Normal ,OpDissCFS,"xor #,R0" ,1,1,EX,fix_none}, // xor #,R0 {rec_shil_i1100_1011_iiii_iiii ,i1100_1011_iiii_iiii ,Mask_imm8 ,0xCB00 ,Normal ,OpDissCFS,"or #,R0" ,1,1,EX,fix_none}, // or #,R0 {rec_shil_i1100_1100_iiii_iiii ,i1100_1100_iiii_iiii ,Mask_imm8 ,0xCC00 ,Normal ,OpDissCFS,"tst.b #,@(R0,GBR)" ,3,3,CO,fix_none}, // tst.b #,@(R0,GBR) {rec_shil_i1100_1101_iiii_iiii ,i1100_1101_iiii_iiii ,Mask_imm8 ,0xCD00 ,Normal ,OpDissCFS,"and.b #,@(R0,GBR)" ,4,4,CO,fix_none}, // and.b #,@(R0,GBR) {rec_shil_i1100_1110_iiii_iiii ,i1100_1110_iiii_iiii ,Mask_imm8 ,0xCE00 ,Normal ,OpDissCFS,"xor.b #,@(R0,GBR)" ,4,4,CO,fix_none}, // xor.b #,@(R0,GBR) {rec_shil_i1100_1111_iiii_iiii ,i1100_1111_iiii_iiii ,Mask_imm8 ,0xCF00 ,Normal ,OpDissCFS,"or.b #,@(R0,GBR)" ,4,4,CO,fix_none}, // or.b #,@(R0,GBR) {rec_shil_i1101_nnnn_iiii_iiii ,i1101_nnnn_iiii_iiii ,Mask_n_imm8,0xD000 ,ReadsPC ,OpDissCFS,"mov.l @()," ,1,2,CO,fix_none}, // mov.l @(,PC), {rec_shil_i1110_nnnn_iiii_iiii ,i1110_nnnn_iiii_iiii ,Mask_n_imm8,0xE000 ,Normal ,OpDissCFS,"mov #," ,1,1,EX,fix_none}, // mov #, //and here are the new ones :D {rec_shil_i1111_nnnn_mmmm_0000 ,i1111_nnnn_mmmm_0000 ,Mask_n_m ,0xF000,Normal ,d1111_nnnn_mmmm_0000,"" ,1,3,FE,fix_none}, //fadd , {rec_shil_i1111_nnnn_mmmm_0001 ,i1111_nnnn_mmmm_0001 ,Mask_n_m ,0xF001,Normal ,d1111_nnnn_mmmm_0001,"" ,1,3,FE,fix_none}, //fsub , {rec_shil_i1111_nnnn_mmmm_0010 ,i1111_nnnn_mmmm_0010 ,Mask_n_m ,0xF002,Normal ,d1111_nnnn_mmmm_0010,"" ,1,3,FE,fix_none}, //fmul , {rec_shil_i1111_nnnn_mmmm_0011 ,i1111_nnnn_mmmm_0011 ,Mask_n_m ,0xF003,Normal ,d1111_nnnn_mmmm_0011,"" ,1,12,FE,fix_none},//fdiv , {rec_shil_i1111_nnnn_mmmm_0100 ,i1111_nnnn_mmmm_0100 ,Mask_n_m ,0xF004,Normal ,d1111_nnnn_mmmm_0100,"" ,1,4,FE,fix_none}, //fcmp/eq , {rec_shil_i1111_nnnn_mmmm_0101 ,i1111_nnnn_mmmm_0101 ,Mask_n_m ,0xF005,Normal ,d1111_nnnn_mmmm_0101,"" ,1,4,FE,fix_none}, //fcmp/gt , {rec_shil_i1111_nnnn_mmmm_0110 ,i1111_nnnn_mmmm_0110 ,Mask_n_m ,0xF006,Normal ,d1111_nnnn_mmmm_0110,"" ,1,2,LS,fix_none}, //fmov.s @(R0,), {rec_shil_i1111_nnnn_mmmm_0111 ,i1111_nnnn_mmmm_0111 ,Mask_n_m ,0xF007,Normal ,d1111_nnnn_mmmm_0111,"" ,1,1,LS,fix_none}, //fmov.s ,@(R0,) {rec_shil_i1111_nnnn_mmmm_1000 ,i1111_nnnn_mmmm_1000 ,Mask_n_m ,0xF008,Normal ,d1111_nnnn_mmmm_1000,"" ,1,2,LS,fix_none}, //fmov.s @, {rec_shil_i1111_nnnn_mmmm_1001 ,i1111_nnnn_mmmm_1001 ,Mask_n_m ,0xF009,Normal ,d1111_nnnn_mmmm_1001,"" ,1,2,LS,fix_none}, //fmov.s @+, {rec_shil_i1111_nnnn_mmmm_1010 ,i1111_nnnn_mmmm_1010 ,Mask_n_m ,0xF00A,Normal ,d1111_nnnn_mmmm_1010,"" ,1,1,LS,fix_none}, //fmov.s ,@ {rec_shil_i1111_nnnn_mmmm_1011 ,i1111_nnnn_mmmm_1011 ,Mask_n_m ,0xF00B,Normal ,d1111_nnnn_mmmm_1011,"" ,1,1,LS,rn_fpu_4}, //fmov.s ,@- {rec_shil_i1111_nnnn_mmmm_1100 ,i1111_nnnn_mmmm_1100 ,Mask_n_m ,0xF00C,Normal ,d1111_nnnn_mmmm_1100,"" ,1,0,LS,fix_none}, //fmov , {rec_shil_i1111_nnnn_0101_1101 ,i1111_nnnn_0101_1101 ,Mask_n ,0xF05D,Normal ,d1111_nnnn_0101_1101,"" ,1,0,LS,fix_none}, //fabs {rec_shil_i1111_nnn0_1111_1101 ,i1111_nnn0_1111_1101 ,Mask_nh3bit ,0xF0FD,Normal ,OpDissFSCA ,"" ,1,4,FE,fix_none}, //FSCA FPUL, DRn//F0FD//1111_nnnn_1111_1101 {rec_shil_i1111_nnnn_1011_1101 ,i1111_nnnn_1011_1101 ,Mask_n ,0xF0BD,Normal ,d1111_nnnn_1011_1101,"" ,1,4,FE,fix_none}, //fcnvds ,FPUL {rec_shil_i1111_nnnn_1010_1101 ,i1111_nnnn_1010_1101 ,Mask_n ,0xF0AD,Normal ,d1111_nnnn_1010_1101,"" ,1,4,FE,fix_none}, //fcnvsd FPUL, {rec_shil_i1111_nnmm_1110_1101 ,i1111_nnmm_1110_1101 ,Mask_n ,0xF0ED,Normal ,OpDissfipr ,"" ,1,4,FE,fix_none}, //fipr , {rec_shil_i1111_nnnn_1000_1101 ,i1111_nnnn_1000_1101 ,Mask_n ,0xF08D,Normal ,d1111_nnnn_1000_1101,"" ,1,0,LS,fix_none}, //fldi0 {rec_shil_i1111_nnnn_1001_1101 ,i1111_nnnn_1001_1101 ,Mask_n ,0xF09D,Normal ,d1111_nnnn_1001_1101,"" ,1,0,LS,fix_none}, //fldi1 {rec_shil_i1111_nnnn_0001_1101 ,i1111_nnnn_0001_1101 ,Mask_n ,0xF01D,Normal ,d1111_nnnn_0001_1101,"" ,1,0,LS,fix_none}, //flds ,FPUL {rec_shil_i1111_nnnn_0010_1101 ,i1111_nnnn_0010_1101 ,Mask_n ,0xF02D,Normal ,d1111_nnnn_0010_1101,"" ,1,3,FE,fix_none}, //float FPUL, {rec_shil_i1111_nnnn_0100_1101 ,i1111_nnnn_0100_1101 ,Mask_n ,0xF04D,Normal ,d1111_nnnn_0100_1101,"" ,1,0,LS,fix_none}, //fneg {rec_shil_i1111_1011_1111_1101 ,i1111_1011_1111_1101 ,Mask_none ,0xFBFD,WritesFPSCR ,OpDissCFS,"frchg" ,1,2,FE,fix_none}, //frchg {rec_shil_i1111_0011_1111_1101 ,i1111_0011_1111_1101 ,Mask_none ,0xF3FD,WritesFPSCR ,OpDissCFS,"fschg" ,1,2,FE,fix_none}, //fschg {rec_shil_i1111_nnnn_0110_1101 ,i1111_nnnn_0110_1101 ,Mask_n ,0xF06D,Normal ,d1111_nnnn_0110_1101,"" ,1,12,FE,fix_none},//fsqrt {rec_shil_i1111_nnnn_0011_1101 ,i1111_nnnn_0011_1101 ,Mask_n ,0xF03D,Normal ,d1111_nnnn_0011_1101,"" ,1,4,FE,fix_none}, //ftrc , FPUL {rec_shil_i1111_nnnn_0000_1101 ,i1111_nnnn_0000_1101 ,Mask_n ,0xF00D,Normal ,d1111_nnnn_0000_1101,"" ,1,0,LS,fix_none}, //fsts FPUL, {rec_shil_i1111_nn01_1111_1101 ,i1111_nn01_1111_1101 ,Mask_nh2bit ,0xF1FD,Normal ,OpDissftrv ,"" ,1,6,FE,fix_none}, //ftrv xmtrx, {rec_shil_i1111_nnnn_mmmm_1110 ,i1111_nnnn_mmmm_1110 ,Mask_n_m ,0xF00E,Normal ,OpDissfmac ,"" ,1,4,FE,fix_none}, //fmac ,, {rec_shil_i1111_nnnn_0111_1101 ,i1111_nnnn_0111_1101 ,Mask_n ,0xF07D,Normal ,d1111_nnnn_0111_1101,"" ,1,4,FE,fix_none}, //FSRRA (1111nnnn 01111101) //HLE ops {0 ,gdrom_hle_op ,Mask_none ,GDROM_OPCODE,ReadWritePC ,dissasm_GDROM}, {rec_shil_sh4_bpt_op ,sh4_bpt_op ,Mask_none ,BPT_OPCODE ,ReadWritePC ,dissasm_Break}, //end of list {0,0,0,0,ReadWritePC}//Branch in order to stop the block and save pc ect :) }; bool bBuilded=false; void BuildOpcodeTables() { if (bBuilded) return; u32 fpu_unh=0; u32 cpu_unh=0; bBuilded=true; for (int i=0;i<0x10000;i++) { OpPtr[i]=iNotImplemented;// (OpCallFP*)0; OpTyp[i]=Invalid; RecOpPtr[i]=rec_shil_icpu_nimp; for (int i2=0;opcodes[i2].oph;i2++) { if ((i&opcodes[i2].mask)==opcodes[i2].rez) { if (OpTyp[i]==Invalid) { OpPtr[i]=opcodes[i2].oph; RecOpPtr[i]=opcodes[i2].rec_oph; //if (((i&0xF00F)>0x4006) && ((i&0xF00F)<0x400F) )//0x9739 //if ( ((i&0xF0FF)==0x400E) || ((i&0xF0FF)==0x4007) ) //RecOpPtr[i]=rec_cpu_opcode_nimp; OpTyp[i]=opcodes[i2].type; OpDesc[i]=&opcodes[i2]; if (OpDesc[i]->dissasm==0) OpDesc[i]->dissasm=OpNoDiss; } else { dlog("OPCODE TABLE FAULT , DOUBLE DEFINED OPCODE\n"); } } } } u32 cpu_count; for (cpu_count=0;opcodes[cpu_count].oph;cpu_count++) { if (rec_shil_icpu_nimp==opcodes[cpu_count].rec_oph) { cpu_unh++; } } cpu_unh = (cpu_count-31)-cpu_unh; fpu_unh = 31-fpu_unh; dlog("shil generation status : %d%% cpu done[%d of %d] , %d%% fpu done[%d of %d]\n", cpu_unh*100/(cpu_count-31),cpu_unh,(cpu_count-31) ,fpu_unh*100/31 ,fpu_unh,31); } void DissasembleOpcode(u16 opcode,u32 pc,char* Dissasm) { if (!bBuilded) BuildOpcodeTables(); if (OpDesc[opcode]!=0) { OpDesc[opcode]->Dissasemble(Dissasm,pc,opcode); } else { sprintf(Dissasm,"unknown Opcode 0x%X",opcode); } }