102 commits

Author	SHA1	Message	Date
GliGli	a181694f25	little bugfix	2011-11-28 01:16:55 +01:00
GliGli	b11fc036f9	multithreaded TA Dma, fixes a bios bug, small speedup	2011-11-27 22:56:34 +01:00
GliGli	bbea6e9888	more threaded pvr stuff	2011-11-26 23:08:24 +01:00
GliGli	8d08f766c9	threaded pvr + pref opti	2011-11-26 19:37:55 +01:00
GliGli	4d3563b574	adding pref profiling	2011-11-26 00:39:49 +01:00
GliGli	d139e0f3f4	opti: generate fpu ftrv code, faster than altivec function call	2011-11-25 23:39:32 +01:00
GliGli	916f5d6d83	#define for regs profiling	2011-11-25 23:38:19 +01:00
GliGli	dab0609c1e	another readm / writem opti	2011-11-25 22:17:51 +01:00
GliGli	81e523db81	opti: removing 1 op for each readm / writem	2011-11-25 20:58:55 +01:00
GliGli	9c7f60c509	dynarec reads/writes/float movs optis	2011-11-25 01:23:26 +01:00
GliGli	ddf67f1e93	dynarec blocks invalidation opti	2011-11-24 22:12:19 +01:00
GliGli	1e65abbb64	major opti: using a dedicated ppc register for sh4 pc	2011-11-24 01:22:11 +01:00
GliGli	be9116a163	little branch opti	2011-11-23 20:35:53 +01:00
GliGli	1068b5b4e3	jumps/branches opti + fsrra opti	2011-11-23 19:58:16 +01:00
GliGli	3743e8897e	temp (unsafe?) optis	2011-11-22 20:09:07 +01:00
GliGli	29cc438256	added some profiling infos + moved 3d rendering to UpdateSystem	2011-11-21 22:27:41 +01:00
GliGli	7ddfd6c582	int reg allocator optimisations	2011-11-21 20:24:32 +01:00
GliGli	5fb759b8a9	fix mulls from unallocated reg	2011-11-20 20:43:24 +01:00
GliGli	567c2abe10	all shil ops except div are recompiled	2011-11-20 17:45:33 +01:00
GliGli	439aee1451	2 more recompiled ops	2011-11-19 21:48:02 +01:00
GliGli	10b7941e9f	recompiled integer mulls & swaps	2011-11-19 19:24:17 +01:00
GliGli	d2f2ca63af	dynarec bugfix for bios	2011-11-19 17:06:27 +01:00
GliGli	f12ed12919	working dynarec SQ write opti	2011-11-19 16:21:48 +01:00
GliGli	0b07114803	bugfix, soucalibur is working on dynarec :)	2011-11-19 11:54:30 +01:00
GliGli	98d834d687	dynarec bugfixes	2011-11-19 00:28:07 +01:00
GliGli	bb7eb6d2c6	bugfixes & more recompiled ops	2011-11-18 22:35:56 +01:00
GliGli	ecb3017bd6	bugfixes & optis	2011-11-18 20:45:25 +01:00
GliGli	51109bb3cb	misc changes	2011-11-17 20:12:13 +01:00
GliGli	01c0ddef4c	working dr blocks invalidation	2011-11-13 00:33:25 +01:00
GliGli	442fd87ee9	working shil CE optimiser	2011-11-12 15:29:51 +01:00
GliGli	8eae90dd62	wip	2011-11-11 19:17:58 +01:00
GliGli	d7a740913b	misc dynarec shift stuff	2011-11-10 00:28:53 +01:00
GliGli	3b0341ef40	dynarec load/store opti	2011-11-09 23:28:41 +01:00
GliGli	e9045122f2	misc optis	2011-11-09 17:22:14 +01:00
GliGli	15b795dc79	opti: ASM UpdateINTC	2011-11-09 15:52:08 +01:00
GliGli	227d2d5d1b	misc dynarec optis	2011-11-09 14:52:18 +01:00
GliGli	7b31920aa0	little branchs opti	2011-11-09 12:30:59 +01:00
GliGli	8a627e5efd	round of optimisations	2011-11-09 10:21:52 +01:00
GliGli	f8166927a4	more remcompiled FPU ops	2011-11-08 19:55:17 +01:00
GliGli	f3c0b7eb7a	opti: use CR bit to emulate T flag	2011-11-08 16:47:29 +01:00
GliGli	6bf875db91	implemented simple FPU ops	2011-11-08 12:51:31 +01:00
GliGli	3688b01bc0	implemented dynarec saves and a bunch of missed ops / shil_ifp profiler	2011-11-08 11:26:14 +01:00
GliGli	701128d0c7	implemented dynarec reads (speedup!) / more linux compilation fixes by warfaren	2011-11-07 22:01:19 +01:00
GliGli	fc0363b391	opti to generate less code	2011-11-05 21:14:22 +01:00
GliGli	f401c9dcbe	even more recompiled ops	2011-11-05 20:44:43 +01:00
GliGli	7cf10db31e	more recompiled ops	2011-11-05 13:06:02 +01:00
GliGli	d21ac5b50a	generate better code / print less log	2011-11-04 18:13:41 +01:00
GliGli	33c2ad49f4	(slowly) working dynarec	2011-11-04 17:39:36 +01:00
GliGli	c2d01d5087	more preliminary dynarec work	2011-10-16 16:07:40 +02:00
GliGli	b5b882fee6	preliminary work on dynarec + compilation fixes for linux from warfaren	2011-10-16 14:34:06 +02:00