38 commits

Author	SHA1	Message	Date
GliGli	5a71129af8	gui working with dynarec / cleanups	2012-09-09 18:16:36 +02:00
GliGli	62d03c2a9c	emitter opti epic fail, corrupted memory, wasted a PPC reg and wasn't any usefull / using that reg for SH4 PR, actually much faster, and safer :)	2012-09-08 18:36:50 +02:00
GliGli	d34106896e	dynarec blocks opti / removing failed ret opti / cleanups	2012-09-06 20:33:32 +02:00
GliGli	0deaa0899c	using altivec for SH4 matrix ops / various cleanups / threaded pvr refinements	2012-09-04 20:12:55 +02:00
GliGli	501c222883	new dynarec SQ writes handling method / various cleanups	2012-09-01 22:56:59 +02:00
GliGli	ed1c592b9f	lto working again / threaded pvr improvements / cleanups	2012-08-31 00:33:46 +02:00
GliGli	ab83a08f91	floating point reg allocator opti	2012-02-25 23:21:09 +01:00
GliGli	51a5ddb345	tiny emitter opti	2012-02-25 01:05:30 +01:00
GliGli	f978fa4856	various optis, maybe unsafe	2012-02-22 20:10:06 +01:00
GliGli	ebb84d9396	removing risky and useless opti / cleanup	2011-12-08 21:04:02 +01:00
GliGli	751a03257f	fully working shil ce optimiser	2011-12-05 22:56:08 +01:00
GliGli	df4c919502	wip (one new recompiled op + shil ifb opti)	2011-12-04 18:16:00 +01:00
GliGli	d139e0f3f4	opti: generate fpu ftrv code, faster than altivec function call	2011-11-25 23:39:32 +01:00
GliGli	9c7f60c509	dynarec reads/writes/float movs optis	2011-11-25 01:23:26 +01:00
GliGli	1e65abbb64	major opti: using a dedicated ppc register for sh4 pc	2011-11-24 01:22:11 +01:00
GliGli	1068b5b4e3	jumps/branches opti + fsrra opti	2011-11-23 19:58:16 +01:00
GliGli	3743e8897e	temp (unsafe?) optis	2011-11-22 20:09:07 +01:00
GliGli	7ddfd6c582	int reg allocator optimisations	2011-11-21 20:24:32 +01:00
GliGli	567c2abe10	all shil ops except div are recompiled	2011-11-20 17:45:33 +01:00
GliGli	439aee1451	2 more recompiled ops	2011-11-19 21:48:02 +01:00
GliGli	98d834d687	dynarec bugfixes	2011-11-19 00:28:07 +01:00
GliGli	ecb3017bd6	bugfixes & optis	2011-11-18 20:45:25 +01:00
GliGli	51109bb3cb	misc changes	2011-11-17 20:12:13 +01:00
GliGli	442fd87ee9	working shil CE optimiser	2011-11-12 15:29:51 +01:00
GliGli	8eae90dd62	wip	2011-11-11 19:17:58 +01:00
GliGli	3b0341ef40	dynarec load/store opti	2011-11-09 23:28:41 +01:00
GliGli	7b31920aa0	little branchs opti	2011-11-09 12:30:59 +01:00
GliGli	8a627e5efd	round of optimisations	2011-11-09 10:21:52 +01:00
GliGli	f8166927a4	more remcompiled FPU ops	2011-11-08 19:55:17 +01:00
GliGli	f3c0b7eb7a	opti: use CR bit to emulate T flag	2011-11-08 16:47:29 +01:00
GliGli	6bf875db91	implemented simple FPU ops	2011-11-08 12:51:31 +01:00
GliGli	701128d0c7	implemented dynarec reads (speedup!) / more linux compilation fixes by warfaren	2011-11-07 22:01:19 +01:00
GliGli	fc0363b391	opti to generate less code	2011-11-05 21:14:22 +01:00
GliGli	f401c9dcbe	even more recompiled ops	2011-11-05 20:44:43 +01:00
GliGli	7cf10db31e	more recompiled ops	2011-11-05 13:06:02 +01:00
GliGli	d21ac5b50a	generate better code / print less log	2011-11-04 18:13:41 +01:00
GliGli	33c2ad49f4	(slowly) working dynarec	2011-11-04 17:39:36 +01:00
GliGli	b5b882fee6	preliminary work on dynarec + compilation fixes for linux from warfaren	2011-10-16 14:34:06 +02:00