From dcefef20acaf343542184f4a76c3743cc518d071 Mon Sep 17 00:00:00 2001 From: rkx1209 Date: Fri, 8 Jun 2018 02:27:32 +0900 Subject: [PATCH] Add 128bit FP register support --- ARMv8/Interpreter.cpp | 15 ++++++++++++++- GdbStub.cpp | 4 ---- Svc.cpp | 2 +- 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/ARMv8/Interpreter.cpp b/ARMv8/Interpreter.cpp index 71690c1..15f7051 100644 --- a/ARMv8/Interpreter.cpp +++ b/ARMv8/Interpreter.cpp @@ -20,7 +20,7 @@ int Interpreter::SingleStep() { void Interpreter::Run() { debug_print ("Running with Interpreter\n"); static uint64_t counter = 0; - uint64_t estimate = 3500000, mx = 10000; + uint64_t estimate = 3500000, mx = 15000; //uint64_t estimate = 0, mx = 100000; while (Cpu::GetState () == Cpu::State::Running) { if (GdbStub::enabled) { @@ -681,6 +681,8 @@ void IntprCallback::LoadVecReg(unsigned int vd_idx, int element, unsigned int rn VREG(vd_idx).s[element] = ARMv8::ReadU32 (addr); } else if (size == 3) { // 8byte (1D/2D) VREG(vd_idx).d[element] = ARMv8::ReadU64 (addr); + } else { + ns_abort ("Unknown size\n"); } } void IntprCallback::StoreVecReg(unsigned int rd_idx, int element, unsigned int vn_idx, int size) { @@ -694,6 +696,8 @@ void IntprCallback::StoreVecReg(unsigned int rd_idx, int element, unsigned int v ARMv8::WriteU32 (addr, VREG(vn_idx).s[element]); } else if (size == 3) { ARMv8::WriteU64 (addr, VREG(vn_idx).d[element]); + } else { + ns_abort ("Unknown size\n"); } } @@ -709,6 +713,11 @@ void IntprCallback::LoadFpRegI64(unsigned int fd_idx, unsigned int ad_idx, int s S(fd_idx) = ARMv8::ReadU32 (addr); } else if (size == 3) { D(fd_idx) = ARMv8::ReadU64 (addr); + } else { + /* 128-bit Qt */ + VREG(fd_idx).d[0] = ARMv8::ReadU64 (addr + 8); + VREG(fd_idx).d[1] = ARMv8::ReadU64 (addr); + //ns_debug("Read: Q = 0x%lx, 0x%lx\n", VREG(rd_idx).d[0], VREG(rd_idx).d[1]); } } void IntprCallback::StoreFpRegI64(unsigned int fd_idx, unsigned int ad_idx, int size) { @@ -722,6 +731,10 @@ void IntprCallback::StoreFpRegI64(unsigned int fd_idx, unsigned int ad_idx, int ARMv8::WriteU32 (addr, S(fd_idx)); } else if (size == 3) { ARMv8::WriteU64 (addr, D(fd_idx)); + } else if (size == 4) { + /* 128-bit Qt */ + ARMv8::WriteU64 (addr + 8, VREG(fd_idx).d[0]); + ARMv8::WriteU64 (addr, VREG(fd_idx).d[1]); } } diff --git a/GdbStub.cpp b/GdbStub.cpp index e6206ea..f896fcf 100644 --- a/GdbStub.cpp +++ b/GdbStub.cpp @@ -138,7 +138,6 @@ static int IsQueryPacket (const char *p, const char *query, char separator) } static int TargetMemoryRW(uint64_t addr, uint8_t *buf, int len, bool is_write) { - ns_print("[%s] addr 0x%016lx(%d byte)\n", (is_write?"WRITE":"READ"), addr, len); if ((int64_t)addr < 0) { return -1; //FIXME: Correct validation is required } @@ -253,7 +252,6 @@ void NotifyMemAccess(unsigned long addr, size_t len, bool read) { Watchpoint wp = wp_list[i]; if (addr <= wp.addr && wp.addr + wp.len <= addr + len) { if (wp.type == GDB_WATCHPOINT_ACCESS || wp.type == type) { - ns_print("Hit watchpoint 0x%lx, %d, %s (PC:0x%lx)\n", addr, len, (read ? "read" : "write"), PC); HitWatchpoint (addr, wp.type); return; } @@ -306,8 +304,6 @@ static RSState HandleCommand(char *line_buf) { uint8_t mem_buf[GDB_BUFFER_SIZE]; unsigned long addr, len; - ns_print("command='%s'\n", line_buf); - p = line_buf; ch = *p++; switch(ch) { diff --git a/Svc.cpp b/Svc.cpp index c1beb6e..f20ac79 100644 --- a/Svc.cpp +++ b/Svc.cpp @@ -288,7 +288,7 @@ std::tuple ConnectToPort(uint64_t name) { } uint64_t SendSyncRequest(uint32_t handle) { - ns_print("SendSyncRequest\n"); + ns_print("SendSyncRequest 0x%x\n", handle); uint8_t msgbuf[0x100]; ARMv8::ReadBytes (ARMv8::GetTls(), msgbuf, 0x100); auto handler = IPC::GetHandle(handle);