mirror of
https://github.com/RKX1209/nsemu.git
synced 2024-06-23 14:43:16 -04:00
Add support for load/store operation with 128bit register(FP)
This commit is contained in:
rkx1209
parent
3679e913a5
commit
adde42797b
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@ -10,6 +10,11 @@ static inline void UnallocatedOp(uint32_t insn) {
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ns_abort ("Unallocated operation 0x%08lx\n", insn);
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}
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static inline bool FpAccessCheck(uint32_t insn) {
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/* TODO: */
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return true;
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}
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static bool LogicImmDecode(uint64_t *wmask, unsigned int immn, unsigned int imms, unsigned int immr) {
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assert (immn < 2 && imms < 64 && immr < 64);
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uint64_t mask;
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@ -863,7 +868,16 @@ static void DisasLdstRegUnsignedImm(uint32_t insn, DisasCallback *cb,
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bool is_extended = false;
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if (is_vector) {
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UnsupportedOp ("LDR/STR [base, #simm12] (SIMD&FP)");
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/* LDR/STR [base, #simm12] (SIMD&FP) */
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size |= (opc & 2) << 1;
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if (size > 4) {
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UnallocatedOp (insn);
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return;
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}
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is_store = !extract32(opc, 0, 1);
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if (!FpAccessCheck (insn)) {
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return;
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}
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} else {
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if (size == 3 && opc == 2) {
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/* PRFM - prefetch */
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@ -877,12 +891,21 @@ static void DisasLdstRegUnsignedImm(uint32_t insn, DisasCallback *cb,
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is_signed = extract32(opc, 1, 1);
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is_extended = (size < 3) && extract32(opc, 0, 1);
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}
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bool sf = DisasLdstCompute64bit (size, is_signed, opc);
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offset = imm12 << size;
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if (is_store) {
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cb->StoreRegImm64 (rt, rn, offset, size, is_extended, false, false, sf);
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if (is_vector) {
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/* size must be 4 (128-bit) */
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if (is_store) {
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cb->StoreRegImm64 (rt, rn, offset, size, false, false, false, true);
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} else {
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cb->LoadRegImm64 (rt, rn, offset, size, false, false, false, true);
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}
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} else {
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cb->LoadRegImm64 (rt, rn, offset, size, is_extended, false, false, sf);
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bool sf = DisasLdstCompute64bit (size, is_signed, opc);
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if (is_store) {
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cb->StoreRegImm64 (rt, rn, offset, size, is_extended, false, false, sf);
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} else {
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cb->LoadRegImm64 (rt, rn, offset, size, is_extended, false, false, sf);
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}
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}
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}
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@ -346,49 +346,43 @@ void IntprCallback::ExtendReg(unsigned int rd_idx, unsigned int rn_idx, unsigned
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}
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/* Load/Store */
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static void _LoadReg(unsigned int rd_idx, uint64_t addr, int size, bool extend, bool bit64) {
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if (bit64) {
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if (size == 4)
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W(rd_idx) = ARMv8::ReadU32 (addr);
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if (size == 8)
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X(rd_idx) = ARMv8::ReadU64 (addr);
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/* TODO: if (extend)
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ExtendReg(rd_idx, rd_idx, type, true); */
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} else {
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if (size == 4)
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W(rd_idx) = ARMv8::ReadU32 (addr);
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/* TODO: if (extend)
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ExtendReg(rd_idx, rd_idx, type, true); */
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}
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static void _LoadReg(unsigned int rd_idx, uint64_t addr, int size, bool extend) {
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if (size < 4) {
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X(rd_idx) = ARMv8::ReadU64 (addr);
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} else {
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/* 128-bit Qt */
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VREG(rd_idx).d[0] = ARMv8::ReadU64 (addr + 8);
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VREG(rd_idx).d[1] = ARMv8::ReadU64 (addr);
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}
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/* TODO: if (extend)
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ExtendReg(rd_idx, rd_idx, type, true); */
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}
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static void _StoreReg(unsigned int rd_idx, uint64_t addr, int size, bool extend, bool bit64) {
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if (bit64) {
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if (size == 4)
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ARMv8::WriteU32 (addr, X(rd_idx));
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if (size == 8)
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ARMv8::WriteU64 (addr, X(rd_idx));
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/* TODO: if (extend)
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ExtendReg(rd_idx, rd_idx, type, true); */
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} else {
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if (size == 4)
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ARMv8::WriteU32 (addr, W(rd_idx));
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/* TODO: if (extend)
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ExtendReg(rd_idx, rd_idx, type, true); */
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}
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static void _StoreReg(unsigned int rd_idx, uint64_t addr, int size, bool extend) {
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if (size < 4) {
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ARMv8::WriteU64 (addr, X(rd_idx));
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} else {
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/* 128-bit Qt */
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ARMv8::WriteU64 (addr + 8, VREG(rd_idx).d[0]);
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ARMv8::WriteU64 (addr, VREG(rd_idx).d[1]);
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}
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/* TODO: if (extend)
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ExtendReg(rd_idx, rd_idx, type, true); */
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}
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void IntprCallback::LoadReg(unsigned int rd_idx, unsigned int base_idx, unsigned int rm_idx, int size,
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bool extend, bool post, bool writeback, bool bit64) {
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char regc = bit64? 'X': 'W';
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debug_print ("Load(%d): %c[%u] <= [%c[%u], %c[%u]]\n", size, regc, rd_idx, regc, base_idx, regc, rm_idx);
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char regdc = bit64 && size >= 4 ? 'Q' : regc;
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debug_print ("Load(%d): %c[%u] <= [%c[%u], %c[%u]]\n", size, regdc, rd_idx, regc, base_idx, regc, rm_idx);
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uint64_t addr;
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if (bit64) {
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if (post)
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addr = X(base_idx);
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else
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addr = X(base_idx) + X(rm_idx);
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_LoadReg (rd_idx, addr, size, extend, true);
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_LoadReg (rd_idx, addr, size, extend);
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if (writeback)
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X(base_idx) = addr;
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} else {
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@ -396,7 +390,7 @@ void IntprCallback::LoadReg(unsigned int rd_idx, unsigned int base_idx, unsigned
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addr = W(base_idx);
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else
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addr = W(base_idx) + W(rm_idx);
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_LoadReg (rd_idx, addr, size, extend, false);
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_LoadReg (rd_idx, addr, size, extend);
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if (writeback)
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W(base_idx) = addr;
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}
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@ -404,14 +398,15 @@ void IntprCallback::LoadReg(unsigned int rd_idx, unsigned int base_idx, unsigned
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void IntprCallback::LoadRegImm64(unsigned int rd_idx, unsigned int base_idx, uint64_t offset, int size,
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bool extend, bool post, bool writeback, bool bit64) {
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char regc = bit64? 'X': 'W';
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debug_print ("Load(%d): %c[%u] <= [%c[%u], 0x%lx]\n", size, regc, rd_idx, regc, base_idx, offset);
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char regdc = bit64 && size >= 4 ? 'Q' : regc;
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debug_print ("Load(%d): %c[%u] <= [%c[%u], 0x%lx]\n", size, regdc, rd_idx, regc, base_idx, offset);
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uint64_t addr;
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if (bit64) {
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if (post)
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addr = X(base_idx);
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else
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addr = X(base_idx) + offset;
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_LoadReg (rd_idx, addr, size, extend, true);
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_LoadReg (rd_idx, addr, size, extend);
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if (writeback)
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X(base_idx) = addr;
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} else {
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@ -419,7 +414,7 @@ void IntprCallback::LoadRegImm64(unsigned int rd_idx, unsigned int base_idx, uin
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addr = W(base_idx);
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else
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addr = W(base_idx) + offset;
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_LoadReg (rd_idx, addr, size, extend, false);
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_LoadReg (rd_idx, addr, size, extend);
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if (writeback)
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W(base_idx) = addr;
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}
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@ -427,14 +422,15 @@ void IntprCallback::LoadRegImm64(unsigned int rd_idx, unsigned int base_idx, uin
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void IntprCallback::StoreReg(unsigned int rd_idx, unsigned int base_idx, unsigned int rm_idx, int size,
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bool extend, bool post, bool writeback, bool bit64) {
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char regc = bit64? 'X': 'W';
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debug_print ("Store(%d): %c[%u] => [%c[%u], %c[%u]]\n", size, regc, rd_idx, regc, base_idx, regc, rm_idx);
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char regdc = bit64 && size >= 4 ? 'Q' : regc;
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debug_print ("Store(%d): %c[%u] => [%c[%u], %c[%u]]\n", size, regdc, rd_idx, regc, base_idx, regc, rm_idx);
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uint64_t addr;
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if (bit64) {
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if (post)
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addr = X(base_idx);
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else
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addr = X(base_idx) + X(rm_idx);
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_StoreReg (rd_idx, addr, size, extend, true);
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_StoreReg (rd_idx, addr, size, extend);
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if (writeback)
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X(base_idx) = addr;
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} else {
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@ -442,7 +438,7 @@ void IntprCallback::StoreReg(unsigned int rd_idx, unsigned int base_idx, unsigne
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addr = W(base_idx);
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else
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addr = W(base_idx) + W(rm_idx);
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_StoreReg (rd_idx, addr, size, extend, false);
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_StoreReg (rd_idx, addr, size, extend);
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if (writeback)
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W(base_idx) = addr;
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}
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@ -450,14 +446,15 @@ void IntprCallback::StoreReg(unsigned int rd_idx, unsigned int base_idx, unsigne
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void IntprCallback::StoreRegImm64(unsigned int rd_idx, unsigned int base_idx, uint64_t offset, int size,
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bool extend, bool post, bool writeback, bool bit64) {
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char regc = bit64? 'X': 'W';
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debug_print ("Store(%d): %c[%u] => [%c[%u], 0x%lx]\n", size, regc, rd_idx, regc, base_idx, offset);
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char regdc = bit64 && size >= 4 ? 'Q' : regc;
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debug_print ("Store(%d): %c[%u] => [%c[%u], 0x%lx]\n", size, regdc, rd_idx, regc, base_idx, offset);
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uint64_t addr;
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if (bit64) {
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if (post)
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addr = X(base_idx);
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else
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addr = X(base_idx) + offset;
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_StoreReg (rd_idx, addr, size, extend, true);
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_StoreReg (rd_idx, addr, size, extend);
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if (writeback)
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X(base_idx) = addr;
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} else {
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@ -465,7 +462,7 @@ void IntprCallback::StoreRegImm64(unsigned int rd_idx, unsigned int base_idx, ui
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addr = W(base_idx);
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else
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addr = W(base_idx) + offset;
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_StoreReg (rd_idx, addr, size, extend, false);
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_StoreReg (rd_idx, addr, size, extend);
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if (writeback)
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W(base_idx) = addr;
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}
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@ -8,11 +8,24 @@ typedef union {
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uint64_t x;
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}reg_t;
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/* NEON & FP register */
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typedef union {
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uint8_t b[16];
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uint16_t h[8];
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uint32_t s[4];
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uint64_t d[2];
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}vreg_t;
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struct ARMv8State {
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reg_t gpr[34];
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/*
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* x0 - x31 (x30 is usually "link regsiter" and x31 is "stack pointer" or "zero register" )
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* NOTE: In nsemu, 'PC' register is respresented as x32 internally. */
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* NOTE: In nsemu, 'PC' register is respresented as x32 internally.
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*/
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reg_t gpr[34];
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/* v0 - v31 (128 bit vector register, sometime treated as set of smaller size regs) */
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vreg_t vreg[32];
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uint32_t nzcv; // flag register
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};
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@ -25,8 +38,14 @@ extern ARMv8State arm_state;
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#define GPR_DUMMY 33
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#define GPR(r) ARMv8::arm_state.gpr[r]
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#define VREG(r) ARMv8::arm_state.vreg[r]
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#define X(r) GPR(r).x
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#define W(r) GPR(r).w[1]
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#define W(r) GPR(r).w[0]
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#define D(r) VREG(r).d[0]
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#define S(r) VREG(r).s[0]
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#define H(r) VREG(r).h[0]
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#define B(r) VREG(r).b[0]
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#define LR X(GPR_LR)
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#define SP X(GPR_SP)
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