mirror of
https://github.com/RKX1209/nsemu.git
synced 2024-06-23 06:32:39 -04:00
Add support for load/store operation with register immediate
This commit is contained in:
rkx1209
parent
77e2611ca2
commit
ad2cfdc816
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@ -725,7 +725,7 @@ static void DisasLdLit(uint32_t insn, DisasCallback *cb) {
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size = 2 + extract32(opc, 0, 1);
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is_signed = extract32(opc, 1, 1);
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}
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cb->LoadRegImm64 (rt, PC + imm - 4, size, false, sf);
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cb->LoadRegImm64 (rt, PC_IDX, imm - 4, size, false, false, false, sf);
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}
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static bool DisasLdstCompute64bit(unsigned int size, bool is_signed, unsigned int opc) {
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@ -761,7 +761,7 @@ static void DisasLdstRegRoffset(uint32_t insn, DisasCallback *cb,
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}
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if (is_vector) {
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UnsupportedOp ("LDR/STR (SIMD&FP)");
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UnsupportedOp ("LDR/STR [base, Xm/Wm] (SIMD&FP)");
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} else {
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if (size == 3 && opc == 2) {
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/* PRFM - prefetch */
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@ -778,9 +778,75 @@ static void DisasLdstRegRoffset(uint32_t insn, DisasCallback *cb,
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cb->ExtendReg (rm, rm, opt, sf);
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cb->ShiftReg (rm, rm, ShiftType_LSL, shift ? size : 0, sf);
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if (is_store) {
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cb->StoreReg (rt, rm, size, is_extended, sf);
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cb->StoreReg (rt, rn, rm, size, is_extended, false, false, sf);
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} else {
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cb->LoadReg (rt, rm, size, is_extended, sf);
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cb->LoadReg (rt, rn, rm, size, is_extended, false, false, sf);
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}
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}
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/*
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* Load/store register (unscaled immediate)
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* Load/store immediate pre/post-indexed
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* Load/store register unprivileged
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*/
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static void DisasLdstRegImm9(uint32_t insn, DisasCallback *cb,
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unsigned int opc,
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unsigned int size,
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unsigned int rt,
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bool is_vector) {
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unsigned int rn = extract32(insn, 5, 5);
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unsigned int imm9 = sextract32(insn, 12, 9);
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unsigned int idx = extract32(insn, 10, 2);
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bool is_signed = false;
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bool is_store = false;
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bool is_extended = false;
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bool is_unpriv = (idx == 2);
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bool iss_valid = !is_vector;
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bool post_index;
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bool writeback;
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bool sf = DisasLdstCompute64bit (size, is_signed, opc);
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if (is_vector) {
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UnsupportedOp ("LDR/STR [base, #imm9] (SIMD&FP)");
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} else {
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if (size == 3 && opc == 2) {
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/* PRFM - prefetch */
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if (is_unpriv) {
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UnallocatedOp (insn);
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return;
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}
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return;
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}
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if (opc == 3 && size > 1) {
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UnallocatedOp (insn);
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return;
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}
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is_store = (opc == 0);
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is_signed = extract32(opc, 1, 1);
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is_extended = (size < 3) && extract32(opc, 0, 1);
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}
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switch (idx) {
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case 0:
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case 2:
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post_index = false;
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writeback = false;
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break;
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case 1:
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post_index = true;
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writeback = true;
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break;
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case 3:
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post_index = false;
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writeback = true;
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break;
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default:
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ns_abort ("Unreachable status\n");
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}
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if (is_store) {
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cb->StoreRegImm64 (rt, rn, imm9, size, is_extended, post_index, writeback, sf);
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} else {
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cb->LoadRegImm64 (rt, rn, imm9, size, is_extended, post_index, writeback, sf);
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}
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}
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@ -796,11 +862,12 @@ static void DisasLdstReg(uint32_t insn, DisasCallback *cb) {
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if (extract32(insn, 21, 1) == 1 && extract32(insn, 10, 2) == 2) {
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DisasLdstRegRoffset (insn, cb, opc, size, rt, is_vector);
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} else {
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/* Load/store register (unscaled immediate)
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/*
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* Load/store register (unscaled immediate)
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* Load/store immediate pre/post-indexed
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* Load/store register unprivileged
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*/
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//DisasLdstRegImm9 (insn, cb);
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DisasLdstRegImm9 (insn, cb, opc, size, rt, is_vector);
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}
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break;
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case 1:
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@ -344,23 +344,7 @@ void IntprCallback::ExtendReg(unsigned int rd_idx, unsigned int rn_idx, unsigned
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}
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/* Load/Store */
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void IntprCallback::LoadReg(unsigned int rd_idx, unsigned int rm_idx, int size, bool extend, bool bit64) {
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if (bit64) {
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if (size == 4)
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X(rd_idx) = ARMv8::ReadU32 (X(rm_idx));
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if (size == 8)
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X(rd_idx) = ARMv8::ReadU64 (X(rm_idx));
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/* TODO: if (extend)
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ExtendReg(rd_idx, rd_idx, type, true); */
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} else {
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if (size == 4)
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W(rd_idx) = ARMv8::ReadU32 (W(rm_idx));
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/* TODO: if (extend)
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ExtendReg(rd_idx, rd_idx, type, true); */
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}
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}
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void IntprCallback::LoadRegImm64(unsigned int rd_idx, uint64_t addr, int size, bool extend, bool bit64) {
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static void _LoadReg(unsigned int rd_idx, uint64_t addr, int size, bool extend, bool bit64) {
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if (bit64) {
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if (size == 4)
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X(rd_idx) = ARMv8::ReadU32 (addr);
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@ -376,22 +360,7 @@ void IntprCallback::LoadRegImm64(unsigned int rd_idx, uint64_t addr, int size, b
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}
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}
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void IntprCallback::StoreReg(unsigned int rd_idx, unsigned int rm_idx, int size, bool extend, bool bit64) {
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if (bit64) {
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if (size == 4)
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ARMv8::WriteU32 (X(rm_idx), X(rd_idx));
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if (size == 8)
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ARMv8::WriteU64 (X(rm_idx), X(rd_idx));
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/* TODO: if (extend)
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ExtendReg(rd_idx, rd_idx, type, true); */
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} else {
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if (size == 4)
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ARMv8::WriteU32 (W(rm_idx), W(rd_idx));
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/* TODO: if (extend)
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ExtendReg(rd_idx, rd_idx, type, true); */
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}
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}
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void IntprCallback::StoreRegImm64(unsigned int rd_idx, uint64_t addr, int size, bool extend, bool bit64) {
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static void _StoreReg(unsigned int rd_idx, uint64_t addr, int size, bool extend, bool bit64) {
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if (bit64) {
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if (size == 4)
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ARMv8::WriteU32 (addr, X(rd_idx));
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@ -407,6 +376,91 @@ void IntprCallback::StoreRegImm64(unsigned int rd_idx, uint64_t addr, int size,
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}
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}
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void IntprCallback::LoadReg(unsigned int rd_idx, unsigned int base_idx, unsigned int rm_idx, int size,
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bool extend, bool post, bool writeback, bool bit64) {
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uint64_t addr;
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if (bit64) {
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if (post)
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addr = X(base_idx);
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else
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addr = X(base_idx) + X(rm_idx);
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_LoadReg (rd_idx, addr, size, extend, true);
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if (writeback)
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X(base_idx) = addr;
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} else {
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if (post)
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addr = W(base_idx);
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else
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addr = W(base_idx) + W(rm_idx);
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_LoadReg (rd_idx, addr, size, extend, false);
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if (writeback)
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W(base_idx) = addr;
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}
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}
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void IntprCallback::LoadRegImm64(unsigned int rd_idx, unsigned int base_idx, uint64_t offset, int size,
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bool extend, bool post, bool writeback, bool bit64) {
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uint64_t addr;
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if (bit64) {
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if (post)
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addr = X(base_idx);
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else
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addr = X(base_idx) + offset;
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_LoadReg (rd_idx, addr, size, extend, true);
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if (writeback)
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X(base_idx) = addr;
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} else {
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if (post)
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addr = W(base_idx);
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else
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addr = W(base_idx) + offset;
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_LoadReg (rd_idx, addr, size, extend, false);
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if (writeback)
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W(base_idx) = addr;
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}
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}
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void IntprCallback::StoreReg(unsigned int rd_idx, unsigned int base_idx, unsigned int rm_idx, int size,
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bool extend, bool post, bool writeback, bool bit64) {
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uint64_t addr;
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if (bit64) {
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if (post)
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addr = X(base_idx);
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else
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addr = X(base_idx) + X(rm_idx);
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_StoreReg (rd_idx, addr, size, extend, true);
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if (writeback)
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X(base_idx) = addr;
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} else {
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if (post)
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addr = W(base_idx);
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else
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addr = W(base_idx) + W(rm_idx);
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_StoreReg (rd_idx, addr, size, extend, false);
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if (writeback)
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W(base_idx) = addr;
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}
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}
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void IntprCallback::StoreRegImm64(unsigned int rd_idx, unsigned int base_idx, uint64_t offset, int size,
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bool extend, bool post, bool writeback, bool bit64) {
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uint64_t addr;
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if (bit64) {
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if (post)
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addr = X(base_idx);
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else
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addr = X(base_idx) + offset;
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_StoreReg (rd_idx, addr, size, extend, true);
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if (writeback)
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X(base_idx) = addr;
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} else {
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if (post)
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addr = W(base_idx);
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else
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addr = W(base_idx) + offset;
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_StoreReg (rd_idx, addr, size, extend, false);
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if (writeback)
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W(base_idx) = addr;
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}
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}
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/* Bitfield Signed/Unsigned Extract... with Immediate value */
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void IntprCallback::SExtractI64(unsigned int rd_idx, unsigned int rn_idx, unsigned int pos, unsigned int len, bool bit64) {
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/* TODO: */
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@ -9,8 +9,10 @@ typedef union {
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}reg_t;
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struct ARMv8State {
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reg_t gpr[33]; // x0 - x31 (x30 is usually "link regsiter" and x31 is "stack pointer" or "zero register" )
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uint64_t pc;
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reg_t gpr[34];
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/*
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* x0 - x31 (x30 is usually "link regsiter" and x31 is "stack pointer" or "zero register" )
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* NOTE: In nsemu, 'PC' register is respresented as x32 internally. */
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uint32_t nzcv; // flag register
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};
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@ -19,12 +21,13 @@ extern ARMv8State arm_state;
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#define GPR_LR 30
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#define GPR_SP 31
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#define GPR_ZERO 31
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#define GPR_DUMMY 32
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#define PC_IDX 32
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#define GPR_DUMMY 33
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#define LR ARMv8::arm_state.gpr[GPR_LR]
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#define SP ARMv8::arm_state.gpr[GPR_SP]
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#define ZERO ARMv8::arm_state.gpr[GPR_ZERO]
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#define PC ARMv8::arm_state.pc
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#define PC ARMv8::arm_state.gpr[PC_IDX].x // XXX: bit tricky
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#define NZCV ARMv8::arm_state.nzcv
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#define N_MASK 0x80000000
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#define Z_MASK 0x40000000
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@ -44,10 +44,10 @@ virtual void NotReg(unsigned int rd_idx, unsigned int rm_idx, bool bit64) = 0;
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virtual void ExtendReg(unsigned int rd_idx, unsigned int rn_idx, unsigned int extend_type, bool bit64) = 0;
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/* Load/Store */
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virtual void LoadReg(unsigned int rd_idx, unsigned int rm_idx, int size, bool extend, bool bit64) = 0;
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virtual void LoadRegImm64(unsigned int rd_idx, uint64_t addr, int size, bool extend, bool bit64) = 0;
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virtual void StoreReg(unsigned int rd_idx, unsigned int rm_idx, int size, bool extend, bool bit64) = 0;
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virtual void StoreRegImm64(unsigned int rd_idx, uint64_t addr, int size, bool extend, bool bit64) = 0;
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virtual void LoadReg(unsigned int rd_idx, unsigned int base_idx, unsigned int rm_idx, int size, bool extend, bool post, bool writeback, bool bit64) = 0;
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virtual void LoadRegImm64(unsigned int rd_idx, unsigned int base_idx, uint64_t offset, int size, bool extend, bool post, bool writeback, bool bit64) = 0;
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virtual void StoreReg(unsigned int rd_idx, unsigned int base_idx, unsigned int rm_idx, int size, bool extend, bool post, bool writeback, bool bit64) = 0;
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virtual void StoreRegImm64(unsigned int rd_idx, unsigned int base_idx, uint64_t offset, int size, bool extend, bool post, bool writeback, bool bit64) = 0;
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/* Bitfield Signed/Unsigned Extract... with Immediate value */
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virtual void SExtractI64(unsigned int rd_idx, unsigned int rn_idx, unsigned int pos, unsigned int len, bool bit64) = 0;
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@ -44,10 +44,10 @@ void NotReg(unsigned int rd_idx, unsigned int rm_idx, bool bit64);
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void ExtendReg(unsigned int rd_idx, unsigned int rn_idx, unsigned int extend_type, bool bit64);
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/* Load/Store */
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void LoadReg(unsigned int rd_idx, unsigned int rm_idx, int size, bool extend, bool bit64);
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void LoadRegImm64(unsigned int rd_idx, uint64_t addr, int size, bool extend, bool bit64);
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void StoreReg(unsigned int rd_idx, unsigned int rm_idx, int size, bool extend, bool bit64);
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void StoreRegImm64(unsigned int rd_idx, uint64_t addr, int size, bool extend, bool bit64);
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void LoadReg(unsigned int rd_idx, unsigned int base_idx, unsigned int rm_idx, int size, bool extend, bool post, bool writeback, bool bit64);
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void LoadRegImm64(unsigned int rd_idx, unsigned int base_idx, uint64_t offset, int size, bool extend, bool post, bool writeback, bool bit64);
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void StoreReg(unsigned int rd_idx, unsigned int base_idx, unsigned int rm_idx, int size, bool extend, bool post, bool writeback, bool bit64);
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void StoreRegImm64(unsigned int rd_idx, unsigned int base_idx, uint64_t offset, int size, bool extend, bool post, bool writeback, bool bit64);
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/* Bitfield Signed/Unsigned Extract... with Immediate value */
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void SExtractI64(unsigned int rd_idx, unsigned int rn_idx, unsigned int pos, unsigned int len, bool bit64);
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