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Fixed 64bit variant detection bug for load/store

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This commit is contained in:
rkx1209 2018-03-05 19:03:44 +09:00
parent d5ff88f6be
commit a5d8832222
2 changed files with 16 additions and 6 deletions
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10
ARMv8/Disassembler.cpp
View file

@ -753,7 +753,6 @@ static void DisasLdstRegRoffset(uint32_t insn, DisasCallback *cb,
bool is_signed = false;
bool is_store = false;
bool is_extended = false;
bool sf = DisasLdstCompute64bit (size, is_signed, opc);
if (extract32(opt, 1, 1) == 0) {
UnallocatedOp (insn);
@ -775,6 +774,7 @@ static void DisasLdstRegRoffset(uint32_t insn, DisasCallback *cb,
is_signed = extract32(opc, 1, 1);
is_extended = (size < 3) && extract32(opc, 0, 1);
}
bool sf = DisasLdstCompute64bit (size, is_signed, opc);
cb->ExtendReg (rm, rm, opt, sf);
cb->ShiftReg (rm, rm, ShiftType_LSL, shift ? size : 0, sf);
if (is_store) {
@ -804,7 +804,6 @@ static void DisasLdstRegImm9(uint32_t insn, DisasCallback *cb,
bool iss_valid = !is_vector;
bool post_index;
bool writeback;
bool sf = DisasLdstCompute64bit (size, is_signed, opc);
if (is_vector) {
UnsupportedOp ("LDR/STR [base, #imm9] (SIMD&FP)");
@ -825,7 +824,7 @@ static void DisasLdstRegImm9(uint32_t insn, DisasCallback *cb,
is_signed = extract32(opc, 1, 1);
is_extended = (size < 3) && extract32(opc, 0, 1);
}
bool sf = DisasLdstCompute64bit (size, is_signed, opc);
switch (idx) {
case 0:
case 2:
@ -862,7 +861,6 @@ static void DisasLdstRegUnsignedImm(uint32_t insn, DisasCallback *cb,
bool is_store;
bool is_signed = false;
bool is_extended = false;
bool sf = DisasLdstCompute64bit (size, is_signed, opc);
if (is_vector) {
UnsupportedOp ("LDR/STR [base, #simm12] (SIMD&FP)");
@ -879,6 +877,7 @@ static void DisasLdstRegUnsignedImm(uint32_t insn, DisasCallback *cb,
is_signed = extract32(opc, 1, 1);
is_extended = (size < 3) && extract32(opc, 0, 1);
}
bool sf = DisasLdstCompute64bit (size, is_signed, opc);
offset = imm12 << size;
if (is_store) {
cb->StoreRegImm64 (rt, rn, offset, size, is_extended, false, false, sf);
@ -936,7 +935,6 @@ static void DisasLdstPair(uint32_t insn, DisasCallback *cb) {
bool writeback = false;
int size;
bool sf = DisasLdstCompute64bit (size, is_signed, opc);
if (opc == 3) {
UnallocatedOp (insn);
@ -954,6 +952,8 @@ static void DisasLdstPair(uint32_t insn, DisasCallback *cb) {
}
}
bool sf = DisasLdstCompute64bit (size, is_signed, opc);
switch (index) {
case 0:
if (is_signed) {

12
ARMv8/Interpreter.cpp
View file

@ -334,6 +334,8 @@ void IntprCallback::BicReg(unsigned int rd_idx, unsigned int rn_idx, unsigned in
ArithmeticLogic (rd_idx, W(rn_idx), ~W(rm_idx), false, bit64, AL_TYPE_AND);
}
void IntprCallback::NotReg(unsigned int rd_idx, unsigned int rm_idx, bool bit64) {
char regc = bit64? 'X': 'W';
debug_print ("NOT: %c[%u] = ~%c[%u]\n", regc, rd_idx, regc, rm_idx);
if (bit64)
X(rd_idx) = ~X(rm_idx);
else
@ -347,7 +349,7 @@ void IntprCallback::ExtendReg(unsigned int rd_idx, unsigned int rn_idx, unsigned
static void _LoadReg(unsigned int rd_idx, uint64_t addr, int size, bool extend, bool bit64) {
if (bit64) {
if (size == 4)
X(rd_idx) = ARMv8::ReadU32 (addr);
W(rd_idx) = ARMv8::ReadU32 (addr);
if (size == 8)
X(rd_idx) = ARMv8::ReadU64 (addr);
/* TODO: if (extend)
@ -378,6 +380,8 @@ static void _StoreReg(unsigned int rd_idx, uint64_t addr, int size, bool extend,
void IntprCallback::LoadReg(unsigned int rd_idx, unsigned int base_idx, unsigned int rm_idx, int size,
bool extend, bool post, bool writeback, bool bit64) {
char regc = bit64? 'X': 'W';
debug_print ("Load(%d): %c[%u] <= [%c[%u], %c[%u]]\n", size, regc, rd_idx, regc, base_idx, regc, rm_idx);
uint64_t addr;
if (bit64) {
if (post)
@ -399,6 +403,8 @@ void IntprCallback::LoadReg(unsigned int rd_idx, unsigned int base_idx, unsigned
}
void IntprCallback::LoadRegImm64(unsigned int rd_idx, unsigned int base_idx, uint64_t offset, int size,
bool extend, bool post, bool writeback, bool bit64) {
char regc = bit64? 'X': 'W';
debug_print ("Load(%d): %c[%u] <= [%c[%u], 0x%16lx]\n", size, regc, rd_idx, regc, base_idx, offset);
uint64_t addr;
if (bit64) {
if (post)
@ -420,6 +426,8 @@ void IntprCallback::LoadRegImm64(unsigned int rd_idx, unsigned int base_idx, uin
}
void IntprCallback::StoreReg(unsigned int rd_idx, unsigned int base_idx, unsigned int rm_idx, int size,
bool extend, bool post, bool writeback, bool bit64) {
char regc = bit64? 'X': 'W';
debug_print ("Store(%d): %c[%u] => [%c[%u], %c[%u]]\n", size, regc, rd_idx, regc, base_idx, regc, rm_idx);
uint64_t addr;
if (bit64) {
if (post)
@ -441,6 +449,8 @@ void IntprCallback::StoreReg(unsigned int rd_idx, unsigned int base_idx, unsigne
}
void IntprCallback::StoreRegImm64(unsigned int rd_idx, unsigned int base_idx, uint64_t offset, int size,
bool extend, bool post, bool writeback, bool bit64) {
char regc = bit64? 'X': 'W';
debug_print ("Store(%d): %c[%u] => [%c[%u], 0x%16lx]\n", size, regc, rd_idx, regc, base_idx, offset);
uint64_t addr;
if (bit64) {
if (post)