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Fixed some bugs

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This commit is contained in:
rkx1209 2018-06-05 04:56:03 +09:00
parent f751c7d9e4
commit 3564c422b2
5 changed files with 34 additions and 35 deletions
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4
ARMv8/ARMv8.cpp
View file

@ -26,7 +26,7 @@ void RunLoop() {
void Dump() {
int cnt = 1;
ns_print ("CPU Dump:\n");
for (int r = 0; r < GPR_DUMMY; r++) {
for (int r = 0; r <= PC_IDX; r++) {
if (!X(r))
continue;
if (r == GPR_LR)
@ -35,8 +35,6 @@ void Dump() {
ns_print ("SP:\t");
else if (r == PC_IDX)
ns_print ("PC:\t");
else if (r == GPR_DUMMY)
ns_print ("DUM:\t");
else
ns_print ("X%d:\t", r);
ns_print ("0x%016lx%c", X(r), cnt % 3 == 0 ? '\n' : '\t');

26
ARMv8/Disassembler.cpp
View file

@ -61,19 +61,19 @@ static bool LogicImmDecode(uint64_t *wmask, unsigned int immn, unsigned int imms
static void DisasPCRelAddr(uint32_t insn, DisasCallback *cb) {
unsigned int rd, page;
uint64_t offset, base;
uint64_t offset;
page = extract32 (insn, 31, 1);
offset = sextract64 (insn, 5, 19);
offset = offset << 2 | extract32 (insn, 29, 2);
rd = extract32 (insn, 0, 5);
//base = PC - 4;
base = PC;
cb->MovReg (GPR_DUMMY, PC_IDX, true);
if (page) {
base &= ~0xfff;
cb->AndI64 (GPR_DUMMY, GPR_DUMMY, ~0xfff, false, true);
offset <<= 12;
}
cb->MoviI64 (rd, base + offset, true);
cb->AddI64 (GPR_DUMMY, GPR_DUMMY, offset, false, true);
cb->MovReg (rd, GPR_DUMMY, true);
}
static void DisasAddSubImm(uint32_t insn, DisasCallback *cb) {
@ -754,11 +754,11 @@ static void DisasDataProc3src(uint32_t insn, DisasCallback *cb) {
/* MADD(64bit), MSUB(64bit) */
src64 = true;
}
cb->MulReg (rd, rn, rm, is_signed, sf, src64);
cb->MulReg (GPR_DUMMY, rn, rm, is_signed, sf, src64);
if (is_sub)
cb->SubReg (rd, ra, rd, false, src64);
cb->SubReg (rd, ra, GPR_DUMMY, false, true);
else
cb->AddReg (rd, ra, rd, false, src64);
cb->AddReg (rd, ra, GPR_DUMMY, false, true);
}
}
@ -816,11 +816,7 @@ static void DisasCondSel(uint32_t insn, DisasCallback *cb) {
return;
}
bool cond_inv = false;
if (rn == 31 && rm == 31) {
/* CSET (CSINC <Wd>, WZR, WZR, invert(<cond>)) *
* CSETM (CSINV <Wd>, WZR, WZR, invert(<cond>)) */
cond = cond ^ 1; // i.e. invert(<cond>)
}
//debug_print("rn: %u, rm: %u, else_inc: %u, else_inv: %u cond: %u\n", rn, rm, else_inc, else_inv, cond);
cb->MovReg (GPR_DUMMY, rm, true);
if (else_inv) {
cb->NotReg (GPR_DUMMY, GPR_DUMMY, sf);
@ -1056,7 +1052,7 @@ static void DisasLdstRegRoffset(uint32_t insn, DisasCallback *cb,
bool is_vector) {
unsigned int rn = extract32(insn, 5, 5);
unsigned int shift = extract32(insn, 12, 1);
unsigned int rm = extract32(insn, 16, 5);
unsigned int rm = ARMv8::HandleAsSP (extract32(insn, 16, 5));
unsigned int opt = extract32(insn, 13, 3);
bool is_signed = false;
bool is_store = false;
@ -1086,7 +1082,7 @@ static void DisasLdstRegRoffset(uint32_t insn, DisasCallback *cb,
is_extended = (size < 3); //TODO: treat other case, size = 0, 1(8bit-> or 16bit->)
}
bool sf = DisasLdstCompute64bit (size, is_signed, opc);
cb->ExtendReg (GPR_DUMMY, rm, opt, sf); //FIXME: When rm == GPR_ZERO, it should be handled as GPR_SP
cb->ExtendReg (GPR_DUMMY, rm, opt, sf);
cb->ShiftI64 (GPR_DUMMY, GPR_DUMMY, ShiftType_LSL, shift ? size : 0, sf);
if (is_store) {
cb->StoreReg (rt, rn, GPR_DUMMY, size, is_signed, is_extended, false, sf);

28
ARMv8/Interpreter.cpp
View file

@ -21,8 +21,9 @@ int Interpreter::SingleStep() {
void Interpreter::Run() {
debug_print ("Running with Interpreter\n");
static uint64_t counter = 0;
uint64_t estimate = 3485900, mx = 100000;
//uint64_t estimate = 0, mx = 3420000;
//uint64_t estimate = 3500000, mx = 100000;
uint64_t estimate = 3490000, mx = 100000;
//uint64_t estimate = 0, mx = 100000;
while (Cpu::GetState () == Cpu::State::Running) {
if (GdbStub::enabled) {
if (GdbStub::cont) {
@ -320,7 +321,7 @@ void IntprCallback::MovReg(unsigned int rd_idx, unsigned int rn_idx, bool bit64)
/* Conditional mov between registers */
void IntprCallback::CondMovReg(unsigned int cond, unsigned int rd_idx, unsigned int rn_idx, unsigned int rm_idx, bool bit64) {
char regc = bit64? 'X': 'W';
debug_print ("MOV: %c[%u] = 0: %c[%u], 1: %c[%u]\n", regc, rd_idx, regc, rm_idx, regc, rn_idx);
debug_print ("MOV: %c[%u] = 0: %c[%u], 1: %c[%u], cond(%u)_hold: %d\n", regc, rd_idx, regc, rm_idx, regc, rn_idx, cond, CondHold(cond));
if (bit64) {
if (CondHold(cond))
X(rd_idx) = X(rn_idx);
@ -386,12 +387,12 @@ void IntprCallback::MulReg(unsigned int rd_idx, unsigned int rn_idx, unsigned in
X(rd_idx) = X(rn_idx) * X(rm_idx);
} else {
if (sign)
X(rd_idx) = (int64_t)((int32_t)W(rn_idx) * (int32_t)W(rm_idx));
X(rd_idx) = (int64_t)W(rn_idx) * (int64_t)W(rm_idx);
else
X(rd_idx) = W(rn_idx) * W(rm_idx);
X(rd_idx) = (uint64_t)W(rn_idx) * (uint64_t)W(rm_idx);
}
} else {
X(rd_idx) = (W(rn_idx) * W(rm_idx)) & 0xffffffff;
X(rd_idx) = W(rn_idx) * W(rm_idx);
}
}
//64bit * 64bit
@ -561,7 +562,7 @@ static void ExtendRegI64(unsigned int rd_idx, uint64_t imm, unsigned int option)
}
void IntprCallback::ExtendReg(unsigned int rd_idx, unsigned int rn_idx, unsigned int extend_type, bool bit64) {
char regc = bit64? 'X': 'W';
debug_print ("Extend: %c[%u] Ext(%c[%u])\n", regc, rd_idx, regc, rn_idx);
debug_print ("Extend(type %u): %c[%u] Ext(%c[%u])\n", extend_type, regc, rd_idx, regc, rn_idx);
if (bit64)
ExtendRegI64 (rd_idx, X(rn_idx), extend_type);
else
@ -615,7 +616,8 @@ void IntprCallback::LoadReg(unsigned int rd_idx, unsigned int base_idx, unsigned
char regc = bit64? 'X': 'W';
char regdc = size >= 4 ? 'Q' : (size < 3 ? 'W' : 'X');
base_idx = ARMv8::HandleAsSP (base_idx);
debug_print ("Load(%d): %c[%u] <= [%c[%u], %c[%u]](extend:%d, sign:%d)\n", size, regdc, rd_idx, regc, base_idx, regc, rm_idx, extend, is_sign);
debug_print ("Load(%d): %c[%u] <= [X[%u](0x%lx), %c[%u](0x%lx)](extend:%d, sign:%d)\n",
size, regdc, rd_idx, base_idx, X(base_idx), regc, rm_idx, X(rm_idx), extend, is_sign);
uint64_t addr;
if (bit64) {
if (post)
@ -625,9 +627,9 @@ void IntprCallback::LoadReg(unsigned int rd_idx, unsigned int base_idx, unsigned
_LoadReg (rd_idx, addr, size, is_sign, extend);
} else {
if (post)
addr = W(base_idx);
addr = X(base_idx);
else
addr = W(base_idx) + W(rm_idx);
addr = X(base_idx) + W(rm_idx);
_LoadReg (rd_idx, addr, size, is_sign, extend);
}
}
@ -642,7 +644,7 @@ void IntprCallback::StoreReg(unsigned int rd_idx, unsigned int base_idx, unsigne
char regc = bit64? 'X': 'W';
char regdc = size >= 4 ? 'Q' : (size < 3 ? 'W' : 'X');
base_idx = ARMv8::HandleAsSP (base_idx);
debug_print ("Store(%d): %c[%u] => [%c[%u], %c[%u]](extend:%d, sign:%d)\n", size, regdc, rd_idx, regc, base_idx, regc, rm_idx, extend, is_sign);
debug_print ("Store(%d): %c[%u] => [X[%u], %c[%u]](extend:%d, sign:%d)\n", size, regdc, rd_idx, base_idx, regc, rm_idx, extend, is_sign);
uint64_t addr;
if (bit64) {
if (post)
@ -652,9 +654,9 @@ void IntprCallback::StoreReg(unsigned int rd_idx, unsigned int base_idx, unsigne
_StoreReg (rd_idx, addr, size, is_sign, extend);
} else {
if (post)
addr = W(base_idx);
addr = X(base_idx);
else
addr = W(base_idx) + W(rm_idx);
addr = X(base_idx) + W(rm_idx);
_StoreReg (rd_idx, addr, size, is_sign, extend);
}
}

9
Memory.cpp
View file

@ -45,8 +45,11 @@ static bool inline IsStraight(uint64_t addr, size_t len) {
}
static RAMBlock* FindRamBlock(uint64_t addr, size_t len) {
debug_print("Find 0x%lx, 0x%x\n", addr, len);
for (int i = 0; i < regions.size(); i++) {
debug_print("region[%d] 0x%lx: 0x%x\n", i, regions[i]->addr, regions[i]->length);
if (regions[i]->addr <= addr && addr + len <= regions[i]->addr + regions[i]->length) {
debug_print("0x%lx, 0x%x => match %d\n", addr, len, i);
return regions[i];
}
}
@ -65,7 +68,7 @@ static void AddAnonRamBlock(uint64_t addr, size_t len, int perm) {
ns_abort("Failed to allocate new RAM Block\n");
}
RAMBlock *new_ram = new RAMBlock("[anon]", addr, len, raw, perm);
//ns_print("Add anonymous region [0x%lx, %d]\n", new_ram->addr, new_ram->length);
debug_print("Add anonymous region [0x%lx, %d]\n", new_ram->addr, new_ram->length);
regions.push_back(new_ram);
}
@ -131,12 +134,12 @@ void *GetRawPtr(uint64_t gpa, size_t len) {
void *emu_mem;
if (IsStraight(gpa, len)) {
emu_mem = (void *)&pRAM[gpa];
}
else {
} else {
RAMBlock *ram = FindRamBlock (gpa, len);
if (!ram) {
return nullptr;
}
debug_print("Uncontigious block\n");
emu_mem = (void *)&ram->block[gpa - ram->addr];
}
return emu_mem;

2
Svc.cpp
View file

@ -106,7 +106,7 @@ void Init() {
std::tuple<uint64_t, uint64_t> SetHeapSize(uint64_t size) {
ns_print("SetHeapSize 0x%lx\n", size);
if (Memory::heap_size < size) {
Memory::AddMemmap (Memory::heap_base, size - Memory::heap_size - 1);
Memory::AddMemmap (Memory::heap_base + Memory::heap_size, size - Memory::heap_size - 1);
} else if (Memory::heap_size > size) {
/* TODO: */
}