mirror of
https://github.com/extremscorner/not64.git
synced 2025-04-02 10:52:37 -04:00
261abf9f04
- Optimized load delay slots. - Optimized consecutive ULW/USW/ULD/USD instructions. - Optimized function argument passing. - Optimized memory operations with constant addresses.
506 lines
12 KiB
C
506 lines
12 KiB
C
/**
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* Wii64 - Wrappers.c
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* Copyright (C) 2008, 2009, 2010 Mike Slegeir
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*
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* Interface between emulator code and recompiled code
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*
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* Wii64 homepage: http://www.emulatemii.com
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* email address: tehpola@gmail.com
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*
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*
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* This program is free software; you can redistribute it and/
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* or modify it under the terms of the GNU General Public Li-
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* cence as published by the Free Software Foundation; either
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* version 2 of the Licence, or any later version.
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*
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* This program is distributed in the hope that it will be use-
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* ful, but WITHOUT ANY WARRANTY; without even the implied war-
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* ranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public Licence for more details.
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*
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**/
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#include <stdlib.h>
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#include "../../gui/DEBUG.h"
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#include "../Invalid_Code.h"
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#include "../ARAM-blocks.h"
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#include "../../gc_memory/memory.h"
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#include "../interupt.h"
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#include "../exception.h"
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#include "../r4300.h"
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#include "../macros.h"
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#include "../Recomp-Cache.h"
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#include "Recompile.h"
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#include "Wrappers.h"
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extern int stop;
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extern unsigned long instructionCount;
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extern void (*interp_ops[64])(void);
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inline unsigned long update_invalid_addr(unsigned long addr);
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unsigned int dyna_check_cop1_unusable(unsigned int, int);
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unsigned int dyna_mem(unsigned int, unsigned int, int, memType, unsigned int, int);
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int noCheckInterrupt = 0;
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static PowerPC_instr* link_branch = NULL;
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static PowerPC_func* last_func;
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/* Recompiled code stack frame:
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* $sp+12 |
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* $sp+8 | old cr
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* $sp+4 | old lr
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* $sp | old sp
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*/
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inline unsigned int dyna_run(PowerPC_func* func, PowerPC_instr* code){
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PowerPC_instr* return_addr;
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register void* r3 __asm__("r3");
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register void* r29 __asm__("r29") = rdram;
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register void* r30 __asm__("r30") = func;
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register void* r31 __asm__("r31") = NULL;
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end_section(TRAMP_SECTION);
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__asm__ volatile(
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"mtctr %4 \n"
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"bl 1f \n"
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"mflr %3 \n"
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"lwz %2, 12(1) \n"
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"addi 1, 1, 8 \n"
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"b 2f \n"
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"1: \n"
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"stwu 1, -8(1) \n"
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"mflr 0 \n"
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"stw 0, 12(1) \n"
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"bctr \n"
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"2: \n"
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: "=r" (r3), "=r" (r30), "=r" (return_addr), "=r" (link_branch)
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: "r" (code), "r" (r29), "r" (r30), "r" (r31)
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: "r0", "r2", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
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"fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", "fr8", "fr9", "fr10", "fr11", "fr12", "fr13",
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"lr", "ctr", "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", "ca");
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last_func = r30;
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link_branch = link_branch == return_addr ? NULL : link_branch - 1;
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return r3;
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}
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void dynarec(unsigned int address){
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while(!stop){
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refresh_stat();
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start_section(TRAMP_SECTION);
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PowerPC_block* dst_block = blocks_get(address>>12);
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unsigned long paddr = update_invalid_addr(address);
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/*
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sprintf(txtbuffer, "trampolining to 0x%08x\n", address);
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DEBUG_print(txtbuffer, DBG_USBGECKO);
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*/
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if(!paddr){
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link_branch = NULL;
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address = interp_addr;
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dst_block = blocks_get(address>>12);
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paddr = update_invalid_addr(address);
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}
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if(!dst_block){
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/*sprintf(txtbuffer, "block at %08x doesn't exist\n", address&~0xFFF);
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DEBUG_print(txtbuffer, DBG_USBGECKO);*/
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dst_block = calloc(1, sizeof(PowerPC_block));
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blocks_set(address>>12, dst_block);
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dst_block->start_address = address & ~0xFFF;
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dst_block->end_address = (address & ~0xFFF) + 0x1000;
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init_block(dst_block);
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} else if(invalid_code_get(address>>12)){
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invalidate_block(dst_block);
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}
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PowerPC_func* func = find_func(&dst_block->funcs, address);
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if(!func || !func->code_addr[(address-func->start_addr)>>2]){
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/*sprintf(txtbuffer, "code at %08x is not compiled\n", address);
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DEBUG_print(txtbuffer, DBG_USBGECKO);*/
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dst_block->mips_code = fast_mem_access(paddr & ~0xFFF);
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start_section(COMPILER_SECTION);
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func = recompile_block(dst_block, address);
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end_section(COMPILER_SECTION);
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} else {
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#ifdef USE_RECOMP_CACHE
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RecompCache_Update(func);
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#endif
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}
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int index = (address - func->start_addr)>>2;
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// Recompute the block offset
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PowerPC_instr* code = func->code_addr[index];
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// Create a link if possible
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if(link_branch && !func_was_freed(last_func))
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RecompCache_Link(last_func, link_branch, func, code);
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clear_freed_funcs();
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interp_addr = address = dyna_run(func, code);
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if(!noCheckInterrupt){
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last_addr = interp_addr;
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// Check for interrupts
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if(next_interupt <= Count){
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gen_interupt();
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address = interp_addr;
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}
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}
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noCheckInterrupt = 0;
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}
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interp_addr = address;
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}
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unsigned int decodeNInterpret(MIPS_instr mips, unsigned int pc,
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int isDelaySlot){
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delay_slot = isDelaySlot; // Make sure we set delay_slot properly
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PC->addr = interp_addr = pc;
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start_section(INTERP_SECTION);
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prefetch_opcode(mips);
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interp_ops[MIPS_GET_OPCODE(mips)]();
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end_section(INTERP_SECTION);
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delay_slot = 0;
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if(interp_addr != pc + 4) noCheckInterrupt = 1;
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return interp_addr != pc + 4 ? interp_addr : 0;
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}
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#ifdef COMPARE_CORE
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int dyna_update_count(unsigned int pc, int isDelaySlot){
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#else
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int dyna_update_count(unsigned int pc){
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#endif
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Count += ((pc - last_addr) >> 2) * count_per_op;
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last_addr = pc;
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#ifdef COMPARE_CORE
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if(isDelaySlot){
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interp_addr = pc;
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compare_core();
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}
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#endif
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return next_interupt - Count;
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}
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unsigned int dyna_check_cop1_unusable(unsigned int pc, int isDelaySlot){
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// Set state so it can be recovered after exception
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delay_slot = isDelaySlot;
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PC->addr = interp_addr = pc;
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// Take a FP unavailable exception
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Cause = (11 << 2) | 0x10000000;
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exception_general();
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// Reset state
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delay_slot = 0;
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noCheckInterrupt = 1;
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// Return the address to trampoline to
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return interp_addr;
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}
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void invalidate_func(unsigned int addr){
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if(!invalid_code_get(addr>>12)){
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PowerPC_block* block = blocks_get(addr>>12);
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PowerPC_func* func = find_func(&block->funcs, addr);
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if(func)
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RecompCache_Free(func->start_addr);
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}
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}
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unsigned int dyna_mem(unsigned int addr, unsigned int value, int count,
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memType type, unsigned int pc, int isDelaySlot){
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int i;
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PC->addr = interp_addr = pc;
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delay_slot = isDelaySlot;
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if(count < 1 || value + count > 32) abort();
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switch(type){
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case MEM_LW:
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addr &= ~3;
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case MEM_ULW:
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for(i = 0; i < count; i++){
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address = addr + i*4;
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read_word_in_memory();
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if(!address) break;
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reg[value + i] = (signed long)word;
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}
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break;
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case MEM_LWU:
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addr &= ~3;
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for(i = 0; i < count; i++){
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address = addr + i*4;
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read_word_in_memory();
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if(!address) break;
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reg[value + i] = word;
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}
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break;
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case MEM_LH:
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addr &= ~1;
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for(i = 0; i < count; i++){
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address = addr + i*2;
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read_hword_in_memory();
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if(!address) break;
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reg[value + i] = (signed short)hword;
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}
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break;
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case MEM_LHU:
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addr &= ~1;
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for(i = 0; i < count; i++){
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address = addr + i*2;
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read_hword_in_memory();
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if(!address) break;
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reg[value + i] = hword;
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}
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break;
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case MEM_LB:
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for(i = 0; i < count; i++){
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address = addr + i;
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read_byte_in_memory();
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if(!address) break;
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reg[value + i] = (signed char)byte;
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}
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break;
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case MEM_LBU:
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for(i = 0; i < count; i++){
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address = addr + i;
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read_byte_in_memory();
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if(!address) break;
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reg[value + i] = byte;
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}
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break;
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case MEM_LD:
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addr &= ~7;
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case MEM_ULD:
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for(i = 0; i < count; i++){
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address = addr + i*8;
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read_dword_in_memory();
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if(!address) break;
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reg[value + i] = dword;
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}
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break;
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case MEM_LWC1:
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addr &= ~3;
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for(i = 0; i < count; i++){
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address = addr + i*4;
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read_word_in_memory();
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if(!address) break;
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*((long*)reg_cop1_simple[value + i*2]) = word;
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}
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break;
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case MEM_LDC1:
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addr &= ~7;
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for(i = 0; i < count; i++){
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address = addr + i*8;
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read_dword_in_memory();
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if(!address) break;
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*((long long*)reg_cop1_double[value + i*2]) = dword;
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}
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break;
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case MEM_LL:
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address = addr &= ~3;
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read_word_in_memory();
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if(!address) break;
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reg[value] = (signed long)word;
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llbit = 1;
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break;
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case MEM_LLD:
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address = addr &= ~7;
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read_dword_in_memory();
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if(!address) break;
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reg[value] = dword;
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llbit = 1;
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break;
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case MEM_LWL:
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address = addr & ~3;
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read_word_in_memory();
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if(!address) break;
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if((addr & 3) == 0){
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reg[value] = (signed long)word;
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} else {
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u32 shift = (addr & 3) * 8;
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u32 mask = 0xFFFFFFFF << shift;
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reg[value] = (signed long)((reg[value] & ~mask) | ((word << shift) & mask));
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}
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break;
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case MEM_LWR:
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address = (addr + 3) & ~3;
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read_word_in_memory();
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if(!address) break;
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if((-addr & 3) == 0){
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reg[value] = (signed long)word;
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} else {
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u32 shift = (-addr & 3) * 8;
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u32 mask = 0xFFFFFFFF >> shift;
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reg[value] = (signed long)((reg[value] & ~mask) | ((word >> shift) & mask));
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}
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break;
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case MEM_LDL:
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address = addr & ~7;
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read_dword_in_memory();
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if(!address) break;
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if((addr & 7) == 0){
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reg[value] = dword;
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} else {
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u32 shift = (addr & 7) * 8;
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u64 mask = 0xFFFFFFFFFFFFFFFFLL << shift;
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reg[value] = (reg[value] & ~mask) | ((dword << shift) & mask);
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}
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break;
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case MEM_LDR:
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address = (addr + 7) & ~7;
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read_dword_in_memory();
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if(!address) break;
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if((-addr & 7) == 0){
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reg[value] = dword;
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} else {
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u32 shift = (-addr & 7) * 8;
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u64 mask = 0xFFFFFFFFFFFFFFFFLL >> shift;
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reg[value] = (reg[value] & ~mask) | ((dword >> shift) & mask);
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}
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break;
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case MEM_SW:
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addr &= ~3;
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case MEM_USW:
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for(i = 0; i < count; i++){
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address = addr + i*4;
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word = reg[value + i];
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write_word_in_memory();
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}
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invalidate_func(addr);
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break;
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case MEM_SH:
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addr &= ~1;
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for(i = 0; i < count; i++){
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address = addr + i*2;
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hword = reg[value + i];
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write_hword_in_memory();
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}
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invalidate_func(addr);
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break;
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case MEM_SB:
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for(i = 0; i < count; i++){
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address = addr + i;
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byte = reg[value + i];
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write_byte_in_memory();
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}
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invalidate_func(addr);
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break;
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case MEM_SD:
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addr &= ~7;
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case MEM_USD:
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for(i = 0; i < count; i++){
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address = addr + i*8;
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dword = reg[value + i];
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write_dword_in_memory();
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}
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invalidate_func(addr);
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break;
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case MEM_SWC1:
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addr &= ~3;
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for(i = 0; i < count; i++){
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address = addr + i*4;
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word = *((long*)reg_cop1_simple[value + i*2]);
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write_word_in_memory();
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}
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invalidate_func(addr);
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break;
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case MEM_SDC1:
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addr &= ~7;
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for(i = 0; i < count; i++){
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address = addr + i*8;
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dword = *((long long*)reg_cop1_double[value + i*2]);
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write_dword_in_memory();
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}
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invalidate_func(addr);
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break;
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case MEM_SC:
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if(llbit){
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address = addr &= ~3;
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word = reg[value];
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write_word_in_memory();
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invalidate_func(addr);
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}
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reg[value] = !!llbit;
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llbit = 0;
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break;
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case MEM_SCD:
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if(llbit){
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address = addr &= ~7;
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dword = reg[value];
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write_dword_in_memory();
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invalidate_func(addr);
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}
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reg[value] = !!llbit;
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llbit = 0;
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break;
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case MEM_SWL:
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address = addr & ~3;
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read_word_in_memory();
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if((addr & 3) == 0){
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word = reg[value];
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} else {
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u32 shift = (addr & 3) * 8;
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u32 mask = 0xFFFFFFFF >> shift;
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word = (word & ~mask) | ((reg[value] >> shift) & mask);
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}
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write_word_in_memory();
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invalidate_func(addr);
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break;
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case MEM_SWR:
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address = (addr + 3) & ~3;
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read_word_in_memory();
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if((-addr & 3) == 0){
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word = reg[value];
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} else {
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u32 shift = (-addr & 3) * 8;
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u32 mask = 0xFFFFFFFF << shift;
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word = (word & ~mask) | ((reg[value] << shift) & mask);
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}
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write_word_in_memory();
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invalidate_func(addr);
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break;
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case MEM_SDL:
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address = addr & ~7;
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read_dword_in_memory();
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if((addr & 7) == 0){
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dword = reg[value];
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} else {
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u32 shift = (addr & 7) * 8;
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u64 mask = 0xFFFFFFFFFFFFFFFFLL >> shift;
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dword = (dword & ~mask) | ((reg[value] >> shift) & mask);
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}
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write_dword_in_memory();
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invalidate_func(addr);
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break;
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case MEM_SDR:
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address = (addr + 7) & ~7;
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read_dword_in_memory();
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if((-addr & 7) == 0){
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dword = reg[value];
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} else {
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u32 shift = (-addr & 7) * 8;
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u64 mask = 0xFFFFFFFFFFFFFFFFLL << shift;
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dword = (dword & ~mask) | ((reg[value] << shift) & mask);
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}
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write_dword_in_memory();
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invalidate_func(addr);
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break;
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default:
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abort();
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break;
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}
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delay_slot = 0;
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if(interp_addr != pc) noCheckInterrupt = 1;
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return interp_addr != pc ? interp_addr : 0;
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}
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